CN108336895B

CN108336895B - DC-DC converter, DC-DC power conversion system and method

Info

Publication number: CN108336895B
Application number: CN201810046838.2A
Authority: CN
Inventors: P·J·哈里曼; A·博内利; D·罗密欧
Original assignee: Semiconductor Components Industries LLC
Current assignee: Semiconductor Components Industries LLC
Priority date: 2017-01-18
Filing date: 2018-01-17
Publication date: 2021-03-19
Anticipated expiration: 2038-01-17
Also published as: CN108336895A

Abstract

The invention relates to a DC-DC converter, a DC-DC power conversion system and a method. The invention discloses a DC-DC converter including an output power stage and a driver circuit. The output stage switches an input voltage to a switch node using a first transistor in response to a top gate signal received at a top gate node and switches the switch node to ground potential using a second transistor in response to a bottom gate signal received at a bottom gate node. The driver circuit provides a top gate signal and a bottom gate signal in response to the high-side switch signal and the low-side switch signal, respectively, activates the top gate signal by actively adjusting the top gate node to a first voltage between a threshold voltage and a breakdown voltage of the first transistor using charge from the bottom gate node, and activates the bottom gate signal by actively adjusting a second voltage provided to the bottom gate node between a threshold voltage and a breakdown voltage of the second transistor using charge from the top gate node.

Description

DC-DC converter, DC-DC power conversion system and method

Technical Field

The present disclosure relates generally to power conversion circuits, and more particularly to DC-DC converters.

Background

A DC-DC converter is a power converter that converts one Direct Current (DC) voltage to another DC voltage. Although several DC-DC converter topologies exist, such as Low Dropout (LDO), capacitive, and hysteretic types, one common approach is a switch-mode DC-DC converter. A switch mode DC-DC converter uses a Pulse Width Modulation (PWM) switch in series with an inductive element and varies the duty cycle of the switch to determine the output voltage, and uses a feedback voltage to regulate the output voltage to a desired level.

A DC-DC converter is called a buck converter if it converts an input voltage from a higher voltage to a lower output voltage. A typical switch-mode buck converter selectively connects a first terminal of an inductor to an input voltage or ground potential to regulate an output voltage at a second terminal of the inductor to a desired level.

It is desirable to operate the switch mode DC-DC converter at a higher switching frequency to reduce the size of the output filter. However, system efficiency may drop at higher switching frequencies due to increased switching losses associated with Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) used to switch the current flowing through the inductor. These switching losses are particularly undesirable in low voltage battery powered devices because the additional switching losses shorten battery life.

Disclosure of Invention

A first aspect of the present invention provides a DC-DC converter comprising: a dead-time control circuit having an input for receiving a pulse width modulated signal, a first output for providing a high-side switching signal, and a second output for providing a low-side switching signal; an output power stage to receive an input voltage and to switch the input voltage to a switch node using a first transistor in response to a top gate signal received at a top gate node and to switch the switch node to ground potential using a second transistor in response to a bottom gate signal received at a bottom gate node; and a driver circuit to provide the top gate signal and the bottom gate signal in response to the high-side switch signal and the low-side switch signal, respectively, the driver circuit to activate the top gate signal by actively adjusting the top gate node to a first voltage between a threshold voltage and a breakdown voltage of the first transistor using charge from the bottom gate node, and to activate the bottom gate signal by actively adjusting a second voltage provided to the bottom gate node between a threshold voltage and a breakdown voltage of the second transistor using charge from the top gate node.

A second aspect of the present invention provides a DC-DC power conversion system, comprising: an error amplifier having a first input for receiving a feedback signal, a second input for receiving a reference voltage, and an output; an oscillator having an output for providing a clock signal; and a pulse width modulator having a control input coupled to the output of the error amplifier, a clock input for receiving the clock signal, and an output for providing a pulse width modulator signal; a dead-time control circuit having an input for receiving a pulse width modulated signal, a first output for providing a high-side switching signal, and a second output for providing a low-side switching signal; an output power stage to receive an input voltage and to switch the input voltage to a switch node using a first transistor in response to a top gate signal received at a top gate node and to switch the switch node to ground potential using a second transistor in response to a bottom gate signal received at a bottom gate node; and a driver circuit to provide the top gate signal and the bottom gate signal in response to the high-side switch signal and the low-side switch signal, respectively, the driver circuit to activate the top gate signal by actively adjusting the top gate node to a first voltage between a threshold voltage and a breakdown voltage of the first transistor using charge from the bottom gate node, and to activate the bottom gate signal by actively adjusting a second voltage provided to the bottom gate node between a threshold voltage and a breakdown voltage of the second transistor using charge from the top gate node.

A third aspect of the invention provides a method comprising: receiving a pulse width modulation signal; providing a high-side switching signal and a low-side switching signal having a dead time therebetween in response to the pulse width modulated signal; driving a top gate node coupled to a gate of a first transistor by actively adjusting the top gate node to a first voltage between a threshold voltage and a breakdown voltage of the first transistor using charge from a bottom gate node coupled to a gate of a second transistor in response to the high-side switch signal; and driving the bottom gate node in response to the low-side switching signal by actively regulating the bottom gate node to a second voltage between a threshold voltage and a breakdown voltage of the second transistor using charge from the top gate node.

Drawings

The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings, wherein:

fig. 1 shows in partial block diagram and partial schematic form a DC-DC converter known in the prior art;

fig. 2 shows in partial block diagram and partial schematic form a DC-DC converter with charge sharing as known in the prior art;

fig. 3 shows in partial block diagram and partial schematic form another DC-DC converter with charge sharing known in the prior art;

FIG. 4 illustrates, in partial block diagram and partial schematic form, a power conversion system having a DC-DC converter in accordance with various embodiments of the present invention;

fig. 5 shows in partial block diagram and partial schematic form a part of a DC-DC converter according to an embodiment of the DC-DC converter of fig. 4.

Fig. 6 shows in partial block diagram and partial schematic form a part of a DC-DC converter according to another embodiment of the DC-DC converter of fig. 4.

Fig. 7 shows, in partial block diagram and partial schematic form, a part of a DC-DC converter according to a further embodiment of the DC-DC converter of fig. 4.

The use of the same reference symbols in different drawings indicates the same or similar elements. Unless otherwise stated, the word "coupled" and its associated verb form includes both a direct connection and an indirect electrical connection through means known in the art; and unless otherwise indicated, any description of a direct connection implies an alternative implementation using an indirect electrical connection of suitable form.

Detailed Description

Fig. 1 shows a DC-DC converter 100 known in the prior art in partial block diagram and partial schematic form. The DC-DC converter 100 includes an input capacitor 105, a dead time control circuit 110, a driver circuit 120, an output power stage 130, an inductanceA capacitor 140, and a capacitor 150. The input capacitor 105 has a capacitor for receiving a voltage labeled "V_{Input device}"and a second terminal connected to ground potential. As used herein, "ground" is a voltage reference that forms circuit common and has a nominal voltage of 0 volts, and may be implemented using ground or another suitable voltage (such as an analog ground or a virtual ground).

The dead-time control circuit 110 has an input terminal for receiving a pulse width modulated signal labeled "PWM", a first output terminal for providing a high-side switching signal labeled "HSS", and a second output terminal for providing a low-side switching signal labeled "LSS". Driver circuit 120 includes a P-channel Metal Oxide Semiconductor (MOS) transistor 122, an N-channel MOS transistor 124, a P-channel MOS transistor 126, and an N-channel MOS transistor 128. Transistor 122 has a gate for receiving V_{Input device}A gate for receiving a signal HSS, and a drain for providing a signal labeled "TG". Transistor 124 has a drain connected to the drain of transistor 122, a gate for receiving signal HSS, and a source connected to ground potential. Transistor 126 has a transistor for receiving V_{Input device}A gate for receiving a signal LSS, and a drain for providing a signal labeled "BG". Transistor 128 has a drain connected to the drain of transistor 126, a gate for receiving signal LSS, and a source connected to ground potential. Output power stage 130 includes a P-channel MOS transistor 132 and an N-channel MOS transistor 134. Transistor 132 has a transistor for receiving V_{Input device}A gate for receiving a TG signal, and a drain. The transistor 134 has a drain connected to the drain of the transistor 132, a gate for receiving a TG signal, and a source connected to a ground potential.

Inductor 140 has a first terminal connected to the drains of

transistors

132 and 134, and is used to provide a load (not shown in FIG. 1) with a voltage labeled "V_{Output of}"a second terminal of the output voltage. Capacitor 150 has a first terminal connected to the second terminal of inductor 140, and a second terminal connected to ground potential。

The DC-DC converter 100 is to convert a relatively large input voltage V_{Input device}(e.g., between 2.5 and 5.0 volts) to a smaller output voltage V_{Output of}(e.g., between 0.3 and 1.3 volts). During a first portion of the switching cycle, the driver circuit 120 makes the transistor 132 conductive to drive current into the inductor 140 and increase the magnetic flux stored in the inductor 140 while the transistor 134 is non-conductive. During the second portion of the switching cycle, the driver circuit 120 makes the transistor 134 conductive to reduce the flux stored in the inductor 140 and drive current into the load and the capacitor 150, while the transistor 132 is non-conductive. The DC-DC converter 100 operates in a closed loop to output the voltage V by varying the duty cycle of the PWM signal using conventional components not shown in fig. 1_{Output of}Adjust to the desired level. Dead time control circuit 110 ensures a safe non-overlap time between the first and second cycles such that

transistors

132 and 134 are not conductive at the same time and thereby avoid shoot-through current.

Transistors

132 and 134 are power MOS transistors with large gate areas so they can switch large amounts of current. Due to the large gate area, output power stage 130 repeatedly charges and discharges a large gate capacitance on the gates of

transistors

132 and 134. The amount of power consumed by the charging operation and the discharging operation increases as the switching frequency increases.

The dead time control circuit 110 and the driver circuit 120 operate as follows. During the first portion of the switching cycle, dead-time control circuit 110 makes transistor 122 non-conductive while transistor 124 is conductive to form a conductive path from the gate of transistor 132 to ground potential to leak charge from the gate of transistor 132 and reduce the voltage on the gate to make it conductive. Dead-time control circuit 110 also makes transistor 126 non-conductive and makes transistor 128 conductive to leak charge from the gate of transistor 134 to ground potential and lower the voltage on the gate to make it non-conductive. Thus during the first portion of the switching cycle, the driver circuit 120 makes the transistor 132 conductive and the transistor 134 non-conductive to drive current into the inductor 140. At about the end of the first portion of the switching cycle, dead-time control circuit 110 renders transistor 124 non-conductive and renders transistor 122 conductive to charge the gate of transistor 132 to a voltage high enough to render transistor 132 non-conductive while maintaining transistor 134 non-conductive.

During the second portion of the switching cycle, dead-time control circuit 110 makes transistor 126 conductive and transistor 128 non-conductive, and driver circuit 120 forms slave V_{Input device}A conductive path to the gate of transistor 134. This conductive path charges the gate of transistor 134 and makes it conductive. The driver circuit 120 therefore makes the transistor 134 conductive to connect the first terminal of the inductor 140 to ground potential while the transistor 132 remains non-conductive. At about the end of the second portion of the switching cycle, dead-time control circuit 110 renders transistor 126 non-conductive and transistor 128 conductive to allow charge to leak from the gate of transistor 134 to ground potential.

The dead time control circuit 110 repeats this pattern in subsequent switching cycles. The voltage control loop varies the duty cycle of the PWM signal to maintain V regulated to a desired level_{Output of}。

For even medium power applications, this repeated charging and discharging of the gates of

transistors

132 and 134 results in significant power consumption, which tends to shorten battery life. The switching losses are proportional to the switching frequency and the increased power consumption counteracts the other benefits of using a higher switching frequency. Switching power loss P_SWCan be expressed as the following equation [1]The estimates shown in (a) are:

P_SW＝1/2(C_HSS+C_LSS)V²f≈CV²f [1]

wherein C is_HSSGate capacitance of high-side switch, C_LSSIs the gate capacitance of the low-side switch, V is the input voltage, and f is the switching frequency, and C ═ C_HSS+C_LSS。

Fig. 2 shows in partial block diagram and partial schematic form a DC-DC converter 200 with charge sharing as known in the prior art. The DC-DC converter 200 includes an input capacitor 105, a driver circuit 220, an output power stage 230, an inductor 140, and a capacitor 150.

Driver circuit 220 includes a high-side driver 222, a low-side driver 224, and a capacitor 226. The high-side driver 222 has an input for receiving a signal HSS, an output for receiving V_{Input device}And a negative power supply terminal. Low-side driver 224 has an input for receiving signal LSS, an output, a positive power supply terminal connected to the negative power supply terminal of high-side driver 222, and a negative power supply terminal connected to ground potential. Capacitor 226 has a first terminal connected to the negative power terminal of high-side driver 222 and to the positive power terminal of low-side driver 224 and receives a signal having a voltage V_{Input device}Nominal value of/2 is marked as "V_Biasing"and the second terminal is connected to ground potential.

Output power stage 230 includes P-

channel MOS transistors

232 and 234, and N-

channel MOS transistors

236 and 238. Transistor 232 has a transistor for receiving V_{Input device}A gate connected to the output of the high-side driver 222, and a drain. Transistor 234 has a source connected to the drain of transistor 232, a gate connected to the first terminal of capacitor 226, and a drain. Transistor 236 has a drain connected to the drain of transistor 234, a gate connected to the first terminal of capacitor 226, and a source. Transistor 238 has a drain connected to the source of transistor 236, a gate connected to the output of low-side driver 224, and a drain connected to ground potential.

The DC-DC converter 200 uses a stacked cascode design in which the switching

transistors

232 and 238 and the

transistors

234 and 236 are cascode. The dead time control circuit and driver circuit 220 operates as follows. During a first portion of the switching cycle, the dead-time control circuit provides each of the signals HSS and LSS in a high state. The high side driver 222 discharges the gate of transistor 232 to V_{Input device}/2Thereby making transistor 232 conductive. The low-side driver 224 discharges the gate of transistor 238 to ground, thereby keeping transistor 238 non-conductive.

Transistors

234 and 236 are cascode transistors that reduce the voltage swing on the drains of their respective transistors. At about the end of the first portion of the switching cycle, the dead-time control circuit renders the transistor 232 non-conductive by: the gate of transistor 232 is charged to a sufficiently high voltage so that transistor 232 is non-conductive while transistor 238 is kept non-conductive.

During the second portion of the switching cycle, the dead-time control circuit forms a conductive path from the supply voltage terminal of the low-side driver 224 to the gate of the transistor 238 to provide V_{Input device}/2. This conductive path charges and makes the gate of transistor 238 conductive, and driver circuit 220 makes transistor 238 conductive to connect the first terminal of inductor 140 to ground potential while transistor 232 remains non-conductive. At about the end of the second portion of the switching cycle, the dead-time control circuit drives LSS low so that low-side driver 224 provides charge to the gate of transistor 238 and provides V to the gate of transistor 238_{Input device}A voltage of/2.

Driver circuit 220 thus reduces the voltage swing on the gates of the switching transistors in output power stage 230 by about half, thereby reducing switching losses. However, the transistors in the output power stage 230 must be able to withstand at least about V_{Input device}A voltage swing of/2 and is rated for that voltage swing.

Fig. 3 shows in partial block diagram and partial schematic form another DC-DC converter 300 with charge sharing known in the prior art. The DC-DC converter 300 includes the driver circuit 220, the inductor 140 and the capacitor 150 as shown in fig. 2, but uses a different output power stage 330 that will now be described.

Output power stage 330 includes a P-channel MOS transistor 332, an N-channel MOS transistor 334, and diode-connected N-

channel MOS transistors

336 and 338. The transistor 332 has a transistor for receiving V_{Input device}Source electrode of, gate for receiving TG signalA pole, and a drain connected to a first terminal of inductor 140. Transistor 334 has a drain connected to the drain of transistor 332 and to the first terminal of inductor 140, a gate for receiving the BG signal, and a source connected to ground potential. Transistor 336 has a drain connected to the first terminal of capacitor 226, a gate connected to its drain, and a source. Transistor 338 has a drain connected to the source of transistor 336, a gate connected to the drain, and a source connected to the drains of

transistors

332 and 334 and to the first terminal of inductor 140.

The DC-DC converter 300 provides gate charge reuse to reduce switching losses. Additionally,

transistors

332 and 334 are high voltage transistors capable of withstanding a voltage swing of, for example, 1.8 volts. However, will be composed of V_BiasingThe use of biased nodes with

transistors

332 and 334 greatly increases the on-resistance of these transistors because they are biased only to V_{Input device}And due to the high on-resistance, the power consumption due to conduction losses also increases correspondingly. In addition, the gate discharge path is unbalanced between the high-side and low-side transistors, and excess gate charge flow is drained onto the output stage switching node at the drains of

transistors

332 and 334. Specifically, the DC-DC converter 300 causes the charge on the gate of transistor 332 to leak through diode-connected

transistors

336 and 338 into the switch node at the drains of

transistors

332 and 334.

Fig. 4 illustrates, in partial block diagram and partial schematic form, a DC-DC power conversion system 400 having a DC-DC converter 410 in accordance with various embodiments of the present invention. In addition to DC-DC converter 410, DC-DC power conversion system 400 includes inductor 430, capacitor 440, feedback network 450, load 460, and compensation network 470.

The DC-DC converter 410 is an integrated circuit having a set of terminals, an error amplifier 412, an oscillator 414, a pulse width modulator 416, a dead time control circuit 418, a driver circuit 420, and an output power stage 422. Error amplifier 412 has a non-inverting input connected to the feedback terminal labeled "FB", an inverting input for receiving a reference voltage labeled "VREFAn input terminal, and an output terminal connected to a compensation terminal labeled "COMP". The oscillator 414 has an output for providing a clock signal. The clock signal may be, for example, a periodic sawtooth signal. The pulse width modulator 416 has a first input connected to the output of the error amplifier 412, a second input connected to the output of the oscillator 414, and an output for providing a PWM signal. The dead time control circuit has an input for receiving a PWM signal connected to the output of the pulse width modulator 416, a first output for providing a HSS signal, and a second output for providing an LSS signal. The driver circuit 420 has a first input for receiving the HSS signal, a second input for receiving the LSS signal, a first output for providing the TG signal, a second output for providing the BG signal, a first output for receiving the V signal from the corresponding integrated circuit terminal_{Input device}A positive supply terminal for voltage, and a negative supply terminal connected to a ground terminal labeled "GND". The output power stage 422 has a first input for receiving the TG signal, a second input for receiving the BG signal, an output connected to a switch node terminal labeled "SWN", an output for receiving V_{Input device}A positive power supply terminal for signals, and a negative power supply terminal connected to a ground terminal labeled "GND".

The inductor 430 has a first terminal connected to the SWN terminal of the DC-DC converter 410, and is for providing an output voltage V_{Output of}And a second terminal of (1). Capacitor 440 has a first terminal connected to the second terminal of inductor 430, and a second terminal connected to ground potential.

Feedback network 450 includes

resistors

452 and 454. Resistor 452 has a first terminal connected to the second terminal of inductor 430 and a second terminal connected to the non-inverting input of error amplifier 412 through terminal FB. Resistor 454 has a first terminal connected to the second terminal of resistor 452, and a second terminal connected to ground potential. Load 460 has a first terminal connected to the second terminal of inductor 430, and a second terminal connected to ground potential.

The compensation network 470 includes a resistor 472 and a capacitor 474. Resistor 472 has a first terminal connected to the output of error amplifier 412 at the COMP terminal, and a second terminal. Capacitor 474 has a first terminal connected to the second terminal of resistor 472, and a second terminal connected to ground potential.

The DC-DC power conversion system 400 is a step-down DC-DC converter that uses an integrated circuit DC-DC converter 410 having several external components. Which provides the feedback signal FB by using a resistor divider formed by

resistors

452 and 454 to divide V_{Output of}Is adjusted to the desired level. The voltage control loop is stabilized by a compensation network formed by resistor 472 and capacitor 474. The DC-DC converter 410 includes five terminals or pins, including an input voltage terminal V_{Input device}Ground terminal GND, switch node terminal SWN, feedback terminal FB, and compensation terminal COMP. The DC-DC converter 410 uses a driver circuit 420 connected between the dead-time control circuit 418 and the output power stage 422 to enable gate charge reuse and reduce power consumption through charge sharing in the driver.

Fig. 5 shows, in partial block diagram and partial schematic form, a portion of a DC-DC converter 500 according to an embodiment of the DC-DC converter 410 of fig. 4. The DC-DC converter 500 includes a dead-time control circuit 418, a driver circuit 420, and an output power stage 422. Also shown in fig. 5 is the supply of voltage V to a load (not shown in fig. 5)_{Output of} Inductor 430 and capacitor 440.

Dead-time control circuit 418 has an input for receiving the PWM signal, a first output for providing the HSS signal, and a second output for providing the LSS signal. Driver circuit 420 includes a high-side driver 530, a capacitor 540, and a low-side driver 550. High side driver 530 includes driver 532, P-channel MOS transistor 534, and voltage source 536. Driver 532 has an input terminal for receiving HSS signal, an output terminal for providing TG signal, and a terminal for receiving V_{Input device}And an inverting driver of the negative power supply terminal. Transistor 534 has a source connected to the negative power supply terminal of driver 532, a gate connected to intermediate node 542, and a drain. The voltage source 536 hasFor receiving V_{Input device}And a negative terminal connected to the gate of transistor 534. Capacitor 540 has a first terminal connected to intermediate node 542, and a second terminal connected to a ground potential. Low-side driver 550 includes an N-channel MOS transistor 552, a driver 554, and a voltage source 556. Transistor 552 has a drain, a gate, and a drain connected to intermediate node 542. Driver 554 has an input for receiving the LSS signal, an output, a positive power supply terminal connected to the source of transistor 552, and a negative power supply terminal connected to ground potential. The voltage source 556 has a positive terminal connected to the gate of the transistor 552, and a negative terminal connected to ground potential.

The output power stage 422 includes

transistors

562 and 564. The transistor 562 has a transistor for receiving a voltage V_{Input device}A gate connected to an output terminal of the driver 532 for receiving a signal TG, and a drain connected to the SWN node. Transistor 564 has a drain connected to node SWN and to the drain of transistor 562, a gate connected to the output of driver 554 for receiving signal BG, and a source connected to ground potential. In the DC-DC converter 500, the

transistors

534, 552, 562, and 564 are implemented as laterally diffused mos (ldmos) transistors. The LDMOS transistor has a lower threshold voltage and a voltage/current characteristic with a smaller slope than a normal MOS transistor.

In the DC-DC converter 500, the driver circuit 420 includes a high-side driver portion and a low-side driver portion that regulate the voltage swing on the gate of the LDMOS transistor in the output power stage 422 while reusing the gate charge. Capacitor 540 is connected to intermediate node 542 and operates as a tank capacitor. Capacitor 540 operates as a charge pump that stores charge as it is removed from the gate of transistor 562 to render transistor 562 conductive and transfers the stored charge onto the gate of transistor 564 to render transistor 564 conductive. The

transistors

534 and 552 are also LDMOS transistors that operate as source followers to limit the voltage swing on the gates of the

respective transistors

562 and 564 in the output power stage 422.

High side driver 530 provides a gate interface to transistor 562A voltage swing between: v when HSS is low and TG is high_DDAnd an adjusted voltage when HSS is high and TG is low, which is equal to the voltage on the gate of transistor 534 minus the threshold voltage of transistor 534. This voltage swing allows transistor 562 to become fully conductive and biased above its threshold voltage to keep its on-resistance low, while also draining charge onto intermediate node 542 when driver circuit 420 makes transistor 562 conductive.

Similarly, low-side driver 550 provides a voltage swing on the gate of transistor 564 that is between: the voltage at the gate of transistor 552 when LSS is low and BG is high minus the threshold voltage of transistor 552, and GND when LSS is high and BG is low. This voltage swing allows transistor 564 to become fully conductive and biased above its threshold voltage to keep the on-resistance low, while drawing charge from intermediate node 542 when driver circuit 420 makes transistor 564 conductive.

In one example, V_{Input device}Is a battery voltage having a voltage varying between about 2.5 and about 5.0 volts, V_{Output of}Can be programmed to between about 0.3 and 1.35 volts, and the LDMOS transistor is implemented using a process technology that provides it with a threshold voltage of about 0.3 volts and a breakdown voltage of about 5.0 volts. In this case, the voltage drop of each of the

voltage sources

536 and 556 is set to about 2.1 volts to drive each transistor with a gate-source voltage of about 1.8 volts absolute.

The DC-DC converter 500 thus enables gate charge reuse with high-side and low-side drivers having voltage regulators formed from voltage sources and source follower transistors, combined with LDMOS transistors and tank capacitors. This reduces circuit complexity and saves die area compared to known designs, and also allows for an extended voltage input range. The increased efficiency allows for higher frequency operation.

Fig. 6 shows, in partial block diagram and partial schematic form, a portion of a DC-DC converter 600 according to another embodiment of the DC-DC converter 410 of fig. 4. The DC-DC converter 600 includes a driver circuit 420, an output power stage 422, an inductor 430, a capacitor 440, and a capacitor 640.

The driver circuit 420 includes a high-side driver 620 and a low-side driver 630. The high-side driver 620 includes an amplifier 622, a voltage source 624, a capacitor 626, and a driver 628. The amplifier 622 has a non-inverting input, an output connected to the inverting input, for receiving V_{Input device}And a negative power supply input. The voltage source 624 has a terminal for receiving V_{Input device}And a negative terminal connected to the non-inverting input of amplifier 622. Capacitor 626 has a capacitor for receiving V_{Input device}And a second terminal connected to the output of amplifier 622. Driver 628 has an input terminal for receiving the HSS signal, an output terminal for providing the TG signal, and an input terminal for receiving the input voltage V_{Input device}And a negative supply voltage terminal connected to the output of amplifier 622. The low-side driver 630 includes an amplifier 632, a voltage source 634, a capacitor 636, and a driver 638. Amplifier 632 has a non-inverting input, an output connected to the inverting input and to the negative power supply terminal of amplifier 622, a positive power supply terminal connected to the output of amplifier 622, and a negative power supply terminal connected to ground potential. Voltage source 634 has a positive terminal connected to the non-inverting input of amplifier 632, and a negative terminal connected to ground potential. Capacitor 636 has a first terminal connected to the output of amplifier 632, and a second terminal connected to ground potential. Driver 638 has an input for receiving the LSS signal, an output for providing the BG signal, a positive power supply terminal connected to the output of amplifier 632, and a negative power supply terminal connected to ground potential.

Output power stage 422 includes a P-channel LDMOS transistor 652 and an N-channel LDMOS transistor 654. Transistor 652 has a transistor for receiving V_{Input device}A gate connected to an output terminal of the driver 628 for receiving a TG signal, and a drain connected to the SWN terminal. Transistor 754 having a drain connected to the SWN terminalA gate receiving the BG signal, and a source connected to ground.

Capacitor 640 has a capacitor for receiving V_{Input device}And a second terminal coupled to ground potential. Capacitor 640 is to help prevent current variations from affecting V_{Input device}The decoupling capacitor of (1).

The DC-DC converter 600 uses a voltage regulator formed of an amplifier with a unity gain configuration of storage capacitors to regulate the voltage swing across the output transistor and the LDMOS transistor in the output stage. High-side driver 620 provides a voltage swing on the gate of transistor 652 between: v when HSS is low and TG is high_DDAnd a regulated voltage equal to V when HSS is high and TG is low_{Input device}Minus the voltage drop of the voltage source 624 on the gate of the transistor 534. This voltage swing allows transistor 562 to become fully conductive and biased above its threshold voltage to keep its on-resistance low while also sharing charge between

capacitors

626 and 636. The low-side driver 630 provides a voltage swing on the gate of transistor 654 between: a regulated voltage when LSS is low and BG is high, and a ground potential when LSS is high and BG is low, the regulated voltage being equal to the ground potential plus the voltage drop of the voltage source 634. This voltage swing allows

transistors

562 and 564 to become fully conductive and biased to an absolute value above their respective threshold voltages to keep their on-resistances low while also sharing charge between

capacitors

626 and 636. The voltage of the

capacitors

626 and 636 is determined by the

amplifiers

622 and 632 and the

voltage sources

624 and 634 and is set to less than V_{Input device}/2。

Fig. 7 shows, in partial block diagram and partial schematic form, a portion of a DC-DC converter 700 according to yet another embodiment of the DC-DC converter 410 of fig. 4. In the DC-DC converter 700, the driver circuit 420 uses a high-side driver 620 and a low-side driver 630 that are constructed in the same manner as the DC-DC converter 600 but are interconnected in a different manner. In the DC-DC converter 700, rather than the output of the amplifier interfacing with the opposite amplifier power supply terminal, the negative power terminal of the amplifier 622 is connected to the positive power supply terminal of the amplifier 632 to form an intermediate node. In addition, the DC-DC converter 700 has a bias capacitor 740 having a first terminal connected to the intermediate node and a second terminal connected to ground potential to provide charge storage on the intermediate node using a center bias feature.

Various implementations of DC-DC converters have therefore been described that enable gate charge reuse for power reduction. The LDMOS transistor reduces design complexity and saves die area. The driver circuit drives the LDMOS transistor into its active state by providing a gate drive voltage in the middle of the power supply rail, allowing for an extended input voltage range operation.

The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true scope of the claims. For example, although various driver circuits have been described using active regulation, other driver circuits may be used on other embodiments. Furthermore, although various embodiments using LDMOS transistors are shown and described, the above techniques are applicable to other transistor types, particularly those voltage sources having a gradual voltage/current slope, such as LDMOS transistors.

Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

According to one embodiment, a DC-DC converter includes a dead-time control circuit, an output power stage, and a driver circuit. According to one aspect, a first transistor of an output power stage has a first current electrode for receiving an input voltage, a control electrode for receiving a top gate signal, and a second current electrode coupled to a switch node, and a second transistor has a first current electrode coupled to the switch node, a control electrode for receiving a bottom gate signal, and a second current electrode coupled to a ground potential. According to this aspect, the first transistor and the second transistor may comprise Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistors.

According to another aspect, a high side driver includes a first driver, a third transistor, and a first voltage source. According to this aspect, the first voltage source may also provide a voltage between its first and second terminals equal to the predetermined voltage plus the threshold voltage of the third transistor.

According to yet another aspect, the low-side driver includes a fourth transistor, a second driver, and a second voltage source. According to this aspect, the second voltage source may provide a voltage between its first and second terminals equal to the predetermined voltage plus the threshold voltage of the fourth transistor.

According to yet another aspect, the driver circuit includes a high-side driver and a low-side driver. According to this aspect, the high-side driver may include a first amplifier having a non-inverting input, an output coupled to the inverting input and to a first intermediate node, and a negative supply input coupled to a second intermediate node; a first voltage source having a positive terminal for receiving an input voltage and a negative terminal coupled to the non-inverting input of the first amplifier; a first capacitor having a first terminal for receiving an input voltage and a second terminal coupled to the output of the amplifier; and a first driver coupled between the voltage input terminal and the first intermediate node for providing a top gate signal in response to the high-side switch signal. In this case, the low-side driver may include a second amplifier having a non-inverting input, an output coupled to the inverting input and to the second intermediate node, and a positive power supply input coupled to the first intermediate node; a second voltage source having a positive terminal for receiving an input voltage and a negative terminal coupled to the non-inverting input of the second amplifier; a second capacitor having a first terminal coupled to the output of the second amplifier and a second terminal coupled to ground potential; and a second driver coupled between the second intermediate node and ground for providing a bottom gate signal in response to the low-side switch signal.

According to another aspect, a driver circuit includes a high-side driver, a low-side driver, and a bias capacitor. In this case, the high-side driver may include a first amplifier having a non-inverting input, an output coupled to the inverting input, and a negative supply input coupled to the intermediate node; a first voltage source having a positive terminal for receiving an input voltage and a negative terminal coupled to the non-inverting input of the first amplifier; a first capacitor having a first terminal for receiving an input voltage and a second terminal coupled to the output of the amplifier; and a first driver coupled between the voltage input terminal and the output of the first amplifier for providing a top gate signal in response to the high-side switch signal. In this case, the low-side driver may include a second amplifier having a non-inverting input, an output coupled to the inverting input, and a positive power supply input coupled to the intermediate node; a second voltage source having a positive terminal for receiving an input voltage and a negative terminal coupled to the non-inverting input of the second amplifier; a second capacitor having a first terminal coupled to the output of the second amplifier and a second terminal coupled to ground potential; and a second driver coupled between the output of the second amplifier and ground for providing a bottom gate signal in response to the low-side switching signal.

According to another embodiment, a DC-DC power conversion system includes an error amplifier, an oscillator, a pulse width modulator, a dead time control circuit, an output power stage, and a driver circuit. According to one aspect, the error amplifier, the oscillator, the pulse width modulator, the dead time control circuit, the driver circuit and the output power stage are combined into a single monolithic integrated circuit. According to another aspect, the DC-DC power conversion system further includes an inductor having a first terminal coupled to the switch node, and a second terminal for providing an output voltage; and a capacitor having a first terminal coupled to the second terminal of the inductor, and a second terminal coupled to a ground potential. According to yet another aspect, a first transistor of the output power stage has a first current electrode for receiving an input voltage, a control electrode for receiving a top gate signal, and a second current electrode coupled to the switch node, and a second transistor of the output power stage has a first current electrode coupled to the switch node, a control electrode for receiving a bottom gate signal, and a second current electrode coupled to a ground potential. According to this aspect, the first transistor and the second transistor may include Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistors.

According to yet another embodiment, a method includes receiving a pulse width modulated signal; providing a high-side switching signal and a low-side switching signal having a dead time therebetween in response to the pulse width modulated signal; driving a top gate node coupled to the gate of the first transistor in response to the high-side switch signal by actively adjusting the top gate node to a first voltage between a threshold voltage and a breakdown voltage of the first transistor using charge from a bottom gate node coupled to the gate of the second transistor; and driving the bottom gate node in response to the low-side switching signal by actively regulating the bottom gate node to a second voltage between a threshold voltage and a breakdown voltage of the second transistor using charge from the top gate node. According to one aspect, driving the top-gate node includes driving a gate of the first LDMOS transistor, and driving the bottom-gate node includes driving a gate of the second LDMOS transistor.

Claims

1. A DC-DC converter comprising:

a dead-time control circuit having an input for receiving a pulse width modulated signal, a first output for providing a high-side switching signal, and a second output for providing a low-side switching signal;

an output power stage to receive an input voltage and to switch the input voltage to a switch node using a first transistor in response to a top gate signal received at a top gate node and to switch the switch node to ground potential using a second transistor in response to a bottom gate signal received at a bottom gate node; and

a driver circuit to provide the top gate signal and the bottom gate signal in response to the high-side switch signal and the low-side switch signal, respectively, the driver circuit to activate the top gate signal using a first regulator that actively regulates the top gate node to a first voltage between a threshold voltage and a breakdown voltage of the first transistor using charge from the bottom gate node, and to activate the bottom gate signal using a second regulator that actively regulates a second voltage between the threshold voltage and a breakdown voltage of the second transistor provided to the bottom gate node using charge from the top gate node.

2. The DC-DC converter of claim 1, wherein the driver circuit comprises:

a high side driver coupled between a voltage input terminal and an intermediate node for providing the top gate signal in response to the high side switch signal;

a tank capacitor having a first terminal coupled to the intermediate node and a second terminal coupled to a ground potential; and

a low-side driver coupled between the intermediate node and ground potential for providing the bottom gate signal in response to the low-side switch signal.

3. The DC-DC converter of claim 2, wherein the high-side driver comprises:

a first driver having an input for receiving the high-side switching signal, an output, a positive power supply terminal for receiving the input voltage, and a negative power supply terminal;

a third transistor having a first current electrode coupled to the negative power supply terminal of the first driver, a control electrode, and a second current electrode coupled to the intermediate node; and

a first voltage source having a positive terminal for receiving the input voltage and a negative terminal coupled to the control electrode of the third transistor.

4. The DC-DC converter of claim 3, wherein the low-side driver comprises:

a fourth transistor having a first current electrode coupled to the intermediate node, a control electrode, and a second current electrode;

a second driver having an input for receiving the low-side switching signal, an output, a positive power supply terminal coupled to the second current electrode of the fourth transistor, and a negative power supply terminal coupled to ground potential; and

a second voltage source having a positive terminal coupled to the control electrode of the fourth transistor and a negative terminal coupled to a ground potential.

5. The DC-DC converter of claim 1, wherein the driver circuit comprises:

a high side driver coupled between a voltage input terminal and a first intermediate node for providing the top gate signal in response to the high side switch signal; and

a low-side driver coupled between a second intermediate node and ground potential for providing the bottom gate signal in response to the low-side switching signal.

6. The DC-DC converter of claim 1, wherein the driver circuit comprises:

a low-side driver coupled between the intermediate node and ground potential for providing the bottom gate signal in response to the low-side switch signal; and

a bias capacitor having a first terminal coupled to the intermediate node and a second terminal coupled to a ground potential.

7. A DC-DC power conversion system, comprising:

an error amplifier having a first input for receiving a feedback signal, a second input for receiving a reference voltage, and an output;

an oscillator having an output for providing a clock signal; and

a pulse width modulator having a control input coupled to the output of the error amplifier, a clock input for receiving the clock signal, and an output for providing a pulse width modulator signal;

8. A method for DC-DC power conversion, comprising:

receiving a pulse width modulation signal;

providing a high-side switching signal and a low-side switching signal having a dead time therebetween in response to the pulse width modulated signal;

driving a top gate node coupled to a gate of a first transistor using a first regulator in response to the high-side switching signal, the first regulator actively regulating the top gate node to a first voltage between a threshold voltage and a breakdown voltage of the first transistor using charge from a bottom gate node coupled to a gate of a second transistor; and

driving the bottom gate node using a second regulator in response to the low-side switching signal, the second regulator actively regulating the bottom gate node to a second voltage between a threshold voltage and a breakdown voltage of the second transistor using charge from the top gate node.

9. The method of claim 8, further comprising:

switching an input voltage to a switching node using the first transistor in response to the driving the top gate node; and

switching the switch node to ground potential using the second transistor in response to the driving the bottom gate node.

10. The method of claim 8, further comprising:

using a tank capacitor to form a tank voltage;

clamping a top gate voltage on the top gate node to the first voltage using the tank voltage; and

clamping a bottom gate voltage on the bottom gate node to the second voltage using the tank voltage.