CN108336056B - Universal switching circuit layer for semiconductor packaging structure - Google Patents
Universal switching circuit layer for semiconductor packaging structure Download PDFInfo
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- CN108336056B CN108336056B CN201810326389.7A CN201810326389A CN108336056B CN 108336056 B CN108336056 B CN 108336056B CN 201810326389 A CN201810326389 A CN 201810326389A CN 108336056 B CN108336056 B CN 108336056B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004806 packaging method and process Methods 0.000 title abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000004020 conductor Substances 0.000 claims abstract description 7
- 238000010292 electrical insulation Methods 0.000 claims description 8
- 238000009413 insulation Methods 0.000 abstract 2
- 230000006870 function Effects 0.000 description 8
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000007488 abnormal function Effects 0.000 description 2
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- 230000002159 abnormal effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000007723 die pressing method Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49531—Additional leads the additional leads being a wiring board
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
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Abstract
The invention discloses a universal transfer circuit layer for a semiconductor packaging structure, which is arranged on a chip, the chip is arranged on a substrate, and the universal transfer circuit layer comprises an extended signal area, at least one relay contact area, a grounding area, a power supply area and an electric insulation layer, wherein the extended signal area, the relay contact area, the grounding area and the power supply area are formed by conductive materials, have conductivity and are arranged on the upper surface of the electric insulation layer. In addition, the extended signal region includes a plurality of signal lines and a plurality of pads, and the relay contact region includes a plurality of relay contacts. In particular, each signal line is arranged in parallel and is connected to at least one pad, and the pad, the relay contact, the ground region, the power region and the pins are selectively electrically connected to the connection ports of the substrate by leads.
Description
Technical Field
The invention relates to a universal switching circuit layer for a semiconductor packaging structure, in particular to a universal switching circuit layer which is electrically connected by corresponding leads according to the electrical function of a chip by utilizing a connecting pad, a relay contact, a grounding area, a power area and a pin.
Technical Field
In a conventional packaging process, wire bonding (wire bonding) is required to electrically connect an Integrated Circuit (IC) of a semiconductor and a lead frame, and the wire bonding is usually performed by using gold wires, aluminum wires or copper wires to connect pins of the IC to pins of the lead frame, and finally, encapsulating and curing to complete the packaging.
The pins of the integrated circuit must be configured with the design of the internal circuit to achieve the best performance, and when the wires between different pins and corresponding pins are staggered, a short circuit is easy to occur, or if the wire bonding distance between the pins is too long, the bonding wires are easily offset due to excessive die stamping during the subsequent die pressing process, which affects the electrical property, even the short circuit fails.
Therefore, there is a need for an innovative universal switching circuit layer for semiconductor package structure, which not only simplifies the routing design, shortens the routing distance, but also avoids the occurrence of interleaving, thereby solving the above-mentioned problems of the prior art.
Disclosure of Invention
In view of the shortcomings of the prior art, an object of the present invention is to provide a universal switching circuit layer for a semiconductor package structure.
In order to achieve the above object, the present invention adopts the following technical scheme:
The invention discloses a universal switching circuit layer for a semiconductor packaging structure, which comprises: an extended signal area comprising a plurality of signal lines and a plurality of connection pads, wherein the signal lines are arranged in parallel, each signal line is connected with at least one connection pad, and the corresponding connection pads connected with different signal lines are arranged to be spaced apart from each other and not contacted with each other; at least one relay contact region, each of the relay contact regions comprising a plurality of relay contacts; a grounding region; a power supply region; and an electrical insulating layer having electrical insulation, wherein the extended signal region, the at least one relay contact region, the ground region and the power region are made of a conductive material and have electrical conductivity, and are located on an upper surface of the electrical insulating layer; the universal switching circuit layer is arranged on the upper surface of a chip, and the chip is further arranged on the upper surface of a substrate, the substrate is provided with a circuit pattern and a connection port, and the connection pad, the relay contact, the grounding area and the power supply area of the universal switching circuit layer are selectively electrically connected to the connection port of the substrate by leads.
Preferably, the at least one relay contact region is disposed in a left edge region, a top edge region and a right edge region of the universal switching circuit layer.
Preferably, the ground region and the power region are disposed adjacent and not in contact.
Preferably, the at least one pad connected to the plurality of signal lines is arranged in a wavy arrangement.
Preferably, the at least one pad connected to the plurality of signal lines is arranged in parallel.
Preferably, the grounding region and the power supply region are elongated.
In one embodiment of the invention, the chip is a flash memory.
Preferably, a controller is disposed on the substrate or the flash memory, the controller has a plurality of connection pads, the relay contact, the grounding region and the power region of the universal switching circuit layer are selectively electrically connected to the connection pads of the substrate, the flash memory or the controller by leads.
The invention discloses another universal switching circuit layer for a semiconductor packaging structure, which comprises the following components: an extended signal area including a plurality of signal lines and a plurality of pads, wherein the signal lines are arranged in parallel, each signal line is connected with at least one pad, and the corresponding pads connected with different signal lines are arranged to be spaced apart from each other and not to be contacted with each other; at least one relay contact region, each of the relay contact regions comprising a plurality of relay contacts; a grounding region; a power supply region; and an electrical insulating layer having electrical insulation, wherein the extended signal region, the at least one relay contact region, the ground region and the power region are made of a conductive material and have electrical conductivity, and are located on an upper surface of the electrical insulating layer; the universal switching circuit layer is arranged on the upper surface of a first chip, and the first chip is further arranged on the upper surface of a bearing seat of a lead frame, and the connecting pad, the relay contact, the grounding area and the power supply area of the universal switching circuit layer are electrically connected to a pin of the lead frame through leads.
Preferably, the at least one relay contact region is disposed in a left edge region, a top edge region and a right edge region of the universal switching circuit layer.
Preferably, the ground region and the power region are disposed adjacent and not in contact.
Preferably, the at least one pad connected to the plurality of signal lines is arranged in a wavy arrangement.
Preferably, the at least one pad connected to the plurality of signal lines is arranged in parallel.
Preferably, the grounding region and the power supply region are elongated.
Preferably, a second chip is disposed between the first chip and the carrier, and the connection pad of the universal switching circuit layer, the relay contact, the grounding area, and the power supply area are selectively electrically connected to a pin of the lead frame and a connection pad of the second chip by leads.
Thus, the advantages of the present invention over the prior art include: the universal switching circuit layer can provide the signal switching function between the substrate and the chip, so that direct wire bonding between the substrate and the chip is not needed, the configuration of leads can be greatly simplified, the wire bonding yield is improved, the distance between the leads is shortened, the transmission quality of electric signals is improved, the staggering of the leads can be avoided, and the abnormal or even failure of functions caused by signal short circuit can be effectively prevented.
In addition, the universal switching circuit layer has higher design flexibility, can greatly reduce the design cost of developing the switching plate, and is especially not limited to a specific chip design, so that the universal switching circuit layer can be applied to various chips or matched with the chips, thereby improving the application elasticity and expanding the application field.
Drawings
Fig. 1 is a schematic diagram of a universal switching circuit layer for a semiconductor package according to an exemplary embodiment of the present invention.
Fig. 2 is a schematic diagram of a universal switching circuit layer for a semiconductor package according to another exemplary embodiment of the present invention.
Fig. 3 is a top view of a semiconductor package structure completed using a universal interposer circuit layer in accordance with an exemplary embodiment of the present invention.
Fig. 4 is a cross-sectional view of the semiconductor package of fig. 3 in the A-A direction.
Fig. 5 is a top view of another semiconductor package structure completed with a universal interposer circuit layer in accordance with an exemplary embodiment of the present invention.
Fig. 6 is a cross-sectional view of the semiconductor package of fig. 4.
Fig. 7 is a top view of another semiconductor package structure completed with a universal interposer circuit layer in accordance with an exemplary embodiment of the present invention.
Fig. 8 is a cross-sectional view of the semiconductor package of fig. 7.
Fig. 9 is a cross-sectional view of another semiconductor package structure completed with a universal interposer circuit layer in accordance with an exemplary embodiment of the present invention.
Reference numerals illustrate: 10-universal switching circuit layer, 11-extended signal area, 11A-signal line, 11B-connection pad, 12-relay contact area, 12A-relay contact, 13-grounding area, 14-power supply area, 15-electrical insulation layer, 20-chip, 30-substrate, 33-connection Fu, 34-lead frame, 35-bearing seat, 36-pin, 40, 41-lead wire, 60-controller, 62-connection pad, 70-flash memory.
Detailed Description
In view of the shortcomings in the prior art, the inventor of the present invention has long studied and practiced in a large number of ways to propose the technical scheme of the present invention. The technical scheme, implementation process and principle of the present invention will be further clearly and completely explained with reference to the accompanying drawings and more specific embodiments.
Embodiments of the present invention will be described in more detail below with reference to the drawings and reference numerals so that those skilled in the art can practice the invention after studying the specification.
Referring to fig. 1, a schematic diagram of a universal switching circuit layer for a semiconductor package structure according to an embodiment of the invention is shown. As shown in fig. 1, the universal switching circuit layer 10 according to the embodiment of the invention includes an extended signal region 11, at least one relay contact region 12, a ground region 13, a power region 14 and an electrical insulation layer 15, wherein the extended signal region 11, the relay contact region 12, the ground region 13 and the power region 14 are made of conductive materials and have conductivity, and are located on the upper surface of the electrical insulation layer 15. Further, the extended signal region 11 includes a plurality of signal lines 11A and a plurality of pads 11B, wherein the plurality of signal lines 11A are arranged in parallel, each signal line 11A is connected to at least one pad 11B, and the corresponding pads 11B connected to different signal lines 11A are arranged to be spaced apart from each other without touching. In addition, the relay contact region 12 includes a plurality of relay contacts 12A, and the electrical insulating layer 15 is electrically insulating. In particular, the extended signal region 11, the relay contact region 12, the ground region 13, and the power supply region 14 are made of conductive material and have conductivity, and are located on the upper surface of the electrical insulation layer 15.
More specifically, the universal switching circuit layer 10 in fig. 1 is exemplarily shown to have 16 signal lines 11A in total, and is divided into 4 groups, that is, each group includes 4 signal lines 11A, wherein each signal line 11A is self-connected to a plurality of pads 11B, so it is obvious that the corresponding pads 11B of two adjacent signal lines 11A are not at the same horizontal position but have a height difference, so that, as a whole, all signal lines 11A are repeated multiple times, for example, in a left-to-right arrangement from top to bottom, thereby forming an up-down wavy shape. The wavy bonding pad 11B can solve the problem of interlacing the chips 20 during wire bonding.
In addition, each relay contact 12A of the relay contact area 12 can be used to transfer the jumper wire, so that the risk of influencing the yield of the wire bonding or generating the cross wire due to the excessively long distance of the lead wire 40 can be avoided. Furthermore, since the ground region 13 and the power region 14 are formed in a long stripe shape, no staggering occurs when the wire is connected to the chip 20. Overall, the present invention can provide the shortest routing path in service.
As shown in fig. 2, the adjacent two signal lines 11A and the pads 11B of the universal switching circuit layer 10 of the present invention can be designed to be parallel to each other according to the electrical connection requirement, but the universal switching circuit layer is not limited thereto, and the adjacent two signal lines 11A and the pads 11B can be designed to be arranged in a combination of regular or irregular geometric shapes.
As shown in fig. 3 and 4, in the semiconductor package structure formed by using the universal switching circuit layer according to an exemplary embodiment of the present invention, the universal switching circuit layer 10 is disposed on the upper surface of the chip 20, and the chip 20 is further disposed on the upper surface of the substrate 30, so that the universal switching circuit layer 10 provides the electrical signal switching function between the chip 20 and the substrate 30, such that the pad 11B, the relay contact 12A, the ground region 12 of the relay contact region 12, and the connection port 33 of the substrate 30 of the universal switching circuit layer 30 are selectively electrically connected to each other by the lead 40. As shown in fig. 3, the connection port 33 of the substrate 30 is electrically connected to the power supply region 14 by using the lead wire 40 to electrically connect the connection port 33 of the substrate 30 and the power supply region 14 via the adjacent pad 11B with a specific distance on the same signal wire 11A, so as to prevent the deformation caused by using a single lead wire 40 to be too long, improve the transmission quality of the electrical signal, and at the same time prevent the lead wire 40 from being staggered, and effectively prevent the occurrence of signal short circuit to cause abnormal functions or even failure.
Referring to fig. 5 and 6, a top view and a cross-sectional view of another semiconductor package according to the present invention are shown, respectively, and please refer to fig. 1. In this embodiment, the semiconductor package has a leadframe 34, wherein the leadframe 34 includes a socket 35 and a lead 36. The universal switching circuit layer 10 of the present invention can be disposed on the upper surface of the first chip 20, the first chip 20 is further disposed on the second chip 21, and the second chip 21 is disposed on the supporting seat 35 of the lead frame 34, and the leads 40 can be selectively electrically connected to the pads 11B, the relay contacts 12A, the grounding region 13, the power region 14, the connection pads 22 of the second chip 21 and the leads 36 of the lead frame 34 of the universal switching circuit layer 10 according to the electrical functions of the first chip 20 and the second chip 21, respectively.
Therefore, the universal switching circuit layer for the semiconductor packaging structure is applicable to various semiconductor packaging structures, such as a double-wire inner packaging group (DIP), a Plastic Leaded Chip Carrier (PLCC), a Quad Flat Package (QFP), a low-profile quad flat package (LQFP), a Thin Small Outline Package (TSOP), a Thin Quad Flat Package (TQFP), a Tape Carrier Package (TCP), a Ball Grid Array (BGA), a Chip Size Package (CSP), a quad flat non-leaded package (QFN), a small outline package (SON), a lead frame BGA (LF-BGA), a module array package type BGA (MAP-BGA), a Memory Card (Memory Card) and the like.
Referring further to fig. 7 and 8, top and cross-sectional views are shown of another semiconductor package structure completed by using the universal switching circuit layer according to an embodiment of the present invention, and please refer to fig. 1 together. The semiconductor package structure comprises the universal switching circuit layer 10, the substrate 30, the controller 60 and the flash memory 70 according to the present invention, wherein the universal switching circuit layer 10 is used as a signal switching medium between the substrate 30, the controller 60 and the flash memory 70, and is connected by the corresponding leads 41.
Further, the flash memory 70 is disposed on the upper surface of the substrate 30, and the universal switching circuit layer 10 and the controller 60 are disposed on the upper surface of the flash memory 70. Furthermore, the controller 60 on the flash memory 70 includes a plurality of connection pads 62, wherein the universal switching circuit layer 10 and the controller 60 are separated from contact. Further, referring to the semiconductor package structure of fig. 9, the flash memory 70 and the controller 60 may be optionally disposed on the substrate 30, instead of stacking the flash memory 70 and the controller 60 on the substrate 30 as shown in fig. 8. Specifically, the controller 60 of fig. 8 and 9 is connected to the universal switching circuit layer 10 and the substrate 30 by wire bonding using the corresponding leads 41, for example, some connection pads 62 of the controller 60 may be connected to the corresponding plurality of relay contacts 12A of the universal switching circuit layer 10, and other connection pads 62 may be connected to the corresponding plurality of connection pads 33 of the substrate 30, such that the controller 60 may be electrically connected to the substrate 30 via signal switching of the universal switching circuit layer 10.
In summary, each pad 11B, each relay contact 12A, the ground area 13, and the power area 14 of the universal switching circuit layer 10 are selectively electrically connected to the connection port 33 of the substrate 30, the connection pad 62 of the controller 60, or the flash memory 70 by corresponding leads, in other words, the main function of the universal switching circuit layer 10 is to provide electrical connection between the substrate 30, the flash memory 70, and the controller 60, so that the flash memory 70 does not need to be directly wired to the substrate 30 and the controller 60, thereby shortening the wire-bonding distance, simplifying the wire-bonding configuration, and avoiding the wire-bonding interleaving to affect the electrical performance. Furthermore, the semiconductor package structure is well suited for the packaging field of memory cards, but is not limited thereto.
In summary, the present invention is mainly characterized in that the universal switching circuit layer is used to provide the signal switching function, and the universal switching circuit layer is electrically connected to the substrate by the leads, so that the wiring between the substrate and the chip is not needed, the configuration of the leads is greatly simplified, the wiring yield is improved, the distance between the leads is shortened, the transmission quality of the electrical signal is improved, and meanwhile, the staggering of the leads is avoided, and the occurrence of abnormal functions or even failure caused by short-circuiting of the signal is effectively prevented.
Another feature of the present invention is to provide an electrical transfer function between the substrate, the flash memory, and the controller by using the universal transfer circuit layer, wherein the universal transfer circuit layer and the controller are on the flash memory, and the flash memory is electrically connected to the circuit pattern of the substrate. Because the lead layout of the whole structure is very simplified, the method is very suitable for being applied to the packaging treatment of a memory card or a product which is required to be highly integrated, light, thin and small.
In general, the universal switching circuit layer can greatly reduce the design cost of developing the switching plate, and particularly, the design flexibility of the universal switching circuit layer is higher and is not limited to a specific chip design, so that the universal switching circuit layer can be applied to various chips or matched with the chips, thereby improving the application elasticity and expanding the application field.
It should be understood that the foregoing preferred embodiments are merely illustrative of the present invention, and other embodiments of the present invention are contemplated herein, which fall within the scope of the invention, as will be appreciated by those skilled in the art upon attaining an equivalent to or more than one of the following claims.
Claims (11)
1. A universal switching circuit layer for a semiconductor package structure, comprising:
An extended signal area comprising a plurality of signal lines and a plurality of connection pads, wherein the signal lines are arranged in parallel, each signal line is connected with at least one connection pad, the at least one connection pad connected with the signal lines is arranged in a wavy arrangement, and the corresponding connection pads connected with different signal lines are arranged to be spaced apart from each other and not contacted with each other;
At least one relay contact region, each of the relay contact regions comprising a plurality of relay contacts;
A grounding region;
A power supply region; and
An electrical insulating layer having electrical insulation, and the extended signal region, the at least one relay contact region, the ground region and the power region being made of an electrically conductive material and being located on an upper surface of the electrical insulating layer,
The universal switching circuit layer is arranged on the upper surface of a chip, and the chip is further arranged on the upper surface of a substrate, the substrate is provided with a circuit pattern and a connection port, and the connection pad, the relay contact, the grounding area and the power supply area of the universal switching circuit layer are selectively electrically connected to the connection port of the substrate by leads.
2. The universal adaptor circuit layer for a semiconductor package according to claim 1, wherein: the at least one relay contact region is disposed in a left edge region, a top edge region, and a right edge region of the universal switching circuit layer.
3. The universal adaptor circuit layer for a semiconductor package according to claim 1, wherein: the ground region and the power region are disposed adjacent to and not in contact with each other.
4. The universal adaptor circuit layer for a semiconductor package according to claim 1, wherein: the grounding area and the power supply area are long strips.
5. The universal adaptor circuit layer for a semiconductor package according to claim 1, wherein: the chip is a flash memory.
6. The universal adaptor circuit layer for a semiconductor package according to claim 5, wherein: a controller is provided on the substrate or the flash memory, the controller having a plurality of connection pads, the connection pads of the universal switching circuit layer, the relay contact, the grounding area and the power area, and is selectively electrically connected to the connection pads of the substrate, the flash memory or the controller by leads.
7. A universal switching circuit layer for a semiconductor package structure, comprising:
an extended signal area comprising a plurality of signal lines and a plurality of connection pads, wherein the signal lines are arranged in parallel, each signal line is connected with at least one connection pad, the at least one connection pad connected with the signal lines is arranged in a wavy arrangement, and the corresponding connection pads connected with different signal lines are arranged to be spaced apart from each other and not contacted with each other;
At least one relay contact region, each of the relay contact regions comprising a plurality of relay contacts;
A grounding region;
A power supply region; and
An electrical insulating layer having electrical insulation, and the extended signal region, the at least one relay contact region, the ground region and the power region being made of an electrically conductive material and being located on an upper surface of the electrical insulating layer,
The universal switching circuit layer is arranged on the upper surface of a first chip, and the first chip is further arranged on the upper surface of a bearing seat of a lead frame, and the connecting pad, the relay contact, the grounding area and the power supply area of the universal switching circuit layer are selectively electrically connected to a pin of the lead frame through leads.
8. The universal adaptor circuit layer for a semiconductor package according to claim 7, wherein: the at least one relay contact region is disposed in a left edge region, a top edge region, and a right edge region of the universal switching circuit layer.
9. The universal adaptor circuit layer for a semiconductor package according to claim 7, wherein: the ground region and the power region are disposed adjacent to and not in contact with each other.
10. The universal adaptor circuit layer for a semiconductor package according to claim 7, wherein: the grounding area and the power supply area are long strips.
11. The universal adaptor circuit layer for a semiconductor package according to claim 7, wherein: a second chip is disposed between the first chip and the support base, and the connection pad, the relay contact, the grounding area and the power area of the universal switching circuit layer are selectively electrically connected with a pin of the lead frame and a connection pad of the second chip by leads.
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| CN201810326389.7A CN108336056B (en) | 2018-04-12 | 2018-04-12 | Universal switching circuit layer for semiconductor packaging structure |
| TW107113313A TWI677956B (en) | 2018-04-12 | 2018-04-19 | A universal transfer layer for semiconductor packaging structure |
| TW107205109U TWM565880U (en) | 2018-04-12 | 2018-04-19 | Universal adapting circuit layer for semiconductor package structure |
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