CN108281442B - Image sensor and forming method thereof - Google Patents
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- CN108281442B CN108281442B CN201810069702.3A CN201810069702A CN108281442B CN 108281442 B CN108281442 B CN 108281442B CN 201810069702 A CN201810069702 A CN 201810069702A CN 108281442 B CN108281442 B CN 108281442B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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Abstract
An image sensor and a method of forming the same, the method comprising: providing a semiconductor substrate, wherein the semiconductor substrate comprises a logic area and a pixel area which are arranged in parallel, and an isolation structure is formed in the logic area on the front surface of the semiconductor substrate; etching the logic area from the back side of the semiconductor substrate to form a groove, wherein the bottom of the groove is exposed out of the isolation structure; and filling a dielectric layer in the groove. The scheme of the invention is beneficial to reducing leakage current and parasitic capacitance and avoiding latch-up effect, thereby improving the quality of the device.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to an image sensor and a forming method thereof.
Background
The image sensor is a core component of the image pickup apparatus, and realizes an image pickup function by converting an optical signal into an electric signal. Taking CMOS Image Sensors (CIS) devices as an example, CMOS Image Sensors are widely used in various fields due to their advantages of low power consumption and high signal-to-noise ratio.
In a conventional manufacturing process of a CIS, a logic device, a pixel device, and a metal interconnection structure may be formed on a front surface of a semiconductor substrate, and then a carrier wafer is used to bond with the front surface of the semiconductor substrate, so as to thin a back surface of the semiconductor substrate, and further form a subsequent process of the CIS on a back surface of the semiconductor substrate, for example, form a filter on the back surface of the semiconductor substrate of the pixel device.
The logic device may include a gate, a source region and a drain region, and an isolation structure may be formed in the logic region, and the isolation structure may be used to isolate the logic device.
However, in the existing CIS process, the depth of the isolation structure is usually shallow, which reduces the isolation effect on the logic device, and even there is a carrier moving from the source region to the drain region of the adjacent logic device by bypassing the bottom end of the isolation structure, which results in leakage current and parasitic capacitance, and even latch-up occurs in severe cases, which damages the semiconductor device.
Disclosure of Invention
The invention provides an image sensor and a forming method thereof, which are beneficial to reducing leakage current and parasitic capacitance and avoiding latch-up effect, thereby improving the quality of devices.
To solve the above technical problem, an embodiment of the present invention provides a method for forming an image sensor, including: providing a semiconductor substrate, wherein the semiconductor substrate comprises a logic area and a pixel area which are arranged in parallel, and an isolation structure is formed in the logic area on the front surface of the semiconductor substrate; etching the logic area from the back side of the semiconductor substrate to form a groove, wherein the bottom of the groove is exposed out of the isolation structure; and filling a dielectric layer in the groove.
Optionally, filling a dielectric layer in the groove includes: forming a dielectric material, wherein the dielectric material fills the groove and covers the pixel region on the back surface of the semiconductor substrate; and planarizing the dielectric material to expose the back surface of the semiconductor substrate of the pixel region.
Optionally, the dielectric material is silicon oxide and/or silicon nitride.
Optionally, before etching the logic region from the back side of the semiconductor substrate to form the groove, the method for forming the image sensor further includes: and thinning the semiconductor substrate from the back surface to a preset thickness.
Optionally, etching the logic region from the back side of the semiconductor substrate to form a groove includes: forming a patterned mask layer on the back surface of the semiconductor substrate; and etching the logic area by taking the patterned mask layer as a mask to form the groove.
Optionally, a logic device is formed in the semiconductor substrate of the logic region, and the isolation structure is used for isolating the logic device.
To solve the above technical problem, an embodiment of the present invention provides an image sensor, including: the semiconductor substrate comprises a logic area and a pixel area which are arranged in parallel; an isolation structure located in the logic region of the front side of the semiconductor substrate; a groove located in the logic region on the back surface of the semiconductor substrate, wherein the isolation structure is exposed from the bottom of the groove; and the dielectric layer is filled in the groove.
Optionally, the surface of the dielectric layer is flush with the back surface of the semiconductor substrate in the pixel region.
Optionally, the dielectric layer is made of silicon oxide and/or silicon nitride.
Optionally, a logic device is formed in the semiconductor substrate of the logic region, and the isolation structure is used for isolating the logic device.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, a semiconductor substrate is provided, wherein the semiconductor substrate comprises a logic area and a pixel area which are arranged in parallel, and an isolation structure is formed in the logic area on the front surface of the semiconductor substrate; etching the logic area from the back side of the semiconductor substrate to form a groove, wherein the bottom of the groove is exposed out of the isolation structure; and filling a dielectric layer in the groove. By adopting the scheme of the embodiment of the invention, the groove is formed on the back surface of the semiconductor substrate, the isolation structure is exposed at the bottom of the groove, and the dielectric layer is filled in the groove, so that a path for a current carrier to move from a source region to a drain region of an adjacent logic device by bypassing the bottom end of the isolation structure can be effectively isolated, the leakage current and the parasitic capacitance can be reduced, the latch-up effect can be avoided, and the quality of the device can be improved.
Further, the dielectric material is planarized to expose the back surface of the semiconductor substrate in the pixel region, so that the back surface of the semiconductor substrate in the pixel region is not affected by the logic region and is restored to the thickness in the prior art, parameters of a subsequent process can be continuously adopted, and the influence on the subsequent process is reduced.
Drawings
FIG. 1 is a schematic cross-sectional view of an image sensor in the prior art;
FIG. 2 is a flow chart of a method of forming an image sensor in an embodiment of the invention;
fig. 3 to fig. 7 are schematic cross-sectional views of devices corresponding to steps in a method for forming an image sensor according to an embodiment of the invention.
Detailed Description
In a conventional manufacturing process of a CIS, a logic device, a pixel device, and a metal interconnection structure may be formed on a front surface of a semiconductor substrate, and then a carrier wafer is used to bond with the front surface of the semiconductor substrate, so as to thin a back surface of the semiconductor substrate, and further form a subsequent process of the CIS on a back surface of the semiconductor substrate, for example, form a filter on the back surface of the semiconductor substrate of the pixel device.
Referring to fig. 1, fig. 1 is a schematic cross-sectional structure diagram of an image sensor in the prior art. The image sensor may include a semiconductor substrate 100, a logic device, a metal interconnection structure 150, and a Carrier Wafer (Carrier Wafer) 160.
The semiconductor substrate 100 includes a logic area a and a pixel area B, which are juxtaposed, and the semiconductor substrate 100 has a front surface and a back surface.
Specifically, a logic device and an isolation structure 110 are formed in the semiconductor substrate 100 of the logic region a, and the isolation structure 110 is used for isolating the logic device. The logic device may include, among other things, a gate 130, a source region 120, and a drain region 122.
However, in the conventional CIS process, as shown in the direction of the dotted arrow in fig. 1, there is a case where carriers move from the source region 120 to the drain region 126 of the adjacent logic device by bypassing the bottom end of the isolation structure 110, which is prone to generate leakage current and parasitic capacitance, and even latch-up occurs in a serious case, resulting in damage to the semiconductor device.
The inventors of the present invention have found through research that in the prior art, the depth of the isolation structure 110 is generally shallow, which reduces the isolation effect on the logic device. Specifically, since the semiconductor substrate 100 is thinned from the back surface, the thickness of the semiconductor substrate 100 is often thin (for example, about 2.5 μm), and therefore, the isolation structure 110 is difficult to be infinitely increased, resulting in a limitation in thickness.
In the embodiment of the invention, a semiconductor substrate is provided, wherein the semiconductor substrate comprises a logic area and a pixel area which are arranged in parallel, and an isolation structure is formed in the logic area on the front surface of the semiconductor substrate; etching the logic area from the back side of the semiconductor substrate to form a groove, wherein the bottom of the groove is exposed out of the isolation structure; and filling a dielectric layer in the groove. By adopting the scheme of the embodiment of the invention, the groove is formed on the back surface of the semiconductor substrate, the isolation structure is exposed at the bottom of the groove, and the dielectric layer is filled in the groove, so that a path for a current carrier to move from a source region to a drain region of an adjacent logic device by bypassing the bottom end of the isolation structure can be effectively isolated, the leakage current and the parasitic capacitance can be reduced, the latch-up effect can be avoided, and the quality of the device can be improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 2, fig. 2 is a flowchart of a method for forming an image sensor according to an embodiment of the present invention. The image sensor forming method may include steps S21 to S23:
step S21: providing a semiconductor substrate, wherein the semiconductor substrate comprises a logic area and a pixel area which are arranged in parallel, and an isolation structure is formed in the logic area on the front surface of the semiconductor substrate;
step S22: etching the logic area from the back side of the semiconductor substrate to form a groove, wherein the bottom of the groove is exposed out of the isolation structure;
step S23: and filling a dielectric layer in the groove.
The above steps will be described with reference to fig. 3 to 7.
Fig. 3 to fig. 7 are schematic cross-sectional views of devices corresponding to steps in a method for forming an image sensor according to an embodiment of the invention.
Referring to fig. 3, a semiconductor substrate 200 is provided, the semiconductor substrate 200 including a logic region a and a pixel region juxtaposed, the semiconductor substrate 200 having a front surface and a back surface.
A plurality of logic devices and an isolation structure 210 are formed in the semiconductor substrate 200 of the logic region a, and the isolation structure 210 is used to isolate each logic device. Wherein the logic device may be a MOS transistor including the gate 230, the source region 220, and the drain region 222, or the logic device may be other suitable device types, as non-limiting examples. As a non-limiting example, the isolation structure 210 may be a Shallow Trench Isolation (STI), or the isolation structure 210 may be another suitable type of isolation structure.
In a specific implementation, the semiconductor substrate 200 may be a silicon substrate, or the material of the semiconductor substrate 200 may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the semiconductor substrate 200 may also be a silicon substrate on the surface of an insulator or a germanium substrate on the surface of an insulator, or a substrate on which an epitaxial layer (Epi layer) is grown.
Preferably, the semiconductor substrate 200 is a lightly doped semiconductor substrate, and the doping type is opposite to the source region 220 and the drain region 222 formed in the semiconductor substrate 200 in the subsequent process. Specifically, Deep well doping (Deep WellImplant) may be achieved by ion implantation into the semiconductor substrate 200. If the type of the doping ions of the source region 220 and the drain region 222 is N type, the doping ions of the semiconductor substrate 200 are P type ions, for example comprising B, Ga or In; on the contrary, if the type of the dopant ions of the source region 220 and the drain region 222 is P-type, the dopant ions of the semiconductor substrate 200 are N-type ions, for example, P, As or Sb is included.
It is noted that although the pixel region B is not shown in the image sensor shown in fig. 3, in a specific implementation, the pixel region B may have a pixel device and an isolation structure for isolating a plurality of pixel devices, which may include a photodiode, a transfer gate, and a floating diffusion region. In the embodiment of the present invention, the specific device structure and the formation step of the pixel region B are not limited.
Referring to fig. 4, a metal interconnection structure 250 is formed on the front surface of the semiconductor substrate 200 and bonded to a carrier wafer 260.
It should be noted that the processing performed on the front surface of the semiconductor substrate 200 may be any conventional processing of an existing image sensor, and the embodiment of the present invention is not limited thereto.
Further, the semiconductor substrate 200 is thinned from the back side to a predetermined thickness.
Specifically, the preset thickness may be 1 μm to 4 μm.
It is understood that the thickness of the semiconductor substrate 200 cannot be too thin, which would increase the complexity of the thinning process and the wafer breakage rate; the thickness of the semiconductor substrate 200 cannot be too thick, otherwise it is difficult to realize the corresponding communication between the back trench and the front trench when the back trench is formed subsequently. Preferably, the thickness of the semiconductor substrate 200 is 2.5 μm.
Referring to fig. 5, the logic region a is etched from the back side of the semiconductor substrate 200 to form a groove 240, wherein the isolation structure 210 is exposed at the bottom of the groove 240.
Specifically, the step of etching the logic region a from the back side of the semiconductor substrate 200 to form the groove 240 may include: forming a patterned mask layer 270 on the back surface of the semiconductor substrate 200; and etching the logic area a by using the patterned mask layer 270 as a mask to form the groove 240.
More specifically, the front surface of the semiconductor substrate 200 has an alignment mark, a patterned mask layer 270 is formed on the back surface of the semiconductor substrate 200, and the pattern of the mask layer 270 is aligned according to the alignment mark.
The Alignment Mark (Alignment Mark) on the front surface of the semiconductor substrate 200 may be an Alignment Mark on an Active Area (AA) layer, and may also be another Alignment Mark that can be determined on the back surface of the semiconductor substrate 200.
Further, the process of etching the logic region a may be dry etching (DryEtch).
Referring to fig. 6, a dielectric layer 242 is filled in the groove 240.
Specifically, a dielectric material is formed, which fills the groove 240 and covers the pixel region B of the back surface of the semiconductor substrate 200. Since the isolation structures 210 are exposed at the bottom of the recess 240, the filled dielectric material is connected to the isolation structures 210.
Specifically, the dielectric material of the dielectric layer 242 may be silicon oxide and/or silicon nitride.
In a specific implementation manner of the embodiment of the present invention, a stacked structure of silicon oxide and silicon nitride, such as SiO, may be used as the dielectric layer 2422And Si3N4Since the stresses of the two materials, namely silicon oxide and silicon nitride, are opposite, excessive stress on the semiconductor substrate 200 can be avoided, which affects the device performance, and the silicon nitride can be used as a Stop Layer (Stop Layer) in a subsequent Chemical Mechanical Polishing (CMP) process.
In another specific implementation manner of the embodiment of the present invention, silicon oxide or silicon nitride may be used as the dielectric layer 242, such as SiO2Or Si3N4. Wherein the stress due to silicon oxide is lower than the stress due to silicon nitride.
Preferably, silicon oxide may be used as the dielectric layer 242, which may improve device quality compared to silicon nitride.
Further, the thickness of the dielectric layer 242 may be greater than or equal to the depth of the groove 240. As a non-limiting example, the dielectric layer 242 may have a thickness of 0.7 μm to 5 μm.
It is understood that the thickness of the dielectric layer 242 cannot be too thin, otherwise it is difficult to fill the recess 240 with a sufficient thickness of dielectric material, resulting in a weak isolation effect on the logic devices in the logic region a; the thickness of the dielectric layer 242 cannot be too thick, which increases the process time of the subsequent planarization process and causes resource waste.
Referring to fig. 7, the dielectric material is planarized to expose the backside of the semiconductor substrate 200 of the pixel region B.
Wherein the planarization treatment process comprises a chemical mechanical polishing process.
It will be appreciated that in particular implementations, a relatively high etch rate slurry for the semiconductor substrate 200 and the dielectric material may be used to reduce damage to the semiconductor substrate 200 during planarization.
It is noted that in another embodiment of the present invention, an oxide layer, such as silicon oxide, is deposited on the back surface of the semiconductor substrate 200 in the following subsequent processes. Therefore, when the dielectric material is silicon oxide, a part of silicon oxide can be remained in the pixel region B in the planarization process, thereby reducing the time consumption of the subsequent deposition process and the consumption of silicon oxide.
Next, a Through Silicon Via (Through Silicon Via), an aluminum Pad Layer (Pad), a Filter structure (Filter), a Passivation Layer (Passivation Layer), and other post process steps may be formed on the back surface of the semiconductor substrate 200.
It should be noted that, in the embodiment of the present invention, after the dielectric material is planarized, the processing process performed on the back surface of the semiconductor substrate 200 may be any conventional processing process of an existing image sensor, and the embodiment of the present invention is not limited thereto.
In the embodiment of the present invention, the groove 240 is formed on the back surface of the semiconductor substrate 200, the isolation structure 210 is exposed at the bottom of the groove 200, and the dielectric layer 242 is filled in the groove 240, so that a path through which carriers move from the source region 220 to the drain region 226 of an adjacent logic device bypassing the bottom end of the isolation structure 210 can be effectively isolated, which is beneficial to reducing leakage current and parasitic capacitance, and avoiding the occurrence of latch-up effect, thereby improving the device quality.
In an embodiment of the present invention, there is also provided an image sensor, and referring to fig. 7, the image sensor may include:
the semiconductor device comprises a semiconductor substrate 200, wherein the semiconductor substrate 200 comprises a logic area A and a pixel area B which are arranged in parallel;
an isolation structure 210 located in the logic region a of the front surface of the semiconductor substrate 200;
a groove 240 located in the logic region a on the back surface of the semiconductor substrate 200, wherein the isolation structure 210 is exposed at the bottom of the groove 240;
and a dielectric layer 242 filled in the groove 240.
Further, the surface of the dielectric layer 240 may be flush with the back surface of the semiconductor substrate 200 of the pixel region a.
The material of the dielectric layer can be silicon oxide and/or silicon nitride.
Logic devices are formed in the semiconductor substrate 200 of the logic region a, and the isolation structure 210 is used for isolating the logic devices.
The thickness of the semiconductor substrate 200 may be a predetermined thickness, which may be 1 μm to 4 μm as a non-limiting example.
The thickness of the dielectric layer 242 may be greater than or equal to the depth of the groove 240. As a non-limiting example, the dielectric layer 242 may have a thickness of 0.7 μm to 5 μm.
Further, the CIS may include a Front-side Illumination (FSI) CIS and a Back-side Illumination (BSI) CIS, which may also be referred to as a backside-illuminated CIS. In the back-illuminated CIS, light is irradiated from the back side onto the photodiode to generate photogenerated carriers, thereby forming an electrical signal.
In an embodiment of the present invention, the image sensor may be a backside-illuminated CIS.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (9)
1. A method of forming an image sensor, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a logic area and a pixel area which are arranged in parallel, and an isolation structure is formed in the logic area on the front surface of the semiconductor substrate;
etching the logic area from the back side of the semiconductor substrate to form a groove, wherein the bottom of the groove is exposed out of the isolation structure;
filling a dielectric layer in the groove;
wherein, filling the dielectric layer in the groove comprises:
forming a dielectric material, wherein the dielectric material fills the groove and covers the pixel region on the back surface of the semiconductor substrate;
and planarizing the dielectric material to expose the back surface of the semiconductor substrate of the pixel region.
2. The method of claim 1, wherein the dielectric material is silicon oxide and/or silicon nitride.
3. The method of claim 1, wherein before etching the logic region from the back side of the semiconductor substrate to form the recess, further comprising:
and thinning the semiconductor substrate from the back surface to a preset thickness.
4. The method of claim 1, wherein etching the logic region from a back side of the semiconductor substrate to form a recess comprises:
forming a patterned mask layer on the back surface of the semiconductor substrate;
and etching the logic area by taking the patterned mask layer as a mask to form the groove.
5. The method as claimed in claim 1, wherein a logic device is formed in the semiconductor substrate of the logic region, and the isolation structure is used for isolating the logic device.
6. An image sensor, comprising:
the semiconductor substrate comprises a logic area and a pixel area which are arranged in parallel;
an isolation structure located in the logic region of the front side of the semiconductor substrate;
a groove located in the logic region on the back surface of the semiconductor substrate, wherein the isolation structure is exposed from the bottom of the groove;
the dielectric layer is filled in the groove;
and after a dielectric material which fills the groove and covers the pixel region on the back surface of the semiconductor substrate is formed, the dielectric material is flattened to expose the back surface of the semiconductor substrate in the pixel region.
7. The image sensor of claim 6, wherein a surface of the dielectric layer is flush with a back surface of the semiconductor substrate of the pixel region.
8. The image sensor of claim 6, wherein the dielectric layer is made of silicon oxide and/or silicon nitride.
9. The image sensor as claimed in claim 6, wherein a logic device is formed in the semiconductor substrate of the logic region, and the isolation structure is used for isolating the logic device.
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| CN104882460A (en) * | 2014-02-27 | 2015-09-02 | 三星电子株式会社 | Image Sensors Having Deep Trenches Including Negative Charge Material And Methods Of Fabricating The Same |
| US20150372031A1 (en) * | 2014-06-23 | 2015-12-24 | Junho YOON | Image sensor and method of fabricating the same |
| US20170047373A1 (en) * | 2014-05-04 | 2017-02-16 | Semiconductor Manufacturing International (Shanghai) Corporation | Method for reducing crosstalk in cmos image sensor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104882460A (en) * | 2014-02-27 | 2015-09-02 | 三星电子株式会社 | Image Sensors Having Deep Trenches Including Negative Charge Material And Methods Of Fabricating The Same |
| US20170047373A1 (en) * | 2014-05-04 | 2017-02-16 | Semiconductor Manufacturing International (Shanghai) Corporation | Method for reducing crosstalk in cmos image sensor |
| US20150372031A1 (en) * | 2014-06-23 | 2015-12-24 | Junho YOON | Image sensor and method of fabricating the same |
| CN104157661A (en) * | 2014-08-15 | 2014-11-19 | 北京思比科微电子技术股份有限公司 | CMOS image sensor manufacturing method |
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