CN108258050B - High-K dielectric trench lateral superjunction double-diffused metal oxide element semiconductor field effect transistor and method of making the same - Google Patents

Abstract

The invention provides a High-K Dielectric (HK) groove transverse super-junction double-diffused metal oxide semiconductor field effect transistor (SJ-LDMOS) and a manufacturing method thereof. The device is mainly characterized in that a high-K dielectric layer with a deep groove is formed in a drain region of an SJ-LDMOS device, the upper end of the high-K dielectric layer is connected with a drain electrode, and the lower end of the high-K dielectric layer penetrates through a super junction drift region and a buffer layer and extends into an epitaxial layer above a substrate. The high-K dielectric layer of the deep groove and the element semiconductor material substrate form an MIS capacitor structure, and the high-K dielectric layer has a uniform electric field when the device is turned off, so that the electric field distribution in the body of the SJ-LDMOS device can be modulated, the longitudinal peak electric field at the drain end of the device is reduced, the problem that the breakdown voltage of the transverse LDMOS device is easily saturated along with the length of a drift region of the device is solved, and the contradiction relationship between the breakdown voltage of the device and the specific on-resistance is optimized.

Description

Field effects of high-K dielectric trench lateral superjunction double-diffused metal oxide element semiconductors Tube and method of making the same

technical field

The invention relates to the field of power semiconductor devices, in particular to a lateral super-junction double-diffused metal-oxide-semiconductor field effect transistor and a manufacturing method thereof.

Background technique

Lateral double-diffused MOS (Lateral Double-diffused MOS, referred to as LDMOS) represented by high voltage, low on-resistance lateral power devices are widely used in high-voltage integrated circuits (High Voltage Integrated Circuit, referred to as HVIC) and intelligent power integrated circuits ( Smart Power Integrated Circuit, referred to as SPIC). Super Junction (SJ for short) technology enables very low on-resistance (Specific On Resistance, R _ON,sp for short) under a certain breakdown voltage (Breakdown Voltage, BV) condition, and is applied to LDMOS The formation of the SJ-LDMOS structure breaks the limit relationship of traditional power MOS devices. However, many problems have been encountered in the implementation of SJ-LDMOS, including the Substrate Assisted Depletion (SAD) and other problems. Subsequently, some device structures for eliminating SAD have been proposed internationally, among which the Buffered SJ-LDMOS device using the buffer layer structure can effectively eliminate the SAD problem of the device itself. However, with the increase of the drift region length of the SJ-LDMOS device, under the condition that the surface electric field of the device is optimized by techniques such as Reduced Surface Field (RESURF), the longitudinal electric field distribution of the device is not optimized, thus limiting the SJ -BV of the LDMOS device.

Since the withstand voltage of a lateral power device is determined by a combination of lateral and vertical electric fields, in order to improve the breakdown voltage of SJ-LDMOS, the lateral and vertical electric fields of the device need to be optimized simultaneously. Currently, there are few techniques for optimizing the longitudinal electric field of SJ-LDMOS devices.

SUMMARY OF THE INVENTION

The present invention proposes a high-K dielectric (High-K Dielectric Pillar, HK) trench lateral superjunction double-diffused metal oxide element semiconductor field effect transistor, aiming to optimize the contradictory relationship between the breakdown voltage and the specific on-resistance of the SJ-LDMOS device.

The technical scheme of the present invention is as follows:

The high-K dielectric trench lateral superjunction double-diffused metal oxide semiconductor field effect transistor includes:

Substrates of semiconductor materials;

an epitaxial layer grown on a substrate;

a base region and a buffer layer formed on the epitaxial layer; the product of the doping concentration of the buffer layer and the thickness of the buffer layer satisfies the charge balance principle to eliminate the substrate-assisted depletion effect;

The super junction drift region formed on the buffer layer, the super junction drift region is composed of a plurality of N pillars and P pillars arranged alternately;

a source region and a channel formed on one side of the base region adjacent to the super junction drift region, and a drain region formed on the other side of the super junction drift region;

A channel substrate contact formed outside the source region in the base region;

A source electrode formed by short-circuiting the contact surface between the source region and the channel substrate;

a gate insulating layer and a gate electrode formed corresponding to the channel;

a drain electrode formed on the drain region;

Its special features are:

The substrate is made of elemental semiconductor material, and part of the drain region is etched to form a deep trench. The lower end of the deep trench passes through the superjunction drift region and the buffer layer and goes deep into the epitaxial layer above the substrate. The deep trench is filled with high K medium, the aspect ratio of the high-K medium is mainly determined according to the withstand voltage level of the device, and the upper end of the high-K medium is connected to the drain electrode through a polysilicon contact layer.

On the basis of the above scheme, the present invention has also made the following optimizations:

The overall thickness of the polysilicon contact layer and the drain electrode is comparable to the thickness of the gate electrode.

The relative permittivity of high-K dielectrics is 100-2000.

The depth of the high-K dielectric (ie, the depth of the deep trench) is related to the length of the drift region, and a preferred value is: the depth of the high-K dielectric is 1/4 to 2 times the length of the superjunction drift region.

The aspect ratio of the high-K dielectric (ie, the aspect ratio of the deep trench) is determined according to the withstand voltage level of the device and the actual process. For example, when the withstand voltage of the device is 600V, the aspect ratio of the high-K dielectric is 5/1-20/1.

The doping concentration of the substrate of the elemental semiconductor material is 1×10 ¹³ cm ⁻³ to 1×10 ¹⁵ cm ⁻³ .

The doping concentration of the buffer layer is 1×10 ¹⁴ cm ^-3 to 1×10 ¹⁶ cm ^-3 .

The doping concentration of the superjunction drift region is 1×10 ¹⁵ cm ^-3 to 1×10 ¹⁷ cm ^-3 .

As the above-mentioned elemental semiconductor material, silicon, germanium, etc. can be used.

A method for preparing a lateral superjunction double-diffused metal oxide element semiconductor field effect transistor for making the above-mentioned high-K dielectric trench, comprising the following steps:

1) take elemental semiconductor material as substrate;

2) growing an epitaxial layer on the substrate;

3) A base region and a buffer layer are formed on the epitaxial layer by ion implantation and thermal diffusion;

4) forming a superjunction drift region on the buffer layer by N-type and P-type ion implantation respectively;

5) The active region is formed on the base region and the drift region through the field oxygen oxidation process;

6) growing a gate oxide layer on the active area and depositing polysilicon, and then etching the polysilicon to form a gate electrode;

7) forming a source region and a channel on one side of the base region adjacent to the superjunction drift region by ion implantation, and simultaneously forming a drain region on the other side of the superjunction drift region;

8) forming a channel substrate contact through an ion implantation process on the outside of the source region in the base region;

9) forming deep trenches in part of the drain region by trench etching, and then depositing high-K dielectric materials;

10) depositing polysilicon on the surface of the high-K dielectric trench to form contact with the high-K dielectric;

11) depositing a passivation layer on the surface of the device, and then etching the contact hole;

12) depositing metal on the upper surface of the device;

13) forming a source electrode by short-circuiting the contact hole above the source region and the channel substrate;

14) A drain electrode is formed through a contact hole over the drain region.

The beneficial effects of the technical solution of the present invention are as follows:

A trench is formed at the drain end of the SJ-LDMOS device, the lower end of the high-K dielectric layer penetrates the superjunction drift region and the buffer layer and goes deep into the epitaxial layer above the substrate, and the upper end is connected to the drain electrode on the surface of the device. The high-K dielectric deep trench structure can effectively reduce the peak electric field caused by the cylindrical junction under the drain region of the device, optimize the longitudinal electric field distribution of the device, and improve the overall performance of the device. The high-K dielectric layer in the trench and the elemental semiconductor material substrate form a MIS capacitor structure, which can assist in depleting the charges in the substrate when the device is turned off, increasing the doping concentration of the device substrate, and making LDMOS with a low-resistance substrate A high breakdown voltage can be obtained. For SJ-LDMOS devices, the buffer layer structure is used to effectively eliminate the auxiliary depletion effect of the device substrate, and technologies such as RESURF are used on the surface of the device to optimize the surface electric field distribution of the device, and the use of high-K dielectric trenches can effectively optimize the bulk electric field of the device distribution, thereby improving the overall performance of the device. The problem that the breakdown voltage of the lateral LDMOS device is easily saturated with the length of the device drift region is solved, and the contradictory relationship between the device breakdown voltage and the specific on-resistance is further optimized.

Description of drawings

FIG. 1 is a schematic diagram of a three-dimensional structure of a device according to an embodiment of the present invention.

FIG. 2 is a schematic front view of a device according to an embodiment of the present invention.

Description of reference numbers:

1-source electrode; 2-gate electrode; 3-gate insulating layer; 4-superjunction drift region; 41-N pillar; 42-P pillar; 5-drain electrode; 6-polysilicon contact layer; 7-high K dielectric ( 8-drain region; 9-buffer layer; 10-epitaxial layer; 11-substrate; 12-base region; 13-source region; 14-channel substrate contact; 15-channel.

Detailed ways

As shown in FIG. 1, the lateral superjunction double-diffused metal oxide semiconductor field effect transistor of the high-K dielectric trench proposed by the present invention includes:

A substrate 11 of an elemental semiconductor material (such as silicon or germanium) (with a doping concentration of 1×10 ¹³ cm ⁻³ to 1×10 ¹⁵ cm ⁻³ );

an epitaxial layer 10 grown on a substrate;

The base region 12 and the buffer layer 9 formed on the epitaxial layer; the product of the doping concentration of the buffer layer and the thickness of the buffer layer satisfies the principle of charge balance to eliminate the substrate-assisted depletion effect; the doping concentration of the buffer layer is 1×10 ¹⁴ cm ^-3 to 1×10 ¹⁶ cm ^-3 ;

The superjunction drift region 4 formed on the buffer layer is composed of several N pillars 41 and P pillars 42 arranged alternately; the doping concentration of the superjunction drift region is 1×10 ¹⁵ cm ^-3 -1×10 ¹⁷ cm ^-3 ;

A source region 13 and a channel 15 formed on one side of the base region 12 adjacent to the super junction drift region, and a drain region 8 formed on the other side of the super junction drift region;

A channel substrate contact 14 formed outside the source region in the base region;

The source electrode 1 formed by short-circuiting the contact surface between the source region and the channel substrate;

The gate insulating layer 3 and the gate electrode 2 formed corresponding to the channel;

the drain electrode 5 formed on the drain region;

Part of the drain region is etched to form a deep trench. The lower end of the deep trench passes through the superjunction drift region and the buffer layer and penetrates deep into the epitaxial layer 10 above the substrate. The deep trench is filled with a high-K dielectric 7 . The relative permittivity of high-K dielectrics is 100-2000. The depth of the high-K dielectric is 1/4 to 2 times the length of the superjunction drift region. When the device withstand voltage is 600V, the aspect ratio of the high-K dielectric is 5/1-20/1. The upper end of the high-K dielectric is connected to the drain electrode through a polysilicon contact layer. The overall thickness of the polysilicon contact layer and the drain electrode is comparable to the thickness of the gate electrode.

A trench with a high aspect ratio is formed on the inside of the drain region of the SJ-LDMOS device by a trench etching process, HK material is deposited inside the trench, polysilicon is deposited over the HK material, and a drain electrode is formed on the surface. For traditional SJ-LDMOS, the substrate-assisted depletion effect of the device itself can be effectively eliminated through the buffer layer technology, and the surface electric field of the device can be optimized by techniques such as RESURF and field plate. However, since the drain region of the SJ-LDMOS device is a cylindrical junction in the buffer layer, a peak electric field is formed nearby, that is, the bulk electric field of the device is not optimized, which limits the breakdown voltage of the device. The high-K dielectric trench structure reduces the peak electric field at the drain of the device, effectively optimizes the longitudinal electric field distribution of the device, and improves the breakdown voltage of the device. At the same time, since the high-K dielectric layer and the elemental semiconductor material substrate form a MIS capacitor structure, it can assist in depleting the charges in the device substrate when the device is turned off, thereby increasing the doping concentration of the device substrate and reducing the substrate's density. resistivity. In short, the performance of the device can be effectively improved through the HK trench structure at the drain end of the device, and the contradictory relationship between the device breakdown voltage and the specific on-resistance can be further optimized.

The following takes N-channel SJ-LDMOS based on elemental semiconductor Si material as an example, which can be prepared by the following steps:

1) Take the substrate of P-type Si material;

2) growing a P-type epitaxial layer on a Si substrate;

3) forming a base region and a buffer layer on the epitaxial layer by P-type and N-type ion implantation and thermal diffusion respectively;

4) forming a superjunction drift region on the buffer layer by N-type and P ion implantation respectively, and the superjunction drift region is composed of a plurality of N pillars and P pillars arranged in phases;

5) The active region is formed on the base region and the drift region through the field oxygen oxidation process;

6) growing a gate oxide layer on the active area and depositing polysilicon, and then etching the polysilicon to form a gate electrode;

7) Then, through an N-type ion implantation process, a source region and a channel are formed on one side of the base region adjacent to the drift region, while a drain region is formed on the other side of the drift region;

8 forming a channel substrate contact through a P-type ion implantation process on the outside of the source region in the base region;

9) forming deep trenches by trench etching process in part of the drain region, and then depositing HK material;

10) depositing polysilicon on the surface of the HK trench to form contact with the HK material;

11) depositing a passivation layer on the surface of the device, and then etching the contact hole;

12) depositing metal on the upper surface of the device;

13) forming a source electrode by short-circuiting the contact hole above the source region and the channel substrate;

14) forming a drain electrode through a contact hole above the drain region;

Through Sentaurus simulation, the performance of the new device proposed by the present invention is greatly improved compared with the traditional device, and the impact of the new device under the condition that the length of the drift region of the two devices (the device proposed by the present invention and the traditional SJ-LDMOS device) is the same. Breakthrough voltage is increased by 50%.

Of course, the SJ-LDMOS in the present invention can also be a P-type channel, and its structure is equivalent to that of the N-channel SJ-LDMOS. The high-K dielectric trench technology at the drain of the device proposed in the present invention is also suitable for other ultra-high-K dielectrics based on elemental semiconductor materials. Junction power devices, including: SJ-LIGBT, SJ-PiN diode and other power semiconductor devices, should be regarded as belonging to the protection scope of the claims of the present application, and will not be repeated here.

The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the technical principle of the present invention, several improvements and replacements can be made. These improvements and replacements The solution also falls within the protection scope of the present invention.

Claims (9)

1. High-K dielectric trench lateral superjunction double-diffused metal oxide element semiconductor field effect transistor, including: Substrates of semiconductor materials; an epitaxial layer grown on a substrate; a base region and a buffer layer formed on the epitaxial layer; the product of the doping concentration of the buffer layer and the thickness of the buffer layer satisfies the charge balance principle to eliminate the substrate-assisted depletion effect; The super junction drift region formed on the buffer layer, the super junction drift region is composed of a plurality of N pillars and P pillars arranged alternately; a source region and a channel formed on one side of the base region adjacent to the super junction drift region, and a drain region formed on the other side of the super junction drift region; A channel substrate contact formed outside the source region in the base region; A source electrode formed by short-circuiting the contact surface between the source region and the channel substrate; a gate insulating layer and a gate electrode formed corresponding to the channel; a drain electrode formed on the drain region; It is characterized by: The substrate is made of elemental semiconductor material, and part of the drain region is etched to form a deep trench. The lower end of the deep trench passes through the superjunction drift region and the buffer layer and goes deep into the epitaxial layer above the substrate. The deep trench is filled with high K medium, the aspect ratio of the high-K medium is determined according to the withstand voltage level of the device, and the upper end of the high-K medium is connected to the drain electrode through a polysilicon contact layer. 2 . The high-K dielectric trench lateral superjunction double-diffused metal oxide element semiconductor field effect transistor according to claim 1 , wherein the relative permittivity of the high-K dielectric is 100˜2000. 3 . 3. The high-K dielectric trench lateral superjunction double-diffused metal oxide semiconductor field effect transistor according to claim 1, wherein the depth of the high-K dielectric is 1/4 to 2 times the length of the superjunction drift region . 4. The high-K dielectric trench lateral superjunction double-diffused metal oxide element semiconductor field effect transistor according to claim 1, characterized in that: when the device withstand voltage is 600V, the aspect ratio of the high-K dielectric is 5/1 -20/1. 5 . The high-K dielectric trench lateral superjunction double-diffused metal oxide element semiconductor field effect transistor according to claim 1 , wherein the doping concentration of the substrate of the element semiconductor material is 1×10 ¹³ cm ⁻³ . ~1×10 ¹⁵ cm ^-3 . 6 . The high-K dielectric trench lateral super-junction double-diffused metal oxide semiconductor field effect transistor according to claim 1 , wherein the doping concentration of the buffer layer is 1×10 ¹⁴ cm ⁻³ to 1×10 . 7 . ¹⁶ cm ^-3 . 7 . The high-K dielectric trench lateral superjunction double-diffused metal oxide semiconductor field effect transistor according to claim 1 , wherein the doping concentration of the superjunction drift region is 1×10 ¹⁵ cm ⁻³ to 1 . ×10 ¹⁷ cm ^-3 . 8 . The high-K dielectric trench lateral super-junction double-diffused metal oxide element semiconductor field effect transistor according to claim 1 , wherein the element semiconductor material is silicon or germanium. 9 . 9. A method of making the high-K dielectric trench lateral super-junction double-diffused metal oxide semiconductor field effect transistor according to claim 1, comprising the following steps: 1) take elemental semiconductor material as substrate; 2) growing an epitaxial layer on the substrate; 3) A base region and a buffer layer are formed on the epitaxial layer by ion implantation and thermal diffusion; 4) forming a superjunction drift region on the buffer layer by N-type and P-type ion implantation respectively; 5) The active region is formed on the base region and the drift region through the field oxygen oxidation process; 6) growing a gate oxide layer on the active area and depositing polysilicon, and then etching the polysilicon to form a gate electrode; 7) forming a source region and a channel on one side of the base region adjacent to the superjunction drift region by ion implantation, and simultaneously forming a drain region on the other side of the superjunction drift region; 8) forming a channel substrate contact through an ion implantation process on the outside of the source region in the base region; 9) forming deep trenches in part of the drain region by trench etching, and then depositing high-K dielectric materials; 10) depositing polysilicon on the surface of the high-K dielectric trench to form contact with the high-K dielectric; 11) depositing a passivation layer on the surface of the device, and then etching the contact hole; 12) depositing metal on the upper surface of the device; 13) forming a source electrode by short-circuiting the contact hole above the source region and the channel substrate; 14) A drain electrode is formed through a contact hole over the drain region.

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