CN108255770B - Processing method based on 1394 bus event message response mechanism - Google Patents
Processing method based on 1394 bus event message response mechanism Download PDFInfo
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- CN108255770B CN108255770B CN201711283734.5A CN201711283734A CN108255770B CN 108255770 B CN108255770 B CN 108255770B CN 201711283734 A CN201711283734 A CN 201711283734A CN 108255770 B CN108255770 B CN 108255770B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0012—High speed serial bus, e.g. IEEE P1394
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Abstract
The invention belongs to the computer hardware technology, and relates to a processing method based on a 1394 bus event message response mechanism. The processing method based on the 1394 bus event message response mechanism is provided, a receiver can immediately respond to the appointed key 1394 bus event message according to system configuration, and the reliability of the received message is improved; the sender retries sending at the offset time interval of the next STOF period without changing the bandwidth pre-allocated by the node, thereby ensuring the certainty of bus communication.
Description
Technical Field
The invention belongs to the computer hardware technology, and relates to a processing method based on a 1394 bus event message response mechanism.
Background
In the application of 1394 bus in the aeronautical field, the network data is mainly transmitted by asynchronous stream packets. However, asynchronous streaming messages do not require acknowledgement, which does not allow the receiver to confirm the receipt of the outgoing critical event message. In the IEEE1394 family of protocols, there is no definition of how the response mechanism to such critical asynchronous streaming messages should be handled.
Disclosure of Invention
The purpose of the invention is as follows: the invention provides a processing method based on a 1394 bus event message response mechanism, which solves the problem of reliable reception of key event messages.
The technical scheme of the invention is as follows: the invention provides a processing method based on a 1394 bus event message response mechanism, which can be divided into a sender processing step and a receiver processing step.
The sender processing steps are as follows:
step 1: allocating Start Of Frame (STOF) sending offset time to each message on a bus in a communication configuration table, identifying key messages needing to be responded, designing a retry number counter for each message needing to be responded, and loading a maximum retry number with an initial value set by a system;
step 2: the driving interface packages the information to be sent, fills the information into a buffer area to be sent which is empty or is about to be empty in a main memory according to the message attribute (whether response is needed) and the sending condition of the current message, and informs a hardware logic circuit that the data has sending conditions after the data package filling is finished;
and step 3: the hardware logic circuit checks the retry condition of the message, if the sending is finished (responded) or the retry is overtime, the message needs to be moved, and the message which needs to be sent currently is moved into the sending buffer in the chip; if the retry is not finished, the on-chip sending buffer still retains the last data and waits for the retry sending;
and 4, step 4: when the transmission offset time of the message to be transmitted is scheduled by the current configuration table, the message is moved into the on-chip transmission buffer, and at the transmission offset time, data is logically packaged and transmitted to a 1394 bus to finish the transmission of the message;
and 5: whether the message obtained by scheduling according to the configuration table needs to be responded or not, if the message needs to be responded, setting a corresponding response flag bit, and temporarily not updating a corresponding message buffer pointer;
step 6: if the response message is received in the overtime period (before the next data packet to be sent is sent), the sending of the response message is completed, the retry count value of the message is cleared to be 0, and the message is indicated to be sent completely;
and 7: if no response message is received within the timeout period (before the next data packet to be sent is sent), the retry count value is determined:
-if the retry count value is not equal to "0", then 1 is decremented and the subsequent message transmission is forwarded, the retry message being sent in the next transmission cycle;
-if the retry count value is equal to "0", indicating that the message has retried for a timeout, reporting an interrupt to the host and proceeding to a subsequent message transmission.
The receiving side comprises the following processing steps:
step 1: after the data packet is sent, the working mode of the node is set to be a receiving mode;
step 2: after receiving the message, if the Cyclic Redundancy Check (CRC) is correct, the node submits the message to a receiving scheduling logic; otherwise, directly discarding;
and step 3: the hardware logic circuit extracts the channel number of the received message and judges whether the channel number is the same as the channel number of the expected received message stored in the configuration table;
and 4, step 4: if not, directly discarding;
and 5: if the messages are the same, judging whether the messages need to be responded according to received message control words obtained by the scheduling configuration table, if so, writing the ID of the message into a response message load, and immediately starting to transmit;
step 6: and storing the received message into the on-chip receiving buffer area, and moving the data stored in the on-chip receiving buffer area to the main memory buffer area to complete the message receiving.
The invention has the advantages and effects that: the invention can be configured according to the system, the receiver immediately responds to the appointed key 1394 bus event message, and the reliability of receiving the message is improved; the sender retries sending at the offset time interval of the next sending period without changing the bandwidth pre-allocated by the node, thereby ensuring the certainty of bus communication.
Drawings
FIG. 1 is a flow chart of the method of the present invention.
Detailed Description
The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and the specific embodiments. It is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than the whole embodiments, and that all other embodiments, which can be derived by a person skilled in the art without inventive step based on the embodiments of the present invention, belong to the scope of protection of the present invention.
A processing method based on 1394 bus event message response mechanism can be divided into a sender processing step and a receiver processing step.
The sender processing steps are as follows:
step 1: allocating Start Of Frame (STOF) sending offset time to each message on a bus in a communication configuration table, identifying key messages needing to be responded, designing a retry number counter for each message needing to be responded, and loading a maximum retry number with an initial value set by a system;
step 2: the driving interface packages the information to be sent, fills the information into a buffer area to be sent which is empty or is about to be empty in a main memory according to the message attribute (whether response is needed) and the sending condition of the current message, and informs a hardware logic circuit that the data has sending conditions after the data package filling is finished;
and step 3: the hardware logic circuit checks the retry condition of the message, if the sending is finished (responded) or the retry is overtime, the message needs to be moved, and the message which needs to be sent currently is moved into the sending buffer in the chip; if the retry is not finished, the on-chip sending buffer still retains the last data and waits for the retry sending;
and 4, step 4: when the transmission offset time of the message to be transmitted is scheduled by the current configuration table, the message is moved into the on-chip transmission buffer, and at the transmission offset time, data is logically packaged and transmitted to a 1394 bus to finish the transmission of the message;
and 5: whether the message obtained by scheduling according to the configuration table needs to be responded or not, if the message needs to be responded, setting a corresponding response flag bit, and temporarily not updating a corresponding message buffer pointer;
step 6: if the response message is received in the overtime period (before the next data packet to be sent is sent), the sending of the response message is completed, the retry count value of the message is cleared to be 0, and the message is indicated to be sent completely;
and 7: if no response message is received within the timeout period (before the next data packet to be sent is sent), the retry count value is determined:
-if the retry count value is not equal to "0", then 1 is decremented and the subsequent message transmission is forwarded, the retry message being sent in the next transmission cycle;
-if the retry count value is equal to "0", indicating that the message has retried for a timeout, reporting an interrupt to the host and proceeding to a subsequent message transmission.
The receiving side comprises the following processing steps:
step 1: after the data packet is sent, the working mode of the node is set to be a receiving mode;
step 2: after receiving the message, if the Cyclic Redundancy Check (CRC) is correct, the node submits the message to a receiving scheduling logic; otherwise, directly discarding;
and step 3: the hardware logic circuit extracts the channel number of the received message and judges whether the channel number is the same as the channel number of the expected received message stored in the configuration table;
and 4, step 4: if not, directly discarding;
and 5: if the messages are the same, judging whether the messages need to be responded according to received message control words obtained by the scheduling configuration table, if so, writing the ID of the message into a response message load, and immediately starting to transmit;
step 6: and storing the received message into the on-chip receiving buffer area, and moving the data stored in the on-chip receiving buffer area to the main memory buffer area to complete the message receiving.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (1)
1. A processing method based on 1394 bus event message response mechanism is characterized by comprising a sender processing step and a receiver processing step,
the sender processing steps are as follows:
step 1: distributing and sending offset time to each message on a bus in a communication configuration table, identifying key messages needing to be responded, designing a retry number counter for each message needing to be responded, and loading a maximum retry number with an initial value set as a system;
step 2: the driving interface packages the information to be sent, fills the information into a buffer area to be sent which is empty or is about to be empty in a main memory according to the message attribute and the sending condition of the current message, and informs a hardware logic circuit that the data has sending conditions after the data package filling is finished;
and step 3: the hardware logic circuit checks the retry condition of the message, if the message is responded or the retry is overtime, the message needs to be moved, and the message which needs to be sent at present is moved into the sending buffer in the chip; if the retry is not finished, the on-chip sending buffer still retains the last data and waits for the retry sending;
and 4, step 4: when the transmission offset time of the message to be transmitted is scheduled by the current configuration table, the message is moved into the on-chip transmission buffer, and at the transmission offset time, data is logically packaged and transmitted to a 1394 bus to finish the transmission of the message;
and 5: whether the message obtained by scheduling according to the configuration table needs to be responded or not, if the message needs to be responded, setting a corresponding response flag bit, and temporarily not updating a corresponding message buffer pointer;
step 6: if the response message is received in the overtime period, the transmission of the response message is completed, the retry count value of the message is cleared to be 0, and the message is indicated to be completely transmitted;
and 7: if no response message is received within the timeout period, determining a retry count value:
if the retry count value is not equal to '0', 1 is subtracted, and the subsequent message transmission is switched, and the retry message is transmitted in the next transmission period;
if the retry count value is equal to '0', indicating that the message has retried overtime, reporting an interrupt to the host, and switching to subsequent message transmission;
the receiving side comprises the following processing steps:
step 1: after the data packet is sent, the working mode of the node is set to be a receiving mode;
step 2: after receiving the message, if the Cyclic Redundancy Check (CRC) is correct, the node submits the message to a receiving scheduling logic; otherwise, directly discarding;
and step 3: the hardware logic circuit extracts the channel number of the received message and judges whether the channel number is the same as the channel number of the expected received message stored in the configuration table;
and 4, step 4: if not, directly discarding;
and 5: if the messages are the same, judging whether the messages need to be responded according to received message control words obtained by the scheduling configuration table, if so, writing the ID of the message into a response message load, and immediately starting to transmit;
step 6: and storing the received message into the on-chip receiving buffer area, and moving the data stored in the on-chip receiving buffer area to the main memory buffer area to complete the message receiving.
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Citations (3)
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| CN101900772A (en) * | 2010-06-18 | 2010-12-01 | 中国航天科技集团公司第五研究院第五一三研究所 | Box equivalent device |
| CN102761466A (en) * | 2011-04-25 | 2012-10-31 | 中国科学院空间科学与应用研究中心 | IEEE (Institute of Electrical and Electronics Engineers) 1394 bus data record processing system and method |
| CN105391643A (en) * | 2015-12-09 | 2016-03-09 | 中国航空工业集团公司西安航空计算技术研究所 | IEEE_std 1394-2008 protocol-based link layer isochronal cascade packet flow control circuit and method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4631599B2 (en) * | 2005-08-19 | 2011-02-16 | 船井電機株式会社 | Digital television receiver connected to IEEE 1394 serial bus, and target device connected to IEEE 1394 serial bus |
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| CN101900772A (en) * | 2010-06-18 | 2010-12-01 | 中国航天科技集团公司第五研究院第五一三研究所 | Box equivalent device |
| CN102761466A (en) * | 2011-04-25 | 2012-10-31 | 中国科学院空间科学与应用研究中心 | IEEE (Institute of Electrical and Electronics Engineers) 1394 bus data record processing system and method |
| CN105391643A (en) * | 2015-12-09 | 2016-03-09 | 中国航空工业集团公司西安航空计算技术研究所 | IEEE_std 1394-2008 protocol-based link layer isochronal cascade packet flow control circuit and method |
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| Test Methodology for Characterizing the SEE Response of a Commercial IEEE 1394 Serial Bus (FireWire);C. Seidleck;《IEEE TRANSACTIONS ON NUCLEAR SCIENCE》;20021231;3129-3134页 * |
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Effective date of registration: 20221010 Address after: Room S303, Innovation Building, No. 25, Gaoxin 1st Road, Xi'an, Shaanxi 710075 Patentee after: XI'AN XIANGTENG MICROELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 710000 No. 15, Jinye Second Road, Xi'an, Shaanxi Patentee before: AVIC XI''AN AERONAUTICS COMPUTING TECHNIQUE RESEARCH INSTITUTE |
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