CN108255769B

CN108255769B - AXI-PLB bridge

Info

Publication number: CN108255769B
Application number: CN201711280985.8A
Authority: CN
Inventors: 牛少平; 郝冲; 魏艳艳; 邓艺; 韩一鹏
Original assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Current assignee: Xian Aeronautics Computing Technique Research Institute of AVIC
Priority date: 2017-12-06
Filing date: 2017-12-06
Publication date: 2021-03-26
Anticipated expiration: 2037-12-06
Also published as: CN108255769A

Abstract

The invention relates to the technical field of computer hardware, in particular to an AXI-PLB bridge, which comprises a conversion module 1 in an AXI-PLB direction and a conversion module 2 in a PLB-AXI direction; the AXI-PLB conversion module 1 is used for converting the request of an AXI end into a request which accords with a PLB interface and comprises single-beat read-write operation and burst read-write transmission operation of the AXI end; the PLB-AXI conversion module 2 is used for converting the request of the PLB end into a request conforming to an AXI interface, and comprises single-beat read-write operation and burst read-write transmission operation of the PLB end. The invention realizes the mutual conversion between the common operations on the two buses and greatly simplifies the design difficulty.

Description

AXI-PLB bridge

Technical Field

The invention relates to the technical field of computer hardware, in particular to a design implementation scheme of an AXI-PLB bridge.

Background

ARM is a top 32-bit RISC embedded processor in the industry, and has a large market share of embedded processors. The high-performance low-power consumption RISC chip is based on an AMBA bus structure and is widely applied to various products such as electronic equipment, wireless systems, automobiles, industrial control and the like. This also makes the AXI bus a bus protocol that is quite widely used.

The PLB bus is derived from CoreConnect bus specification, is a chip bus protocol designed by IBM corporation, and has complete functions and complete structure.

Therefore, the AXI-PLB bridge is designed and realized, the IP transplantation of different bus interfaces can be facilitated, and the method has important significance for engineering application.

Disclosure of Invention

The invention discloses an AXI-PLB bridge, which supports the mutual conversion of basic operations of common operations on two buses and the mutual conversion of inconsistent data bit widths of buses at two ends.

The technical solution of the invention is as follows:

an AXI-PLB bridge comprising an AXI-PLB directional translation module 1 and a PLB-AXI directional translation module 2;

the AXI-PLB conversion module 1 is used for converting the request of an AXI end into a request which accords with a PLB interface and comprises single-beat read-write operation and burst read-write transmission operation of the AXI end;

the PLB-AXI conversion module 2 is used for converting the request of the PLB end into a request conforming to an AXI interface, and comprises single-beat read-write operation and burst read-write transmission operation of the PLB end.

For the write operation initiated on the AXI, the conversion module 1 in the AXI-PLB direction puts the request on the AXI at the corresponding position on the PLB data bus according to the address, and simultaneously generates the corresponding PLB address and write-enabling information; and for the read operation initiated on the AXI, reading data is retrieved from a proper position on the PLB data bus according to the read address information of the AXI, and the read operation is completed.

The conversion module 2 in the PLB-AXI direction generates signals such as an AXI writing address and AXI writing data matched with AXI according to the writing enable signal for the single-beat writing operation initiated on the PLB; if the write data is more than one word, converting the write data into burst write operation on the AXI; for burst write operation initiated on PLB, converting into AXI burst write operation with fixed length for multiple times; for a single-beat read operation initiated on the PLB, generating a corresponding AXI read word address signal according to read word enable; for a read burst transfer initiated on the PLB, each transfer is converted into multiple fixed length read burst transfers on the AXI.

The invention has the technical effects that:

conventionally, AXI and PLB buses are two relatively complete bus types, supporting multiple operations and operation modes, and it is difficult to implement a complete AXI-PLB bridge. Considering that the application frequency of part of bus operation in engineering is very low and the development difficulty is high, the invention realizes the mutual conversion between the common operations on the two buses and greatly simplifies the design difficulty.

Drawings

FIG. 1 is a diagram of a design implementation structure of an AXI-PLB bridge according to the present invention.

FIG. 2 is a schematic diagram of an AXI-PLB bridge according to the present invention.

Detailed Description

The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and the specific embodiments. It is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than the whole embodiments, and that all other embodiments, which can be derived by a person skilled in the art without inventive step based on the embodiments of the present invention, belong to the scope of protection of the present invention.

An AXI-PLB bridge of the present invention, as shown in fig. 2, comprises an AXI-PLB direction conversion module 1 and a PLB-AXI direction conversion module (2);

Examples

As shown in fig. 1, the AXI data bus bit width is 32 bits, and the PLB data bus bit width is 128 bits. When the PLB master equipment initiates single-beat reading, generating corresponding AXI read address information according to the PLB address and the read word enabling information of the PLB; when a PLB master initiates a burst read operation, each beat of the transfer will be converted to a fixed-length fixed-width burst transfer on the AXI. When the PLB master equipment initiates a single beat write operation, generating write address data of a corresponding AXI according to the PLB address and the write word enable of the PLB; when the PLB master device initiates write burst transmission, each beat of transmission is converted into fixed-length fixed-width burst transmission on the AXI, and the transmitted information such as data, addresses and the like also come from the PLB bus and are controlled by the internal state machine to be sent out.

When AXI master equipment initiates single-shot reading, PLB single-shot read word enabling information is generated according to information such as an AXI word address; when the AXI master initiates a read burst transfer, the requests are merged, resulting in a read four word (32 bit for one word) request for multiple times on the PLB. When the AXI master device initiates write single beat transmission, the write single beat transmission is converted into single beat write on the PLB end, and the write address and write enable information are both generated according to AXI related signals. When the AXI master initiates a write burst transfer, it will merge it, and every four burst transfers on the AXI will be converted to one transfer on the PLB.

Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. An AXI-PLB bridge, characterized by: a conversion module (1) comprising an AXI-PLB direction and a PLB-AXI direction (2);

the AXI-PLB conversion module (1) is used for converting the request of an AXI end into a request conforming to a PLB interface, and comprises single-beat read-write operation and burst read-write transmission operation of the AXI end;

the PLB-AXI conversion module (2) is used for converting the request of the PLB end into a request conforming to an AXI interface, and comprises single-beat read-write operation and burst read-write transmission operation of the PLB end;

the conversion module (2) in the PLB-AXI direction generates signals such as an AXI writing address and AXI writing data matched with AXI according to the writing enable signal for the single-beat writing operation initiated on the PLB; if the write data is more than one word, converting the write data into burst write operation on the AXI; for burst write operation initiated on PLB, converting into AXI burst write operation with fixed length for multiple times; for a single-beat read operation initiated on the PLB, generating a corresponding AXI read word address signal according to read word enable; for a read burst transfer initiated on the PLB, each transfer is converted into multiple fixed length read burst transfers on the AXI.

2. The AXI-PLB bridge of claim 1, wherein: the conversion module (1) of AXI-PLB direction, for the write operation initiated on AXI, puts the request on AXI at the corresponding position on the PLB data bus according to the address, and generates the corresponding PLB address and write-word enabling information at the same time; and for the read operation initiated on the AXI, reading data is retrieved from a proper position on the PLB data bus according to the read address information of the AXI, and the read operation is completed.