CN108206139B - Oxide thin film transistor, manufacturing method thereof and array substrate - Google Patents
Oxide thin film transistor, manufacturing method thereof and array substrate Download PDFInfo
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- CN108206139B CN108206139B CN201810002395.7A CN201810002395A CN108206139B CN 108206139 B CN108206139 B CN 108206139B CN 201810002395 A CN201810002395 A CN 201810002395A CN 108206139 B CN108206139 B CN 108206139B
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- 239000010409 thin film Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 239000000758 substrate Substances 0.000 title claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims abstract description 61
- 239000002184 metal Substances 0.000 claims abstract description 61
- 238000001312 dry etching Methods 0.000 claims abstract description 33
- 239000000463 material Substances 0.000 claims description 98
- 230000004888 barrier function Effects 0.000 claims description 72
- 238000005530 etching Methods 0.000 claims description 37
- 229920002120 photoresistant polymer Polymers 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 33
- 239000011149 active material Substances 0.000 claims description 32
- 238000001039 wet etching Methods 0.000 claims description 21
- 230000000903 blocking effect Effects 0.000 claims description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 238000004380 ashing Methods 0.000 claims description 2
- 230000009286 beneficial effect Effects 0.000 abstract description 4
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- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 239000007788 liquid Substances 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- 239000011787 zinc oxide Substances 0.000 description 3
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
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- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a manufacturing method of an oxide thin film transistor, which comprises the following steps: forming a source drain metal layer on a substrate; and carrying out dry etching on the source drain metal layer to form a source electrode and a drain electrode. Correspondingly, the invention further provides an oxide thin film transistor and an array substrate. The invention is beneficial to reducing the area of the oxide thin film transistor, thereby being beneficial to realizing high resolution.
Description
Technical Field
The invention relates to the technical field of display, in particular to a manufacturing method of an oxide thin film transistor, the oxide thin film transistor and an array substrate.
Background
With the increasing of the size of the liquid crystal display device and the increasing of the frequency of the driving circuit, the mobility of the existing amorphous silicon thin film transistor is difficult to meet, and the metal oxide thin film transistor has high mobility, good uniformity, transparency and simple manufacturing process, so that the requirements of large-size liquid crystal displays and active organic electroluminescence can be better met, and the liquid crystal display device is paid much attention to by people.
The array substrate of the display device comprises a plurality of pixel areas, each pixel area is provided with a thin film transistor, and the ratio of the area occupied by the thin film transistors to the area of the pixel area influences the aperture ratio of pixels. In order to prevent the excessive display power consumption, the ratio of the area occupied by the thin film transistor to the area of the pixel region needs to be limited within a certain range to ensure that the pixel has a sufficient aperture ratio. However, in the prior art, when an oxide thin film transistor is manufactured, it is difficult to reduce the area of the oxide thin film transistor on a substrate, and in this case, in order to ensure the aperture ratio of a pixel, it is difficult to reduce the whole area of the pixel, thereby making it difficult to improve the resolution of a display product.
Disclosure of Invention
The invention aims to at least solve one of the technical problems in the prior art, and provides a manufacturing method of an oxide thin film transistor, the oxide thin film transistor and an array substrate, so as to be beneficial to improving the resolution of a display product.
In order to solve one of the above technical problems, the present invention provides a method for manufacturing an oxide thin film transistor, including:
forming a source drain metal layer on a substrate;
and carrying out dry etching on the source drain metal layer to form a source electrode and a drain electrode.
Preferably, the manufacturing method further comprises:
forming an active layer, wherein the active layer is positioned between the source drain metal layer and the substrate; the active layer includes a source connection portion, a drain connection portion, and an intermediate portion between the source connection portion and the drain connection portion; the source electrode covers the source electrode connecting part and is electrically connected with the source electrode contact part, and the drain electrode covers the drain electrode connecting part and is electrically connected with the drain electrode contact part;
forming a barrier material layer, wherein the barrier material layer at least covers the middle part of the active layer, and the etching selection ratio of the source drain metal layer to the barrier material layer is more than 10 under the same dry etching condition;
and the barrier material layer is formed before the source drain metal layer is subjected to dry etching.
Preferably, the barrier material layer is made of a conductive material;
after forming the source electrode and the drain electrode, the method further comprises the following steps:
and carrying out wet etching on the barrier material layer so as to remove at least the barrier material layer covering the middle part of the active layer.
Preferably, the conductive material comprises a metal.
Preferably, the metal comprises copper, and the thickness of the barrier material layer is between 5nm and 20 nm.
Preferably, the barrier material layer is formed after the active layer is formed.
Preferably, the step of forming the active layer includes:
forming an active material layer;
etching the active material layer to form the active layer;
the barrier material layer is formed after the active material layer is formed and before the active material layer is etched; the blocking material layer covers the whole substrate, and in the step of etching the active material layer, the blocking material layer is also etched to remove the blocking material layer outside the area where the active layer is located.
Preferably, the active layer, the source electrode and the drain electrode are formed through the same patterning process, which includes:
forming an active material layer, the source drain metal layer and a photoresist layer;
performing step exposure and development on the photoresist layer to enable the photoresist thickness of the region where the source electrode connecting part and the drain electrode connecting part of the active layer are located to be larger than that of the region where the middle part of the active layer is located, removing the photoresist of the region outside the region where the active layer is located, and enabling the photoresist thickness of the region where the middle part of the active layer is located to be larger than zero;
carrying out first dry etching on the source drain metal layer to form a middle electrode;
performing wet etching on the active material layer to form the active layer;
ashing the photoresist layer to remove the photoresist in the area of the middle part;
performing second dry etching on the intermediate electrode to form a source electrode and a drain electrode;
the barrier material layer is formed after the active material layer is formed and before the source drain metal layer is formed; the barrier material layer covers the whole substrate, and in the step of performing wet etching on the active material layer, the barrier material layer is further etched to remove the barrier material layer outside the area where the active layer is located.
Correspondingly, the invention also provides an oxide thin film transistor, and the oxide thin film transistor is manufactured by adopting the manufacturing method provided by the invention.
Correspondingly, the invention also provides an array substrate comprising the oxide thin film transistor provided by the invention.
In the invention, the source-drain metal layer is etched by adopting a dry etching process to form a source electrode and a drain electrode. Because the lateral etching effect on the metal is small during the dry etching, the critical dimension of the etched electrode is basically the same as the design value, and then the critical dimension of the source electrode and the drain electrode can be directly designed to be small during the design, so that the area occupied by the oxide thin film transistor on the substrate is reduced, and the high resolution of the display product is realized. In addition, during dry etching, the phenomenon that the mask pattern is washed away by etching liquid does not exist, so that the source electrode and the drain electrode which are small in size are formed by etching, and the high resolution of a display product is realized.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a first method of fabricating an oxide thin film transistor in an embodiment of the present invention;
FIGS. 2a to 2g are schematic structural diagrams of a first process of fabricating an oxide thin film transistor according to an embodiment of the present invention;
FIG. 3 is a flow chart of a second method of fabricating an oxide thin film transistor according to an embodiment of the present invention;
FIGS. 4a to 4e are schematic structural diagrams of an oxide thin film transistor in a second manufacturing process according to an embodiment of the present invention;
FIG. 5 is a flow chart of a third method for fabricating an oxide thin film transistor according to an embodiment of the present invention;
fig. 6a to fig. 6g are schematic structural diagrams of a third manufacturing process of an oxide thin film transistor according to an embodiment of the present invention.
Wherein the reference numerals are:
10. a substrate; 20. a gate electrode; 30. a gate insulating layer; 40. an active layer; 40a, an active material layer; 41. a source electrode connecting portion; 42. a drain electrode connecting portion; 43. an intermediate portion; 50. a layer of barrier material; 60. a source drain metal layer; 61. a source electrode; 62. a drain electrode; PR, photoresist layer.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
As an aspect of the present invention, there is provided a method of manufacturing an oxide thin film transistor, including:
and forming a source drain metal layer on the substrate.
And then, carrying out dry etching on the source drain metal layer to form a source electrode and a drain electrode.
In the prior art, in the process of manufacturing an oxide thin film transistor, when a source and drain metal layer is etched to form a source and a drain, a wet etching method is usually adopted, and since the wet etching not only can longitudinally etch metal but also can obviously laterally etch the metal, the critical dimension of the source and the drain formed after the wet etching is much smaller than the design value, therefore, in the design process, the critical dimension of the source and the drain needs to be designed to be larger, the occupied area of the oxide thin film transistor is larger, and the number of pixels on an array substrate is reduced. Thereby being disadvantageous to the display device for achieving high resolution. In addition, when the electrode with a small width is formed, the width of the mask pattern is small, so when the wet etching method is adopted for etching, the etching liquid can wash away the mask pattern with a small width. This also results in that the source and drain electrodes having a small size cannot be formed by wet etching, which is disadvantageous for the display device to realize high resolution.
The source-drain metal layer is etched by adopting a dry etching process to form a source electrode and a drain electrode. Because the lateral etching effect on the metal is small during the dry etching, the critical dimension of the etched electrode is basically the same as the design value, and then the critical dimension of the source electrode and the drain electrode can be directly designed to be small during the design, so that the area occupied by the oxide thin film transistor on the substrate is reduced, and the display device is further favorable for realizing high resolution. In addition, during dry etching, the phenomenon that the mask pattern is washed away by etching liquid does not exist, so that the source electrode and the drain electrode which are small in size are formed by etching, and the display device is high in resolution.
Preferably, the manufacturing method further comprises:
forming an active layer, wherein the active layer is positioned between the source drain metal layer and the substrate; the active layer includes a source connection portion, a drain connection portion, and an intermediate portion between the source connection portion and the drain connection portion; the source electrode covers the source electrode connecting portion and is electrically connected with the source electrode contact portion, and the drain electrode covers the drain electrode connecting portion and is electrically connected with the drain electrode contact portion. The active layer may be made of an oxide such as Indium Gallium Zinc Oxide (IGZO). It should be understood that "cover" of the present invention means to cover all, for example, the source electrode covers the source electrode connection portion means that the source electrode connection portion is covered by the source electrode, that is, the orthographic projection of the source electrode connection portion on the substrate is within the orthographic projection range of the source electrode on the substrate.
The active layer may be formed before the source electrode and the drain electrode are formed, or may be formed simultaneously with the source electrode and the drain electrode through the same patterning process.
In addition, before the dry etching is performed on the source drain metal layer, the method further comprises the following steps:
and forming a barrier material layer, wherein the barrier material layer at least covers the middle part of the active layer, and the etching selection ratio of the source drain metal layer to the barrier material layer is greater than 10 under the same dry etching condition, so that the active layer is always protected by the barrier material layer and cannot be contacted with plasma during dry etching, and the stability of the oxide thin film transistor is ensured.
When the material of the blocking material layer is an insulating material, the blocking material layer may not completely cover the active layer to ensure the electrical connection between the source and drain electrodes and the active layer; when the material of the blocking material layer is a conductive material, the blocking material layer can completely cover the active layer, and after the dry etching of the source drain metal layer is completed, the part of the blocking material layer, which covers the middle part of the active layer, is etched away.
In the present invention, the blocking material layer is made of a conductive material, and in this case, after the step of forming the source drain metal layer, the method further includes: and performing wet etching on the barrier material layer to remove at least the barrier material layer covering the middle part of the active layer.
Further, the conductive material comprises metal, the metal specifically comprises copper, and the thickness of the barrier material layer is 5 nm-20 nm, so that the barrier material layer cannot be etched when the source-drain metal layer is subjected to dry etching.
The manufacturing method of the thin film transistor is particularly suitable for the thin film transistor with the bottom gate type structure, namely, the step of forming the grid electrode is further included before the step of forming the active layer. The following describes the manufacturing method of the present invention in detail by taking the manufacturing of a bottom gate thin film transistor as an example.
Fig. 1 is a flow chart of a first manufacturing method of an oxide thin film transistor in the invention, and fig. 2a to 2g are schematic structural diagrams in a first manufacturing process of the oxide thin film transistor. In a first fabrication method, a barrier material layer is formed after the active layer. Referring to fig. 1 and fig. 2a to 2d, a first method for fabricating an oxide thin film transistor includes:
s101, a gate 20 is formed on the substrate 10, as shown in fig. 2 a. The method specifically comprises the following steps: the gate metal layer is formed by magnetron sputtering, and the gate metal layer can be a Mo layer, a Mo/Al composite layer or a Mo/Al/Mo composite layer. The gate metal layer is then subjected to a patterning process to form a gate electrode 20. The composition process of the gate metal layer comprises the deposition of photoresist, the exposure and the development of the photoresist and the etching of the gate metal layer; when the gate metal layer is etched, dry etching or wet etching may be used.
S102, forming the gate insulating layer 30, as shown in fig. 2 b.
And S103, forming the active layer 40, as shown in FIG. 2 c. The method specifically comprises the following steps: forming an active material layer, wherein the active material layer can be specifically an Indium Gallium Zinc Oxide (IGZO) layer; the active material layer is then subjected to a photolithographic patterning process to form an active layer 40. The active layer 40 includes a source connection portion 41, a drain connection portion 42, and an intermediate portion 43 between the source connection portion 41 and the drain connection portion 42.
And S104, forming the barrier material layer 50. Specifically, magnetron sputtering may be used to form the barrier material layer 50 covering the entire substrate 10, as shown in fig. 2 d. The material of which the barrier material layer 50 is made comprises copper, and the thickness of the barrier material layer 50 is between 5nm and 20 nm.
And S105, forming a source drain metal layer 60 on the side, away from the substrate 10, of the barrier material layer 50, as shown in FIG. 2 e.
And S106, performing dry etching on the source-drain metal layer 60 to form a source electrode 61 and a drain electrode 62, wherein the source electrode 61 and the drain electrode 62 are electrically connected with the active layer 40 through the barrier material layer 50, as shown in FIG. 2 f. The source electrode 61 covers the source connection part 41 of the active layer 40, and the drain electrode 62 covers the drain connection part 42 of the active layer 40. The source drain metal layer 60 may be an aluminum layer, and the etching gas used when performing dry etching on the source drain metal layer 60 includes chlorine and boron trichloride.
S107, performing wet etching on the blocking material layer 50, so as to leave the blocking material layer 50 in the region where the source electrode 61 is located and the drain electrode 62 is located, and remove the blocking material layer 50 in other regions, as shown in fig. 2 g. In the wet etching, an etching liquid having no etching action on the active layer 40 is used.
It can be understood that, when the source-drain metal layer 60 is dry-etched in step S106, a photoresist layer is formed on the surface of the source-drain metal layer 60; then, exposing and developing the photoresist layer to reserve the photoresist in the region where the source electrode is located and the region where the drain electrode is located and remove the photoresist in other regions; then, dry etching is carried out on the source drain metal layer 60; after the etching, the residual photoresist is not removed for a while, and after the wet etching in step S107 is finished, the residual photoresist on the source electrode 61 and the drain electrode 62 is removed.
Fig. 3 is a flowchart of a second manufacturing method of the oxide thin film transistor according to the present invention, and fig. 4a to 4e are schematic structural diagrams of the oxide thin film transistor in a second manufacturing process. The second manufacturing method of the oxide thin film transistor is different from the first manufacturing method in that: in the first fabrication method, the barrier material layer 50 is formed after the active layer 40; in the second fabrication method, the barrier material layer 50 is formed during the formation of the active layer 40. Specifically, as shown in fig. 3 and fig. 4a to 4d, the second method for fabricating the oxide thin film transistor includes:
s201, forming a gate 20 on the substrate 10, as shown in fig. 4a, the step is the same as the process of the step S101, and details are not repeated.
S202, forming the gate insulating layer 30, as shown in fig. 4 a.
And S203, forming an active layer 40 and a barrier material layer 50. Step S203 specifically includes: forming an active material layer; the active material layer may be specifically an Indium Gallium Zinc Oxide (IGZO) layer.
Thereafter, a barrier material layer 50, which may be specifically a copper layer, is formed covering the entire substrate 10.
Then, the active material layer is etched to form an active layer 40. The active layer 40 includes a source connection portion 41, a drain connection portion 42, and an intermediate portion 43 between the source connection portion 41 and the drain connection portion 42. It will be appreciated that since the barrier material layer 50 covers the entire substrate 10, during the etching of the active material layer, the barrier material layer 50 is also etched to remove the barrier material layer 50 outside the area where the active layer 40 is located, as shown in fig. 4 b. When the active material layer and the barrier material layer 50 are etched, a wet etching method may be adopted, and the etching solution may be an etching solution having an etching effect on both the active material layer and the barrier material layer 50.
And S204, forming a source drain metal layer 60 on the side, away from the substrate, of the barrier material layer 50, as shown in FIG. 4 c.
S205, performing dry etching on the source-drain metal layer 60 to form a source electrode 61 and a drain electrode 62, wherein the source electrode 61 covers the source electrode connecting part 41 of the active layer 40 and is electrically connected with the source electrode connecting part 41 through the barrier material layer 550; the drain electrode 62 covers the drain connection portion 42 of the active layer 40 and is electrically connected to the drain connection portion 42 through the barrier material layer 50. As shown in fig. 4 d.
S206, wet etching is performed on the barrier material layer 50, so that the barrier material layer 50 covering the middle portion 43 of the active layer 40 is removed, as shown in fig. 4 e. Note that, in the wet etching in step S206, an etching solution is used which has an etching effect on the barrier material layer 50 but has no etching effect on the active layer 40.
Fig. 5 is a flowchart of a third manufacturing method of the oxide thin film transistor according to the present invention, and fig. 6a to 6f are schematic structural diagrams in a third manufacturing process of the oxide thin film transistor. The third manufacturing method of the oxide thin film transistor is different from the first manufacturing method in that: in the first fabrication method, the barrier material layer 50 is formed after the active layer 40; in the third manufacturing method, the active layer 40, the source electrode 61, and the drain electrode 62 are formed through the same patterning process, thereby simplifying the manufacturing process. Specifically, as shown in fig. 5 and fig. 6a to 6g, the third method for fabricating the oxide thin film transistor includes:
s301, forming a gate 20 on the substrate 10, as shown in fig. 6a, the step is the same as S101, and detailed description thereof is omitted.
S302, the gate insulating layer 30 is formed, as shown in fig. 6 a.
And S303, forming the active layer 40, the source electrode 61 and the drain electrode 62 through the same patterning process. The method specifically comprises the following steps:
s303a, sequentially forming an active material layer 40a, a barrier material layer 50, a source drain metal layer 60 and a photoresist layer PR, as shown in fig. 6 b. The active material layer 40a, the barrier material layer 50 and the source drain metal layer 60 can be formed in a magnetron sputtering mode; the material of the barrier material layer 50 comprises copper and has a thickness of between 5nm and 20 nm.
S303b, step-exposing and developing the photoresist layer PR, so that the photoresist thickness of the active layer 40 in the region of the source connection portion 41 and the drain connection portion 42 is greater than that of the active layer middle portion, the photoresist of the active layer 40 region is removed, and the photoresist thickness of the active layer 40 middle portion 43 region is greater than zero, as shown in fig. 6 c. The step exposure is to fully expose the photoresist in one partial region, half expose the photoresist in the other partial region, and not expose the photoresist in the third partial region.
S303c, performing a first dry etching on the source/drain metal layer 60 to remove the source/drain metal layer 60 not covered by the photoresist, thereby forming an intermediate electrode 63, as shown in fig. 6 d. The source-drain metal layer 60 may be specifically made of aluminum, and the etching gas that may be used in the first dry etching includes chlorine and boron trichloride.
S303d, wet etching the active material layer 40a and the barrier material layer 50 to remove the active material layer 40a and the barrier material layer 50 which are not covered by the photoresist, thereby forming the active layer 40, and removing the barrier material layer 50 outside the region where the active layer 40 is located, as shown in fig. 6 d. The etching solution used in this step may be an etching solution having an etching effect on both the active material layer and the barrier material layer 50.
S303e, the photoresist layer PR is ashed to remove the photoresist in the region of the middle portion 43 of the active layer 40, while the photoresist in the regions of the source connection portion 41 and the drain connection portion 42 remains partially, as shown in fig. 6 e.
S303f, the intermediate electrode 63 is subjected to a second dry etching to remove the portion of the intermediate electrode 63 in the region of the intermediate portion 43, thereby forming the source electrode 61 and the drain electrode 62. The source electrode 61 and the drain electrode 62 are both electrically connected to the active layer 40 through the barrier material layer 50, as shown in fig. 6 e.
After forming the source electrode 61 and the drain electrode 62: s304, the barrier material layer 50 is wet-etched, thereby removing the barrier material layer 50 covering the intermediate portion 43. It should be noted that, when performing the wet etching in step S304, an etching solution that has an etching effect on the barrier material layer 50 but has no etching effect on the active layer 40 is used, that is, the etching solution used in step S304 is different from the etching solution used in step S303 d.
After that, the photoresist on the source electrode 61 and the drain electrode 62 is removed, so as to obtain the oxide thin film transistor shown in fig. 6 g.
As another aspect of the present invention, there is provided an oxide thin film transistor manufactured by the above-described manufacturing method, as shown in fig. 2g, 4e, and 6 g.
When the oxide thin film transistor is used for manufacturing a source electrode and a drain electrode, the source electrode metal layer and the drain electrode metal layer are etched in a dry etching mode, so that the sizes of the source electrode and the drain electrode are reduced, and the occupied area of the oxide thin film transistor is further reduced. And before the source drain metal layer is formed, a barrier material layer is also formed, so that the influence of plasma on the active layer during dry etching is reduced. Therefore, the oxide thin film transistor manufactured by the manufacturing method can keep stable performance and reduce the area of the oxide thin film transistor.
As another aspect of the present invention, an array substrate is provided, which includes the thin film transistor. The oxide thin film transistor can keep stable performance and reduce the area of the oxide thin film transistor, so that the array substrate can ensure the product quality and increase the number of the oxide thin film transistors, thereby being beneficial to realizing high resolution of the display device.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (5)
1. A method for manufacturing an oxide thin film transistor is characterized by comprising the following steps:
performing wet etching on an active material layer on a substrate to form a pattern of an active layer, wherein the active layer comprises a source electrode connecting part, a drain electrode connecting part and a middle part positioned between the source electrode connecting part and the drain electrode connecting part; the material of the active material layer comprises metal oxide;
forming a conductive barrier material layer covering at least a middle portion of the active layer; the thickness of the barrier material layer is between 5nm and 20 nm; the material of the barrier material layer comprises copper;
forming a source drain metal layer; the source drain metal layer is made of a material different from the barrier material layer; under the same dry etching condition, the etching selection ratio of the source drain metal layer to the barrier material layer is more than 10;
performing dry etching on the source drain metal layer to form a source electrode and a drain electrode; wherein the source electrode covers the source electrode connecting portion and is electrically connected to the source electrode contact portion, and the drain electrode covers the drain electrode connecting portion and is electrically connected to the drain electrode contact portion;
and carrying out wet etching on the barrier material layer to remove the barrier material layer covering the middle part of the active layer.
2. The method of claim 1, wherein the barrier material layer is formed after the active material layer is formed and before the active material layer is etched; the blocking material layer covers the whole substrate, and in the step of etching the active material layer, the blocking material layer is also etched to remove the blocking material layer outside the area where the active layer is located.
3. A method for manufacturing an oxide thin film transistor is characterized by comprising the following steps:
sequentially forming an active material layer, a barrier material layer, a source drain metal layer and a photoresist layer; the active material layer is made of metal oxide, the blocking material layer is made of copper, the source drain metal layer is made of a material different from that of the blocking material layer, and the thickness of the blocking material layer is between 5nm and 20 nm;
carrying out step exposure on the photoresist layer and developing to remove the photoresist outside the first region, wherein the photoresist thickness of the first sub-region in the first region is larger than that of the second sub-region in the first region; the photoresist thickness of the second sub-area is larger than zero; the first sub-region is a region where a source electrode connecting part and a drain electrode connecting part of the active layer are to be formed; the second sub-region is a region where a middle portion of the active layer is to be formed;
carrying out first dry etching on the source drain metal layer to form a middle electrode; under the same dry etching condition, the etching selection ratio of the source drain metal layer to the barrier material layer is greater than 10;
performing wet etching on the active material layer and the barrier material layer to form the active layer, and removing the barrier material layer outside the region where the active layer is located;
ashing the photoresist layer to remove the photoresist of the second sub-area;
performing second dry etching on the intermediate electrode to form a source electrode and a drain electrode;
and etching the barrier material layer to remove the barrier material layer in the area of the middle part of the active layer.
4. An oxide thin film transistor, wherein the oxide thin film transistor is manufactured by the manufacturing method of any one of claims 1 to 3.
5. An array substrate comprising the oxide thin film transistor according to claim 4.
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