CN108109909B - Method for forming groove - Google Patents
Method for forming groove Download PDFInfo
- Publication number
- CN108109909B CN108109909B CN201711354008.8A CN201711354008A CN108109909B CN 108109909 B CN108109909 B CN 108109909B CN 201711354008 A CN201711354008 A CN 201711354008A CN 108109909 B CN108109909 B CN 108109909B
- Authority
- CN
- China
- Prior art keywords
- silicon nitride
- side wall
- forming
- groove
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 106
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 88
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 86
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 40
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 33
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
A method for forming a trench includes the following steps: providing a substrate, and forming first silicon oxide on the substrate; forming photoresist on the first silicon oxide, wherein the photoresist is provided with an etching window; etching the first silicon oxide by using the etching window to form a first opening and a second opening, and removing the photoresist; forming a first silicon nitride side wall on the first opening and the second opening sidewall; etching the substrate by using the first silicon oxide and the first silicon nitride side wall as masks so as to form a first groove and a second groove on the surface of the substrate; forming second silicon nitride in the first and second trenches and the first and second openings; removing the first silicon oxide; forming a second silicon dioxide side wall on the substrate and one side of the first silicon nitride side wall, which is far away from the second silicon nitride; and etching the substrate by using the first silicon nitride side wall, the second silicon nitride and the second silicon dioxide side wall as masks to form a third groove between the first groove and the second groove.
Description
[ technical field ] A method for producing a semiconductor device
The present invention relates to the field of semiconductor chip manufacturing technology, and in particular, to a method for forming a trench of a semiconductor device.
[ background of the invention ]
The drain-source two poles of a semiconductor device, such as a vertical double-diffused field effect transistor (VDMOS), are respectively arranged at two sides of the device, so that current flows vertically in the device, the current density is increased, the rated current is improved, the on-resistance of a unit area is smaller, and the power device is very widely used. At present, the development direction of the vertical double-diffused field effect transistor is as follows:
(1) reducing the forward on-resistance to reduce static power loss;
(2) switching speed is increased to reduce transient power losses.
Among other things, reducing static power loss is achieved primarily by reducing the total on-resistance of the device. The total on-resistance of the device mainly comprises three parts: (1) a channel resistance; (2) a drift region resistance; (3) the resistance of the substrate. The resistance values of the three parts are determined by the structure and the manufacturing process of the device.
For low voltage power devices, the relative proportion of the drift region resistance in the on-resistance is small, so the channel resistance plays a major role in the on-resistance component. Therefore, reducing the channel resistance can significantly reduce the on-resistance of the device, reducing the cell size can increase the number of channels per unit device area, increase the width/length ratio of the channels, increase the current path, and thus reduce the channel resistance. Currently, the main method for reducing the cell size is to reduce the width of the trench. In the currently common trench manufacturing method, the trench width is determined by the minimum line width of the photolithography process, for example, the minimum photolithography line width and the minimum pitch that can be realized by a common I-line photolithography machine are 0.5um by 0.5 um. To reduce the trench width, more advanced lithographic equipment is required and device manufacturing costs can rise dramatically.
Accordingly, there is a need to provide a method for forming a trench to solve the above-mentioned problems of the prior art.
[ summary of the invention ]
One of the objectives of the present invention is to provide a method for forming a trench suitable for narrow trench fabrication.
A method for forming a trench includes the following steps:
providing a substrate, and forming first silicon oxide on the substrate;
forming photoresist on the first silicon oxide, wherein the photoresist is provided with an etching window;
etching the first silicon oxide by using the etching window to form a first opening and a second opening, and removing the photoresist;
forming a first silicon nitride side wall on the first opening and the second opening sidewall;
etching the substrate by using the first silicon oxide and the first silicon nitride side wall as a mask so as to form a first groove and a second groove on the surface of the substrate;
forming second silicon nitride in the first and second trenches and the first and second openings;
removing the first silicon oxide;
forming a second silicon dioxide side wall on the substrate and one side of the first silicon nitride side wall, which is far away from the second silicon nitride;
and etching the substrate by using the first silicon nitride side wall, the second silicon nitride and the second silicon dioxide side wall as masks to form a third groove between the first groove and the second groove.
In one embodiment, the step of forming the first silicon nitride sidewall on the first opening and the second sidewall of the opening includes:
forming a first silicon nitride on the substrate and the first silicon oxide;
and removing the first silicon nitride above the first silicon oxide and on part of the substrate, and reserving part of the first silicon nitride on the side walls of the first opening and the second opening to form the first silicon nitride side wall.
In one embodiment, the step of forming the second silicon oxide sidewall on the substrate and the side of the first silicon nitride sidewall away from the second silicon nitride includes:
forming second silicon dioxide on the first silicon nitride side wall, the second silicon nitride and the substrate;
and removing the first silicon nitride side wall, the second silicon dioxide above the second silicon nitride and part of the second silicon dioxide above the substrate, and reserving part of the second silicon dioxide on one side of the first silicon nitride side wall far away from the second silicon nitride to form the second silicon dioxide side wall.
In one embodiment, the removing the first silicon oxide step comprises: and removing the first silicon oxide by adopting a wet etching mode.
In one embodiment, the method of making further comprises the steps of:
and removing the second silicon nitride, the first silicon nitride side wall and the second silicon dioxide side wall on the inner side and the outer side of the first groove and the second groove.
In one embodiment, the second silicon nitride, the first silicon nitride sidewall and the second silicon dioxide sidewall inside and outside the first and second trenches are removed by wet etching.
In one embodiment, the width of the first opening and the second opening is 0.5um, and the distance between the first opening and the second opening is 0.5 um.
In one embodiment, the thickness of the first silicon nitride spacer is 0.1 um.
In one embodiment, the thickness of the second silicon dioxide side wall is 0.1 um.
In one embodiment, the width of the first trench and the second trench is 0.3um, the width of the third trench is 0.3um, the distance between the first trench and the third trench is 0.2um, and the distance between the second trench and the third trench is 0.2 um.
Compared with the prior art, the forming method of the groove provided by the invention reduces the effective width of the groove by depositing and etching the silicon oxide and/or the silicon nitride twice and adding the silicon oxide and/or the silicon nitride side wall once before each etching, and finally uses the silicon oxide and/or the silicon nitride as a mask to etch the groove on the substrate, so that the width of the groove on the substrate is far smaller than the photoetching width of photoetching equipment. Therefore, the method for forming the groove provided by the invention reduces the requirement of manufacturing the narrow groove on photoetching equipment, and can effectively reduce the manufacturing cost of devices.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a flow chart illustrating a method for forming a trench according to a preferred embodiment of the present invention;
fig. 2 to 13 are schematic structural views of steps in the method for forming the trench shown in fig. 1.
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to solve the problem that narrow grooves are difficult to realize in the semiconductor groove manufacturing method in the prior art, the invention provides a groove forming method, which mainly reduces the effective width of the groove by depositing and etching silicon oxide and/or silicon nitride twice and adding a silicon oxide and/or silicon nitride side wall before each etching, and finally uses the silicon oxide and/or silicon nitride as a mask to etch the groove on the substrate, so that the width of the groove on the substrate is far smaller than the photoetching width of photoetching equipment. Therefore, the method for forming the groove provided by the invention reduces the requirement of manufacturing the narrow groove on photoetching equipment, and can effectively reduce the manufacturing cost of devices.
Please refer to fig. 1, which is a flowchart illustrating a method for forming a trench according to a preferred embodiment of the present invention. The groove forming method can be applied to the manufacturing process of a power device, such as a vertical double-diffusion field effect transistor (VDMOS), and is used for realizing the narrow groove manufacturing of the power device. Specifically, the method for forming the trench mainly includes the following steps S1-S10.
In step S1, referring to fig. 2, a substrate is provided, and a first silicon oxide is formed on the substrate. The body may be a body of a semiconductor device, such as a silicon substrate.
In step S2, referring to fig. 3, a photoresist is formed on the first silicon oxide, and the photoresist has an etching window.
In step S3, referring to fig. 4, the first silicon oxide is etched by using the etching window to form a first opening and a second opening, and the photoresist is removed. In this embodiment, the width of the first opening and the second opening is 0.5um, and the distance between the first opening and the second opening is 0.5 um.
In step S4, please refer to fig. 5 and fig. 6, a first silicon nitride sidewall is formed on the sidewalls of the first opening and the second opening. Specifically, the step S4 may include the following steps: forming a first silicon nitride on the substrate and the first silicon oxide; and removing the first silicon nitride above the first silicon oxide and on part of the substrate, and reserving part of the first silicon nitride on the side walls of the first opening and the second opening to form the first silicon nitride side wall. The thickness of first silicon nitride side wall is 0.1 um.
Step S5, referring to fig. 7, etching the substrate with the first silicon oxide and the first silicon nitride spacer as a mask to form a first trench and a second trench on the surface of the substrate;
in step S6, referring to fig. 8, a second silicon nitride is formed in the first and second trenches and the first and second openings.
In step S7, please refer to fig. 9, the first sio is removed. Specifically, in step S7, the first silicon oxide may be removed by wet etching.
In step S8, referring to fig. 10 and 11, a second silicon dioxide sidewall is formed on the substrate and the side of the first silicon nitride sidewall away from the second silicon nitride. The step S8 may include the following steps: forming second silicon dioxide on the first silicon nitride side wall, the second silicon nitride and the substrate; and removing the first silicon nitride side wall, the second silicon dioxide above the second silicon nitride and part of the second silicon dioxide above the substrate, and reserving part of the second silicon dioxide on one side of the first silicon nitride side wall far away from the second silicon nitride to form the second silicon dioxide side wall. The thickness of the second silicon dioxide side wall is 0.1 um.
In step S9, referring to fig. 12, the substrate is etched by using the first silicon nitride sidewall, the second silicon nitride, and the second silicon dioxide sidewall as masks to form a third trench located between the first trench and the second trench.
In step S10, please refer to fig. 13, the second silicon nitride, the first silicon nitride sidewall spacers and the second silicon dioxide sidewall spacers inside and outside the first and second trenches are removed. Specifically, in step S10, the second silicon nitride, the first silicon nitride sidewall, and the second silicon dioxide sidewall inside and outside the first and second trenches may be removed by wet etching. The first groove with the width of second groove is 0.3um, the width of third groove is 0.3um, the first groove with the interval of third groove is 0.2um, the second groove with the interval of third groove is 0.2 um.
Compared with the prior art, the forming method of the groove provided by the invention has the advantages that the effective width of the groove is reduced by depositing and etching silicon oxide and/or silicon nitride twice and adding the silicon oxide and/or silicon nitride side wall once before each etching, and finally the groove is etched on the substrate by using the silicon oxide and/or the silicon nitride as a mask, so that the width of the groove on the substrate is far smaller than the photoetching width of photoetching equipment, for example, the groove with the photoetching width of 0.5um and the interval of 0.5um can be obtained by combining the forming method of the groove provided by the invention, and the requirement of manufacturing a narrow groove on the photoetching equipment is reduced, and the manufacturing cost of a device can be effectively reduced.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (8)
1. A method for forming a trench, comprising: the manufacturing method comprises the following steps:
providing a substrate, and forming first silicon oxide on the substrate;
forming photoresist on the first silicon oxide, wherein the photoresist is provided with an etching window;
etching the first silicon oxide by using the etching window to form a first opening and a second opening, and removing the photoresist;
forming a first silicon nitride side wall on the first opening and the second opening sidewall;
etching the substrate by using the first silicon oxide and the first silicon nitride side wall as a mask so as to form a first groove and a second groove on the surface of the substrate;
forming second silicon nitride in the first and second trenches and the first and second openings;
removing the first silicon oxide;
forming a second silicon dioxide side wall on the substrate and one side of the first silicon nitride side wall, which is far away from the second silicon nitride;
etching the substrate by using the first silicon nitride side wall, the second silicon nitride and the second silicon dioxide side wall as masks to form a third groove between the first groove and the second groove;
the step of forming a first silicon nitride sidewall on the sidewalls of the first opening and the second opening includes:
forming a first silicon nitride on the substrate and the first silicon oxide;
removing the first silicon nitride above the first silicon oxide and on part of the substrate, and reserving part of the first silicon nitride on the side walls of the first opening and the second opening to form the first silicon nitride side wall;
the step of forming a second silicon dioxide side wall on the substrate and one side of the first silicon nitride side wall, which is far away from the second silicon nitride, comprises the following steps:
forming second silicon dioxide on the first silicon nitride side wall, the second silicon nitride and the substrate;
and removing the first silicon nitride side wall, the second silicon dioxide above the second silicon nitride and part of the second silicon dioxide above the substrate, and reserving part of the second silicon dioxide on one side of the first silicon nitride side wall far away from the second silicon nitride to form the second silicon dioxide side wall.
2. The method of forming a trench according to claim 1, wherein: the removing the first silicon oxide step includes: and removing the first silicon oxide by adopting a wet etching mode.
3. The method of forming a trench according to claim 1, wherein: the manufacturing method further comprises the following steps:
and removing the second silicon nitride, the first silicon nitride side wall and the second silicon dioxide side wall on the inner side and the outer side of the first groove and the second groove.
4. A method of forming a trench as claimed in claim 3, wherein: and removing the second silicon nitride, the first silicon nitride side wall and the second silicon dioxide side wall on the inner side and the outer side of the first and second grooves by adopting a wet etching mode.
5. The method of forming a trench according to claim 1, wherein: the first opening with the width of second open-ended is 0.5um, the first opening with second open-ended interval is 0.5 um.
6. The method of forming a trench according to claim 1, wherein: the thickness of first silicon nitride side wall is 0.1 um.
7. The method of forming a trench according to claim 1, wherein: the thickness of the second silicon dioxide side wall is 0.1 um.
8. The method of forming a trench according to claim 1, wherein: the first groove with the width of second groove is 0.3um, the width of third groove is 0.3um, the first groove with the interval of third groove is 0.2um, the second groove with the interval of third groove is 0.2 um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711354008.8A CN108109909B (en) | 2017-12-15 | 2017-12-15 | Method for forming groove |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711354008.8A CN108109909B (en) | 2017-12-15 | 2017-12-15 | Method for forming groove |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108109909A CN108109909A (en) | 2018-06-01 |
| CN108109909B true CN108109909B (en) | 2020-08-28 |
Family
ID=62216303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711354008.8A Expired - Fee Related CN108109909B (en) | 2017-12-15 | 2017-12-15 | Method for forming groove |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108109909B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108962729A (en) * | 2018-06-25 | 2018-12-07 | 深圳元顺微电子技术有限公司 | A kind of preparation method of groove MOS field effect transistor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001168217A (en) * | 1999-12-10 | 2001-06-22 | Sharp Corp | Semiconductor storage device, and manufacturing method thereof |
| CN101625967A (en) * | 2009-07-28 | 2010-01-13 | 上海宏力半导体制造有限公司 | Preparation method for forming narrow trench structure in polysilicon film layer |
| CN102088035A (en) * | 2010-09-21 | 2011-06-08 | 上海韦尔半导体股份有限公司 | Trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and manufacturing method thereof |
-
2017
- 2017-12-15 CN CN201711354008.8A patent/CN108109909B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001168217A (en) * | 1999-12-10 | 2001-06-22 | Sharp Corp | Semiconductor storage device, and manufacturing method thereof |
| CN101625967A (en) * | 2009-07-28 | 2010-01-13 | 上海宏力半导体制造有限公司 | Preparation method for forming narrow trench structure in polysilicon film layer |
| CN102088035A (en) * | 2010-09-21 | 2011-06-08 | 上海韦尔半导体股份有限公司 | Trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108109909A (en) | 2018-06-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7208379B2 (en) | Pitch multiplication process | |
| US7767530B2 (en) | Transistor having recess channel and fabricating method thereof | |
| US9508609B2 (en) | Fin field effect transistor and method for forming the same | |
| US10714613B2 (en) | Semiconductor device | |
| EP3282485A1 (en) | Semiconductor device and fabrication method thereof | |
| KR101026479B1 (en) | Semiconductor device and manufacturing method of the same | |
| CN108109909B (en) | Method for forming groove | |
| EP3285298A1 (en) | Electrostatic discharge protection structure and fabricating method thereof | |
| KR20040002204A (en) | Semiconductor device and method for manufacturing the same | |
| CN104638011B (en) | A kind of groove MOSFET device and preparation method thereof | |
| US20200243657A1 (en) | Multi-trench MOSFET and method for fabricating the same | |
| CN114497215A (en) | Semiconductor structure and forming method thereof | |
| KR0137811B1 (en) | Fabrication method of semiconductor device | |
| CN104779273A (en) | Gate structure of CMOS device and manufacturing method of gate structure | |
| CN217468441U (en) | Silicon carbide semiconductor device | |
| KR100950758B1 (en) | Method of manufacturing semiconductor device | |
| JP2012033841A (en) | Semiconductor device and manufacturing method of the same | |
| KR100973264B1 (en) | Manufacturing method of semiconductor device | |
| CN107785263B (en) | Field effect transistor with multiple width electrode structure and its manufacturing method | |
| KR100819644B1 (en) | Method for manufacturing of semiconductor device | |
| JPH11177086A (en) | Vertical field-effect transistor and manufacture thereof | |
| KR100771536B1 (en) | Method of fabricating the semiconductor device having recessed channel | |
| KR100680411B1 (en) | Method for forming semiconductor device | |
| CN114188404A (en) | Source end process method of LDMOS device | |
| KR100713937B1 (en) | Method of manufacturing semiconductor device with recess gate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20200806 Address after: 210000 Kechuang building, Futian Road, Zhetang street, Lishui Economic Development Zone, Nanjing City, Jiangsu Province Applicant after: Nanjing Lishui hi tech Venture Capital Management Co.,Ltd. Address before: 518000 Guangdong city of Shenzhen province Baoan District Fuyong Street Peace community Junfeng Industrial Zone A3 building the first floor Applicant before: SHENZHEN JINGTE SMART MANUFACTURING TECHNOLOGY Co.,Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20200828 Termination date: 20201215 |