CN108090001A - A kind of kernel DMA stable states dispatching method and device - Google Patents
A kind of kernel DMA stable states dispatching method and device Download PDFInfo
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- CN108090001A CN108090001A CN201711310406.XA CN201711310406A CN108090001A CN 108090001 A CN108090001 A CN 108090001A CN 201711310406 A CN201711310406 A CN 201711310406A CN 108090001 A CN108090001 A CN 108090001A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/28—DMA
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Abstract
The present invention provides a kind of kernel DMA stable states dispatching methods and device, this method to include：When detecting system sequence exception, sequential mapping table is called；According to the working condition of the mapping relations control system hardware device of the sequential mapping table, to be modified to sequential to be adjusted.As it can be seen that the method for the present invention solves the problems, such as steadily carry out direct memory access during system sequence exception.When system sequence is inconsistent, by the way that sequential mapping table is called to be modified and then according to the mapping relations of sequential mapping table to system sequence.The sequential mapping table only record system sequence it is normal when steady state data, can for correct sequential necessary basis be provided.The present embodiment is also controlled by the hardware device to system, DMA access errors situations caused by correcting sequential exception, DMA scheduling features are completed by algorithm logic, system is made to recover the gross errors such as legacy operating system kernel hang-up caused by normal working condition, avoiding accidental sequential exception.
Description
Technical field
The present invention relates to field of computer technology, more particularly to a kind of kernel DMA stable states dispatching method and device.
Background technology
At present, with the continuous development of Godson CPU technology, the various embedded products based on Godson CPU are also got over
More widely to apply.At this stage, largely the embedded product based on Godson CPU has been increasingly being applied to government, state
Fields, the autonomous extensive computation processors of the Godson CPU as domestic first item maturation such as anti-, public health, finance exist
China occupies the larger market share in special field.It is as a kind of extensive, high-performance, multi-core central operation processing
Device, the low speed communication mode for relying solely on conventional hardware implement of interruption function hardware device and internal storage access hinder system significantly
Overall performance, there is an urgent need for one kind can with the scheduling mode of direct memory access (DMA, Direct Memory Access), to
Accelerate hardware and the efficiency to communicate between operating system.
At this stage, processor hardware, hardware dma controller and operating system are passed through on Loongson number 3 processor
Kernel dispatching algorithm realizes basic DMA scheduling features.But due to the limitation of processor country flow technique, in memory
The feelings of the system sequences entanglement such as unstable or system delay are commonly present when on the cycle is synchronous with the clock that CPU cache calls
Condition.If at this point, still can not ensure that the sequential of system is completely the same using the processing mode of the prior art, traditional behaviour is be easy to cause
Make the gross errors such as system kernel hang-up, seriously affect the stable operation of system.
The content of the invention
In view of the above problems, it is proposed that the present invention overcomes the above problem in order to provide one kind or solves at least partly
State the kernel DMA stable states dispatching method of problem and corresponding device.
One side according to the invention provides a kind of kernel DMA stable state dispatching methods, including：
When detecting system sequence exception, sequential mapping table is called；
According to the working condition of the mapping relations control system hardware device of the sequential mapping table, with to sequential to be adjusted
It is modified.
Optionally, when detecting system sequence exception, sequential mapping table is called, including：
When detecting system sequence exception, system sequence state machine is switched into sequential anomalous mode；
Markov verification sequence state is called according to the sequential anomalous mode of the sequential state machine by kernel dispatching unit
Mapping table.
Optionally, Markov verification sequence is called according to the sequential anomalous mode of the sequential state machine by kernel dispatching unit
After row state mapping map, further include：
When activating the sequential time delay state of the sequential state machine, and the sequential state machine being switched to by sequential anomalous mode
Sequence deferred mode.
Optionally, when system sequence state machine is sequential anomalous mode, further include：
Each register informations of CPU are placed in by closed state by system call function by the kernel dispatching unit；
System bus is placed in by closed state by system call function by the kernel dispatching unit, and forbids the system
The read operation for bus I/O data of uniting.
Optionally, adjusted according to the working condition of the mapping relations control system hardware device of the sequential mapping table with treating
Whole sequential is modified, including：
Letter is called according to the mapping relations calling system of Markov verification sequence state mapping map by kernel dispatching unit
Number controls the working condition of CPU and dma controller to be modified to sequential to be adjusted.
Optionally, by kernel dispatching unit according to the mapping relations calling system of Markov verification sequence state mapping map
Call function controls the working condition of CPU and dma controller to be modified to sequential to be adjusted, including：
Idling conditions is in using system call function control CPU and dma controller by kernel dispatching unit, wherein, institute
It states CPU and dma controller is in duration the reflecting according to the Markov verification sequence state mapping map of idling conditions
The relation of penetrating determines；
Using system call function the value of each registers of CPU and each storage unit is controlled to maintain by kernel dispatching unit
Value under one normal cycle.
Optionally, before sequential mapping table is called, further include：
Acquisition system carries out the data message of DMA access under sequential normal condition, wherein, the data message at least wraps
The total degree and each DMA for including DMA access access consumed cpu clock periodicity；
Mathematical model training is carried out to the data message of the acquisition according to Markov verification sequence, generates Markov
Verification sequence state mapping map.
Optionally, the kernel DMA stable states scheduling is applied to Loongson platform.
Other side according to the invention additionally provides a kind of kernel DMA stable state dispatching devices, including：
Calling module is configured to when detecting system sequence exception, calls sequential mapping table；
Correcting module is configured to the working condition of the mapping relations control system hardware device according to the sequential mapping table
To be modified to sequential to be adjusted.
Optionally, the calling module, is additionally configured to：
When detecting system sequence exception, system sequence state machine is switched into sequential anomalous mode；
Markov verification sequence state is called according to the sequential anomalous mode of the sequential state machine by kernel dispatching unit
Mapping table.
Optionally, described device further includes：
Active module, is configured to activate the sequential time delay state of the sequential state machine, and by the sequential state machine by when
Sequence anomalous mode switches to sequential time delay state.
Optionally, described device further includes：
Control module is configured to be put each register informations of CPU by system call function by the kernel dispatching unit
In closed state；
System bus is placed in by closed state by system call function by the kernel dispatching unit, and forbids the system
The read operation for bus I/O data of uniting.
Optionally, the correcting module, is additionally configured to：
Letter is called according to the mapping relations calling system of Markov verification sequence state mapping map by kernel dispatching unit
Number controls the working condition of CPU and dma controller to be modified to sequential to be adjusted.
Optionally, the correcting module, is additionally configured to：
Idling conditions is in using system call function control CPU and dma controller by kernel dispatching unit, wherein, institute
It states CPU and dma controller is in duration the reflecting according to the Markov verification sequence state mapping map of idling conditions
The relation of penetrating determines；
Using system call function the value of each registers of CPU and each storage unit is controlled to maintain by kernel dispatching unit
Value under one normal cycle.
Optionally, described device further includes：
Acquisition module is configured to the data message that acquisition system carries out DMA access under sequential normal condition, wherein, institute
It states data message and accesses consumed cpu clock periodicity including at least the DMA total degrees accessed and each DMA；
Generation module is configured to carry out mathematical model instruction to the data message of the acquisition according to Markov verification sequence
Practice, generate Markov verification sequence state mapping map.
Other side according to the invention, additionally provides a kind of electronic equipment, including：
Processor；And
The memory of storage computer executable instructions is arranged to, the executable instruction makes the place when executed
Device is managed to perform according to kernel DMA stable state dispatching methods described in any one of the above embodiments.
Other side according to the invention additionally provides a kind of computer readable storage medium, wherein, the computer
The one or more programs of readable storage medium storing program for executing storage, one or more of programs are worked as to be set by the electronics including multiple application programs
During standby execution so that the electronic equipment is performed according to kernel DMA stable state dispatching methods described in any one of the above embodiments.
Kernel DMA stable state dispatching methods according to the invention, can first be detected the time sequence status of system, work as inspection
When measuring system sequence exception, sequential mapping table is called.Further, controlled according to the mapping relations of the sequential mapping table called
The working condition of system hardware equipment, to be modified to sequential to be adjusted.As it can be seen that the method for the present invention can be applied to hardware
CPU, cache memory cache, dma controller and the inconsistent situation of Memory Controller Hub sequential, solve existing skill
The problem of smoothly can not carrying out direct memory access when system sequence exception in art.Specifically, the present embodiment is in system
Sequence occur it is inconsistent when, can by call specific sequential mapping table and then according to the mapping relations of sequential mapping table to system
Sequential be modified.The sequential mapping table of the present embodiment only record system sequence it is normal when steady state data, using its as system
The reference for sequential of uniting can provide necessary basis to correct sequential.In addition, the embodiment of the present invention is in system sequence exception,
It is controlled, is corrected due to DMA access errors situation caused by sequential exception by the hardware device to system, further,
DMA scheduling features are completed by algorithm logic in makeover process, system is made to recover to normal working condition, is avoided accidental
The gross errors such as legacy operating system kernel hang-up caused by sequential exception.
Above description is only the general introduction of technical solution of the present invention, in order to better understand the technological means of the present invention,
And can be practiced according to the content of specification, and in order to allow above and other objects of the present invention, feature and advantage can
It is clearer and more comprehensible, below the special specific embodiment for lifting the present invention.
According to the accompanying drawings to the detailed description of the specific embodiment of the invention, those skilled in the art will be brighter
The above and other objects, advantages and features of the present invention.
Description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this field
Technical staff will be apparent understanding.Attached drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings：
Fig. 1 is kernel DMA stable states dispatching method flow chart according to an embodiment of the invention；
Fig. 2 is Utopian DMA time diagrams according to an embodiment of the invention；
Fig. 3 is that typical case's DMA sequential according to an embodiment of the invention is crossed the border schematic diagram；
Fig. 4 is the composition structure diagram of Markov verification sequence module according to an embodiment of the invention；
Fig. 5 is the different conditions schematic diagram of sequential state machine according to an embodiment of the invention；
Fig. 6 is the particular flow sheet of kernel DMA stable state dispatching methods according to an embodiment of the invention；
Fig. 7 is the first schematic diagram of kernel DMA stable state dispatching devices according to an embodiment of the invention；
Fig. 8 is second of schematic diagram of kernel DMA stable state dispatching devices according to an embodiment of the invention；
Fig. 9 is according to an embodiment of the invention for performing kernel DMA stable state dispatching methods according to the present invention
The block diagram of computing device；And
Figure 10 is according to an embodiment of the invention steady for keeping or carrying realization kernel DMA according to the present invention
The storage unit of the program code of state dispatching method.
Specific embodiment
The exemplary embodiment of the disclosure is more fully described below with reference to accompanying drawings.Although the disclosure is shown in attached drawing
Exemplary embodiment, it being understood, however, that may be realized in various forms the disclosure without should be by embodiments set forth here
It is limited.On the contrary, these embodiments are provided to facilitate a more thoroughly understanding of the present invention, and can be by the scope of the present disclosure
Completely it is communicated to those skilled in the art.
At present, when realizing that hardware device is operated with internal storage access in computer technology, rely solely in traditional hardware
This low speed communication mode that breaks has hindered the overall performance of system significantly.Therefore, it is with operation to improve hardware device
Communication efficiency between system, the prior art has employed one kind can be with the scheduling mode of direct memory access (DMA).DMA technology
It is direct memory access technology, is a kind of mechanism of fast transfer of data.The importance of DMA technology is to utilize it into line number
During according to access CPU is not required to be intervened, the efficiency that system performs application program can be improved.
But the premise that some direct memory access methods needs existing at this stage rely on is CPU, caches
Device cache, dma controller and Memory Controller Hub are completely unified in sequential, and there is no the situations of sequential entanglement.Due to domestic
The manufacturing process in CPU fields is limited, when domestic CPU is used to carry out aforesaid operations, does not ensure that system sequence is completely the same.
However, when system sequence exception, if would generally be caused yet by existing direct memory access method in legacy operating system
The gross errors such as core hang-up, seriously affect the stable operation of system.
In order to solve the above-mentioned technical problem, the present invention proposes a kind of kernel DMA stable state dispatching methods.Fig. 1 is according to this
The kernel DMA stable state dispatching method flow charts of invention one embodiment.As shown in Figure 1, kernel DMA stable state dispatching methods at least wrap
Step S102 is included to step S104：
Step S102, when detecting system sequence exception, sequential mapping table is called；
Step S104, according to the working condition of the mapping relations control system hardware device of sequential mapping table, adjusted with treating
Whole sequential is modified.
Kernel DMA stable state dispatching methods according to the invention, can first be detected the time sequence status of system, work as inspection
When measuring system sequence exception, sequential mapping table is called.Further, controlled according to the mapping relations of the sequential mapping table called
The working condition of system hardware equipment, to be modified to sequential to be adjusted.As it can be seen that the method for the present invention can be applied to hardware
CPU, cache, dma controller and the inconsistent situation of Memory Controller Hub sequential, solve and work as system sequence in the prior art
The problem of direct memory access can not be smoothly carried out when abnormal.Specifically, the present embodiment system sequence occur it is inconsistent when,
It can be by the way that specific sequential mapping table be called to be modified and then the mapping relations according to sequential mapping table to the sequential of system.
The sequential mapping table of the present embodiment only record system sequence it is normal when steady state data, using it as the reference of system sequence, energy
It is enough to provide necessary basis to correct sequential.In addition, the embodiment of the present invention passes through the hardware to system in system sequence exception
Equipment is controlled, and is corrected due to DMA access errors situation caused by sequential exception, further, is passed through calculation in makeover process
Method logic completes DMA scheduling features, and system is made to recover biography caused by normal working condition, avoiding accidental sequential exception
The gross errors such as system operating system nucleus hang-up.
In the present embodiment, Fig. 2 shows Utopian DMA time diagrams according to an embodiment of the invention.Ginseng
See Fig. 2, the CPU timing cycles of the present embodiment are 1.2us, in practical operation, can CPU timing cycles be divided into two parts,
CPU timing cycles first portion (referring to Fig. 2 cache1 sequential 0.6us) by CPU grasp system control, by CPU pairs
System bus and other operations are controlled.CPU timing cycles second portion (referring to Fig. 2 cache2 sequential 0.6us) by
Dma controller grasp system control, by dma controller to system bus and other operate and control.As shown in Fig. 2,
CPU performs corresponding control operation with dma controller in the control time each set in preferable time series, no
There are sequential it is imperfect caused by sequential entanglement ask.It thus will not when hardware device and Memory Controller Hub interact
There are the gross errors such as kernel hang-up caused by sequential entanglement.
But the defects of due to domestic design, production technology, partial domestic cpu motherboard can not be completely dependent on hardware reality
Now whole direct memory access function.Also, DMA sequential is to rely on operating system nucleus and realize to turn with the right of CPU sequential
It hands over, in the hand-off process of right, is often present with the phenomenon that system sequence is inconsistent.Specifically, Fig. 3 is shown according to this hair
The typical DMA sequential of bright one embodiment is crossed the border schematic diagram.Referring to Fig. 3, DMA control sequentials, which are crossed the border, is happened at kernel application DMA
Period be more than specified CPU timing cycles when, since it crosses next cpu cycle, then to next cpu cycle data into
Gone unauthorized access (when crossing the border in such as Fig. 3 preamble section original should by CPU grasp system control, to system bus and other behaviour
It is controlled, but the stage shown in Fig. 3 still controls system bus by dma controller, and DMA controls have occurred at this time
Sequential is crossed the border, and is illegal read/write operation in the operation that data/address bus carries out).DMA sequential at this time is got over zone phenomenon and can be destroyed always
It is abnormal to generate operating system for data in line.And the access method of traditional direct memory, although most of platforms can be solved
The demand of direct memory access, but it is consistent feelings that it, which is only limitted to processing hardware CPU, cache and Memory Controller Hub sequential,
Condition can not be operated in the nonsynchronous direct memory access of completing of the system sequences sequence such as memory, cache.
The problems such as the present embodiment legacy operating system kernel caused by order to solve above system sequential exception is hung up, inside
Markov verification sequence module is additionally arranged in core, for correcting illegal read/write access behaviour when sequential is crossed the border on system bus
Make, solve the inconsistence problems of CPU, cache, dma controller and Memory Controller Hub in sequential.In system sequence uniformity
When clashing, the method for the present embodiment can rely on the verification scheme and buffering area of Markov verification sequence module itself
Complete the amendment operation of system sequence so that can also reach identical with DMA access under normal circumstances in system sequence exception
Effect.
The Markov verification sequence of the present embodiment is a kind of timing verification optimization unrelated with time in the past of current state
The general designation of mathematical model.In addition, the current pervious System History state that the present embodiment is obtained based on Markov verification sequence
It is relatively independent for (i.e. currently later future state) in the future, the two has no actual association, in the present embodiment, can be with
Above-mentioned independent system mode is known as " Markov ".
Further, Fig. 4 shows the composition structure of Markov verification sequence module according to an embodiment of the invention
Schematic diagram.As shown in figure 4, the Markov verification sequence module that the present embodiment proposes can include system sequence state machine, horse
Er Kefu verification sequences state mapping map, kernel dispatching unit.Wherein, kernel dispatching unit is increased in operating system nucleus
Separate unit, be entire Markov verification sequence module base unit.It is internally responsible for coordinating system sequence state machine
With this two-part work of Markov verification sequence state mapping map, externally it is responsible for through system call function systemcall
Control instruction is sent to bus and hardware dma controller.The present embodiment by kernel dispatching unit this core component not only
Markov verification sequence mould other component in the block is mobilized, realizes the association of Markov verification sequence inside modules
Work is adjusted, and system hardware equipment can accordingly be controlled according to system different time sequence status.As it can be seen that kernel tune
Degree unit plays the role of extremely important in the present embodiment.
In addition, the present embodiment further relates to system sequence state machine, Fig. 5 shows sequential according to an embodiment of the invention
The different conditions schematic diagram of state machine.As shown in figure 5, system sequence state machine is divided into three kinds of fundamental system states, including sequential
Normal state, sequential anomalous mode, sequential time delay state.Under normal conditions, system is in sequential normal state.It in the present embodiment, can be with
The time sequence status of system is detected first, specifically, a detection unit can be activated individually by kernel to system
Time sequence status is detected.When detecting that system sequence is in normal condition, without performing other operations.But it is when detecting
During sequential exception of uniting, show that the situation that sequential is crossed the border occurs in system, it at this time can be normal by sequential by system sequence state machine
State switches to sequential anomalous mode.
Further, in the present embodiment, when sequential state machine is in sequential anomalous mode, kernel dispatching unit can be passed through
Call Markov verification sequence state mapping map.And then it is reflected by kernel dispatching unit according to Markov verification sequence state
The working condition of the mapping relations control system hardware device of firing table, to reach the mesh being modified to following sequential to be adjusted
's.
Specifically, the Markov verification sequence state mapping map of the present embodiment be based on Markov verification sequence this
Timing verification optimized mathematical model and generate.When Markov verification sequence is that a kind of current state is unrelated with time in the past
Sequence verifies optimized mathematical model, that is to say, that can weigh Future Data with early experience data, i.e., at the following a certain moment
Acting proceeding by for task can be weighed with the empirical data of early stage stable state.In the present embodiment, Markov verification sequence
Row are only counted in sequential under normal circumstances, total cpu clock cycle that whole hardware are undergone when DMA is accessed, for estimating it
Time data in sequential stable state.When there is unstable state situation, can be redeployed according to stable state historical data.
In addition, Markov verification sequence also has a kind of special circumstances, i.e., in sequential under normal circumstances, a certain hardware exists
Total cpu cycle that DMA is undergone when accessing is uncertain.It should be noted that above-mentioned special circumstances are derived from clock in fact
The uniformity of frequency is not present in computer hardware engineering field, but in order to prevent in philosophy special circumstances generation,
The maximum CPU sequential of consumption and N number of cpu clock cycle and as statistics end value can be cancelled in the present embodiment.
Therefore, the present embodiment is when generating Markov verification sequence mapping table, can obtain system first in sequential just
The data message of DMA access is carried out under normal state.The data message includes at least total degree and each DMA access that DMA is accessed
The cpu clock periodicity consumed.Further, mathematical modulo is carried out to acquired data message according to Markov verification sequence
Type training generates Markov verification sequence state mapping map.It should be noted that the number that the DMA that the present embodiment obtains is accessed
It is believed that breath is only to enumerate, the present invention can also obtain a variety of relevant data according to actual demand, further according to Markov
Verification sequence carries out mathematical model training to acquired data, to generate the higher Markov verification sequence state of accuracy
Mapping table, the present embodiment are not specifically limited the related data extracted.
For the Markov verification sequence state mapping map of the present embodiment only by taking table 1 as an example, table 1 shows according to the present invention one
The Markov verification sequence state mapping map of certain encrypted card of a embodiment.Referring to table 1, encrypted card 1 is normal in previous sequential
In the case of, direct memory access 450 times (being only exemplified by the present embodiment 2 times, other are not shown) occurs altogether, accesses every time
The cpu clock cycle consumed in the process is 30 cpu cycles.On the basis of this Markov verification sequence state mapping map
On, if sequential exception, according to previous statistics experience, this direct memory access have occurred under certain particular case
Clock cycle should also be 30 cpu cycles.
Table 1
After above-mentioned steps execution terminates, Markov verification sequence state mapping map can be obtained.Meanwhile in sequential shape
When state machine is in sequential anomalous mode, since the data in system bus can be destroyed, it is abnormal to generate operating system.At this point, according to this
Each register informations of CPU can be placed in closed state by the method for invention by kernel dispatching unit by system call function.Separately
On the one hand, system bus can also be placed in by closed state by system call function by kernel dispatching unit, and forbids system
The read-write operation of bus I/O data.It can be in system sequence exception, to each hardware device of system by the method for the present invention
Working condition is controlled the gross errors such as hangs up to avoid kernel caused by system sequence exception.
In addition, after above-mentioned each operation is performed and terminated, the sequential time delay state of sequential state machine can also be activated, and by when
Sequence state machine switches to sequential time delay state by sequential anomalous mode.And then in sequential time delay state, execution step S104, by kernel tune
Working condition of the unit according to the mapping relations control system hardware device of Markov verification sequence state mapping map is spent, with right
Sequential to be adjusted is modified.It specifically, can be by kernel dispatching unit according to Markov verification sequence state mapping map
Mapping relations calling system call function controls the working condition of CPU and dma controller to be modified to sequential to be adjusted.
In the present embodiment, idling conditions can be in using system call function control CPU and dma controller by kernel dispatching unit,
Sequential normal state is returned after timing verification is normal.In the present embodiment, CPU and dma controller are in continuing for idling conditions
Time determines according to the mapping relations of Markov verification sequence state mapping map.Also, the present embodiment can also be by kernel tune
Degree unit controls the value of each registers of CPU and each storage unit to maintain under a upper normal cycle using system call function
Value.
Further, according to the method for the present embodiment, system sequence completion is being repaiied by Markov verification sequence
After just, system sequence can be verified again.As it has been found that go successively to sequential anomalous mode if problem, and then according to upper
It states step to be again modified system sequence, normal state is returned if inerrancy is corrected.
It follows that the present embodiment can in time switch to system sequence state machine when finding system sequence exception
Sequential anomalous mode.Also, in system sequence anomalous mode, the information of each registers of CPU and system bus is hung up and is closed, and is prohibited
Locking system bus I/O data read-write operations.Further, the method according to the invention can also be temporary in time in system sequence exception
Stop the various illegal operations of equipment, reduce due to sequential is abnormal and caused by operating system there is the probability of mistake.In addition, this
Embodiment can also call Markov verification sequence state mapping map, and activation system sequential is prolonged in system sequence exception
Slow state.And then system sequence deferred mode according to the mapping relations of Markov verification sequence state mapping map to it is to be adjusted when
Sequence is modified.In specific makeover process, each registers of CPU and storage unit can be maintained in the nearest normal cycle of CPU
Under value and control CPU idle running until system sequence amendment complete.In an optional embodiment, kernel DMA of the invention
Stable state dispatching method is applied under Loongson platform.
The kernel DMA stable state dispatching methods of the present invention are described in detail with a specific embodiment below.
Embodiment one
Fig. 6 is the particular flow sheet of kernel DMA stable state dispatching methods according to an embodiment of the invention.
In the present embodiment, step S601, system normal operation under sequential normal state is first carried out；.
Step S602 is further performed, whether the current sequential of detecting system is abnormal, if so, step S603 is performed, if it is not, returning
Return the system sequence normal state of step S601；
System sequence state machine is switched to sequential anomalous mode by step S603 by sequential normal state；
Step S604 calls Markov verification sequence mapping table to carry out system sequence correction；
Step S605 activates sequential time delay state, and system sequence state machine is switched to sequential time delay by sequential anomalous mode
State；
Step S606 completes timing verification.
It should be noted that in the present embodiment, step S604 and step S605, can be with there is no specific sequencing
According to the present example the step of, calls Er Kefu verification sequence mapping tables to be corrected system sequence first, it then activates during system
The sequential time delay state of sequence state machine.Furthermore it is also possible to the sequential time delay state of activation system sequential state machine first, is further called
Er Kefu verification sequence mapping tables are corrected system sequence, can be carried out at the same time with two steps, the present embodiment to this not
It is specifically limited.
In addition, in the present embodiment, after step S606 execution terminates, system sequence verification is completed.At this point, can also be by
Kernel restarts detection unit, and the time sequence status of system is detected.If detecting system sequence exception, re-execute
System sequence state machine until system sequence is normal, is switched to sequential normal state by step S603- step S605.
Based on same inventive concept, invention provides a kind of kernel DMA stable state dispatching devices, and Fig. 7 is according to this hair
The first schematic diagram of the kernel DMA stable state dispatching devices of bright one embodiment.As shown in fig. 7, comprises：
Calling module 710 is configured to when detecting system sequence exception, calls sequential mapping table；
Correcting module 720 is coupled with calling module 710, is configured to the mapping relations control system according to sequential mapping table
The working condition of hardware device is to be modified sequential to be adjusted.
In a preferred embodiment, calling module 710 are additionally configured to：
When detecting system sequence exception, system sequence state machine is switched into sequential anomalous mode；
The mapping of Markov verification sequence state is called according to the sequential anomalous mode of sequential state machine by kernel dispatching unit
Table.
In a preferred embodiment, as shown in figure 8, the device further includes：
Active module 730 is configured to the sequential time delay state of activation sequential state machine, and sequential state machine is abnormal by sequential
State switches to sequential time delay state.
In a preferred embodiment, as shown in figure 8, the device further includes：
Control module 740 is configured to be placed in each register informations of CPU by system call function by kernel dispatching unit
Closed state；
System bus is placed in by closed state by system call function by kernel dispatching unit, and forbids system bus I/
The read operation of O data.
In a preferred embodiment, correcting module 720 are additionally configured to：
Letter is called according to the mapping relations calling system of Markov verification sequence state mapping map by kernel dispatching unit
Number controls the working condition of CPU and dma controller to be modified to sequential to be adjusted.
In a preferred embodiment, correcting module 720 are additionally configured to：
Idling conditions is in using system call function control CPU and dma controller by kernel dispatching unit, wherein, CPU
And dma controller be in idling conditions duration it is true according to the mapping relations of Markov verification sequence state mapping map
It is fixed；
Using system call function the value of each registers of CPU and each storage unit is controlled to maintain by kernel dispatching unit
Value under one normal cycle.
In a preferred embodiment, as shown in figure 8, the device further includes：
Acquisition module 810 is configured to the data message that acquisition system carries out DMA access under sequential normal condition, wherein,
Data message includes at least the total degree of DMA access and each DMA accesses consumed cpu clock periodicity；
Generation module 820 is coupled with acquisition module 810, is configured to the data to acquisition according to Markov verification sequence
Information carries out mathematical model training, generates Markov verification sequence state mapping map.
Kernel DMA stable states dispatching method and device according to the present invention can reach following advantageous effect：
Kernel DMA stable state dispatching methods according to the invention, can first be detected the time sequence status of system, work as inspection
When measuring system sequence exception, sequential mapping table is called.Further, controlled according to the mapping relations of the sequential mapping table called
The working condition of system hardware equipment, to be modified to sequential to be adjusted.As it can be seen that the method for the present invention can be applied to hardware
CPU, cache, dma controller and the inconsistent situation of Memory Controller Hub sequential, solve and work as system sequence in the prior art
The problem of direct memory access can not be smoothly carried out when abnormal.Specifically, the present embodiment system sequence occur it is inconsistent when,
It can be by the way that specific sequential mapping table be called to be modified and then the mapping relations according to sequential mapping table to the sequential of system.
The sequential mapping table of the present embodiment only record system sequence it is normal when steady state data, using it as the reference of system sequence, energy
It is enough to provide necessary basis to correct sequential.In addition, the embodiment of the present invention passes through the hardware to system in system sequence exception
Equipment is controlled, and is corrected due to DMA access errors situation caused by sequential exception, further, is passed through calculation in makeover process
Method logic completes DMA scheduling features, and system is made to recover biography caused by normal working condition, avoiding accidental sequential exception
The gross errors such as system operating system nucleus hang-up.
In the specification provided in this place, numerous specific details are set forth.It is to be appreciated, however, that the implementation of the present invention
Example can be put into practice without these specific details.In some instances, well known method, structure is not been shown in detail
And technology, so as not to obscure the understanding of this description.
Similarly, it should be understood that in order to simplify the disclosure and help to understand one or more of each inventive aspect,
Above in the description of exemplary embodiment of the present invention, each feature of the invention is grouped together into single implementation sometimes
In example, figure or descriptions thereof.However, the method for the disclosure should be construed to reflect following intention：I.e. required guarantor
Shield the present invention claims the more features of feature than being expressly recited in each claim.It is more precisely, such as following
Claims reflect as, inventive aspect is all features less than single embodiment disclosed above.Therefore,
Thus the claims for following specific embodiment are expressly incorporated in the specific embodiment, wherein each claim is in itself
Separate embodiments all as the present invention.
Those skilled in the art, which are appreciated that, to carry out adaptively the module in the equipment in embodiment
Change and they are arranged in one or more equipment different from the embodiment.It can be the module or list in embodiment
Member or component be combined into a module or unit or component and can be divided into addition multiple submodule or subelement or
Sub-component.In addition at least some in such feature and/or process or unit exclude each other, it may be employed any
Combination is disclosed to all features disclosed in this specification (including adjoint claim, summary and attached drawing) and so to appoint
Where all processes or unit of method or equipment are combined.Unless expressly stated otherwise, this specification is (including adjoint power
Profit requirement, summary and attached drawing) disclosed in each feature can be by providing the alternative features of identical, equivalent or similar purpose come generation
It replaces.
In addition, it will be appreciated by those of skill in the art that although some embodiments described herein include other embodiments
In included some features rather than other feature, but the combination of the feature of different embodiments means in of the invention
Within the scope of and form different embodiments.For example, in detail in the claims, embodiment claimed it is one of arbitrary
It mode can use in any combination.
The all parts embodiment of the present invention can be with hardware realization or to be run on one or more processor
Software module realize or realized with combination thereof.It will be understood by those of skill in the art that it can use in practice
Microprocessor or digital signal processor (DSP) are realized in kernel DMA stable state controlling equipments according to embodiments of the present invention
Some or all components some or all functions.The present invention is also implemented as performing side as described herein
The some or all equipment or program of device (for example, computer program and computer program product) of method.It is such
Realizing the program of the present invention can may be stored on the computer-readable medium or can have the shape of one or more signal
Formula.Such signal can be downloaded from internet website to be obtained either providing or with any other shape on carrier signal
Formula provides.
The embodiment of the present invention additionally provides a kind of electronic equipment, including processor and be arranged to storage computer can
The memory executed instruction, executable instruction make processor perform the kernel according to any one embodiment above when executed
DMA stable state dispatching methods.
The embodiment of the present invention additionally provides a kind of computer storage media, wherein, computer-readable recording medium storage one
A or multiple programs, one or more programs by the electronic equipment including multiple application programs when being performed so that electronic equipment
Perform the kernel DMA stable state dispatching methods of any embodiment above.
For example, Fig. 9 shows the computing device that can realize kernel DMA stable state dispatching methods.The computing device is traditionally
Include the computer program product or computer-readable medium of 920 form of processor 910 and memory.Memory 920 can be with
It is the Electronic saving of such as flash memory, EEPROM (electrically erasable programmable read-only memory), EPROM, hard disk or ROM etc
Device.Memory 920 has storage for performing the memory space of the program code 931 of any method and step in the above method
930.For example, the memory space 930 of storage program code can include being respectively used to realize the various steps in above method
Each program code 931.These program codes can read or write from one or more computer program product
Into this one or more computer program product.These computer program products include such as hard disk, and compact-disc (CD) is deposited
The program code carrier of card storage or floppy disk etc.Such computer program product is usually for example shown in Fig. 10 portable
Or static memory cell.The storage unit can have the storage with 920 similar arrangement of memory in the computing device of Fig. 9
Section, memory space etc..Program code can be for example compressed in a suitable form.In general, storage unit includes performing sheet
The computer-readable code 931 ' of the method and step of invention, you can with the code read by such as 910 etc processor, when this
When a little codes are run by computing device, cause each step in the computing device method described above.
It should be noted that the present invention will be described rather than limits the invention for above-described embodiment, and ability
Field technique personnel can design alternative embodiment without departing from the scope of the appended claims.In the claims,
Any reference symbol between bracket should not be configured to limitations on claims.Word "comprising" does not exclude the presence of not
Element or step listed in the claims.Word "a" or "an" before element does not exclude the presence of multiple such
Element.The present invention can be by means of including the hardware of several different elements and being come by means of properly programmed computer real
It is existing.If in the unit claim for listing equipment for drying, several in these devices can be by same hardware branch
To embody.The use of word first, second, and third does not indicate that any order.These words can be explained and run after fame
Claim.
So far, although those skilled in the art will appreciate that detailed herein have shown and described multiple showing for the present invention
Example property embodiment, still, without departing from the spirit and scope of the present invention, still can according to the present disclosure directly
Determine or derive many other variations or modifications consistent with the principles of the invention.Therefore, the scope of the present invention is understood that and recognizes
It is set to and covers other all these variations or modifications.
Claims (10)
1. a kind of kernel DMA stable state dispatching methods, including：
When detecting system sequence exception, sequential mapping table is called；
According to the working condition of the mapping relations control system hardware device of the sequential mapping table, to be carried out to sequential to be adjusted
It corrects.
2. according to the method described in claim 1, it is characterized in that, when detecting system sequence exception, sequential mapping is called
Table, including：
When detecting system sequence exception, system sequence state machine is switched into sequential anomalous mode；
The mapping of Markov verification sequence state is called according to the sequential anomalous mode of the sequential state machine by kernel dispatching unit
Table.
3. according to the method described in claim 2, it is characterized in that, by kernel dispatching unit according to the sequential state machine when
After sequence anomalous mode calls Markov verification sequence state mapping map, further include：
The sequential time delay state of the sequential state machine is activated, and the sequential state machine is switched into sequential by sequential anomalous mode and is prolonged
Slow state.
4. according to the method described in claim 2, it is characterized in that, when system sequence state machine is sequential anomalous mode, also wrap
It includes：
Each register informations of CPU are placed in by closed state by system call function by the kernel dispatching unit；
System bus is placed in by closed state by system call function by the kernel dispatching unit, and forbids the system total
The read-write operation of line I/O data.
5. according to the method described in claim 1, it is characterized in that, mapping relations control system according to the sequential mapping table
The working condition of hardware device to be modified to sequential to be adjusted, including：
By kernel dispatching unit according to the mapping relations calling system call function control of Markov verification sequence state mapping map
The working condition of CPU and dma controller processed are to be modified sequential to be adjusted.
6. according to the method described in claim 5, it is characterized in that, by kernel dispatching unit according to Markov verification sequence shape
The mapping relations calling system call function control CPU of state mapping table and the working condition of dma controller are with to sequential to be adjusted
It is modified, including：
Idling conditions is in using system call function control CPU and dma controller by kernel dispatching unit, wherein, the CPU
And dma controller is in the duration of idling conditions according to the mapping relations of the Markov verification sequence state mapping map
It determines；
Using system call function the value of each registers of CPU and each storage unit is controlled to maintain upper one by kernel dispatching unit
Value under normal cycle.
7. according to the method described in claim 1, it is characterized in that, before sequential mapping table is called, further include：
Acquisition system carries out the data message of DMA access under sequential normal condition, wherein, the data message includes at least
The total degree and each DMA that DMA is accessed access consumed cpu clock periodicity；
Mathematical model training, generation Markov verification carry out the data message of the acquisition according to Markov verification sequence
Sequence state mapping table.
8. a kind of kernel DMA stable state dispatching devices, including：
Calling module is configured to when detecting system sequence exception, calls sequential mapping table；
Correcting module is configured to the working condition according to the mapping relations control system hardware device of the sequential mapping table with right
Sequential to be adjusted is modified.
9. a kind of electronic equipment, including：
Processor；And
The memory of storage computer executable instructions is arranged to, the executable instruction makes the processor when executed
Perform the kernel DMA stable state dispatching methods according to any one of claim 1-7.
10. a kind of computer readable storage medium, wherein, the computer-readable recording medium storage one or more program,
One or more of programs by the electronic equipment including multiple application programs when being performed so that the electronic equipment performs root
According to the kernel DMA stable state dispatching methods any one of claim 1-7.
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| CN201711310406.XA CN108090001B (en) | 2017-12-11 | 2017-12-11 | Kernel DMA (direct memory access) steady-state scheduling method and device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711310406.XA CN108090001B (en) | 2017-12-11 | 2017-12-11 | Kernel DMA (direct memory access) steady-state scheduling method and device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110737501A (en) * | 2018-07-18 | 2020-01-31 | 中标软件有限公司 | Method and system for realizing functions of check point and recovery point in Docker container |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1169193A (en) * | 1995-11-21 | 1997-12-31 | 昆腾公司 | Synchronous DMA transfer protocol |
| WO2005041421A1 (en) * | 2003-09-30 | 2005-05-06 | Telefonaktiebolaget L M Ericsson (Publ) | In-place data deinterleaving |
| CN101479802A (en) * | 2006-06-30 | 2009-07-08 | 莫塞德技术公司 | Synchronous memory read data capture |
| CN105912487A (en) * | 2016-04-07 | 2016-08-31 | 上海斐讯数据通信技术有限公司 | Data timing sequence equalizing method and system |
-
2017
- 2017-12-11 CN CN201711310406.XA patent/CN108090001B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1169193A (en) * | 1995-11-21 | 1997-12-31 | 昆腾公司 | Synchronous DMA transfer protocol |
| WO2005041421A1 (en) * | 2003-09-30 | 2005-05-06 | Telefonaktiebolaget L M Ericsson (Publ) | In-place data deinterleaving |
| CN101479802A (en) * | 2006-06-30 | 2009-07-08 | 莫塞德技术公司 | Synchronous memory read data capture |
| CN105912487A (en) * | 2016-04-07 | 2016-08-31 | 上海斐讯数据通信技术有限公司 | Data timing sequence equalizing method and system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110737501A (en) * | 2018-07-18 | 2020-01-31 | 中标软件有限公司 | Method and system for realizing functions of check point and recovery point in Docker container |
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