CN108063140B - Transistor structure, memory cell array and preparation method thereof - Google Patents
Transistor structure, memory cell array and preparation method thereof Download PDFInfo
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- CN108063140B CN108063140B CN201711206798.5A CN201711206798A CN108063140B CN 108063140 B CN108063140 B CN 108063140B CN 201711206798 A CN201711206798 A CN 201711206798A CN 108063140 B CN108063140 B CN 108063140B
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
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Abstract
The invention provides a transistor structure, a memory cell array and a preparation method, wherein the transistor preparation method comprises the following steps: providing a semiconductor substrate with an active region, and forming a groove structure in the active region; forming a dielectric layer at the bottom and the side wall of the groove structure; forming a word line surface layer on the bottom of the dielectric layer and the local side wall, and forming a word line entity layer comprising a filling part combined on the surface of the word line surface layer and a protruding part on the top of the filling part, wherein the top end of the word line surface layer is lower than the upper surface of the semiconductor substrate, the top end of the protruding part is higher than the top end of the word line surface layer and lower than the upper surface of the semiconductor substrate, and a side ditch is formed between the outer side wall of the protruding part and the dielectric layer; and the hole filling insulating layer covers the top end of the word line entity layer and the top end of the side ditch, and the side ditch is sealed to form an air cavity. Through the scheme, the transistor structure is prepared through the deposition and wet etching processes, the transistor with the insulating side channel is formed, and the intermediate dielectric layer of the capacitor is changed, so that parasitic capacitance is reduced, and the resistance of the transistor can be reduced.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a transistor structure and a preparation method thereof.
Background
Dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM) is a semiconductor memory device commonly used in computers and is composed of a number of repeated memory cells. Each memory cell is mainly composed of a transistor and a capacitor controlled by the transistor, and the memory cells are arranged in an array form, and each memory cell is electrically connected with each other through a word line and a bit line. With the increasing development of light, thin, short and small electronic products, the design of the dram device is also required to meet the requirements of high integration and high density and the trend of miniaturization, so as to increase the integration of the dram to speed up the operation speed of the device, and meet the requirements of consumers for miniaturized electronic devices.
However, in the above structure, the parasitic capacitance existing in the transistor structure of the memory still has a great influence on the device structure, and in addition, as the array of the dynamic random access memory is continuously reduced, the resistance of the buried gate word line is gradually increased, which affects the final performance of the device.
Therefore, it is necessary to provide a transistor structure, a memory cell array formed by the transistor structure, and a method for manufacturing the memory cell array to solve the above-mentioned problems.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a transistor structure, a memory cell array and a method for manufacturing the same, which are used for solving the problems of parasitic capacitance and transistor circuit resistance in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing a transistor structure, including the steps of:
1) Providing a semiconductor substrate with an active region, and forming a groove structure in the active region;
2) Forming a dielectric layer at the bottom and the side wall of the groove structure;
3) Forming a word line surface layer on the bottom and partial side walls of the dielectric layer, and forming a word line entity layer on the surface of the word line surface layer, wherein the word line entity layer comprises a filling part combined on the surface of the word line surface layer and a protruding part positioned on the top of the filling part, the top end of the word line surface layer is lower than the upper surface of the semiconductor substrate, the top end of the protruding part is higher than the top end of the word line surface layer and lower than the upper surface of the semiconductor substrate, and a side ditch is formed between the outer side wall of the protruding part and the dielectric layer; and
4) And forming a hole filling insulating layer in the groove structure, wherein the bottom of the hole filling insulating layer covers the top end of the word line entity layer and the top end of the side groove so as to seal the side groove to form an air cavity.
As a preferred embodiment of the present invention, the thickness of the word line surface layer is 0.8 to 5 nm to define the width of the air cavity.
As a preferable mode of the present invention, in step 1), the size of the opening of the trench structure is 10-50 nm; in the step 2), the thickness of the dielectric layer is 1-9 nanometers; in the step 4), the height of the air cavity is 1-40 nanometers.
As a preferred aspect of the present invention, in step 1), the step of forming the trench structure includes:
1-1) forming a mask layer with a window on the surface of the semiconductor substrate, wherein the window corresponds to the groove structure vertically; and
1-2) etching the semiconductor substrate based on the window to form the groove structure.
In step 2), the dielectric layer is formed by an In Situ Steam (ISSG) process.
As a preferred embodiment of the present invention, in step 3), the method further comprises the steps of: an adhesion layer is formed between the word line surface layer and the word line physical layer.
In a preferred embodiment of the present invention, in step 3), the step of forming the word line surface layer and the word line physical layer includes:
3-1) forming a first conductive material layer on the bottom, the side wall and the surface of the semiconductor substrate around the trench structure;
3-2) forming a second conductive material layer on the surface of the first conductive material layer, wherein the second conductive material layer fills the groove structure and extends to cover the first conductive material layer on the surface of the semiconductor substrate;
3-3) etching the first conductive material layer and the second conductive material layer to form a first conductive material portion and a second conductive material portion respectively, wherein a first interval is formed from the top end of the first conductive material portion to the upper surface of the semiconductor substrate and from the top end of the second conductive material portion to the upper surface of the semiconductor substrate; and
3-4) continuing to etch the first conductive material layer and the second conductive material layer through a wet etching process to form the word line surface layer and the word line entity layer respectively, wherein the word line surface layer and the semiconductor substrate surface have a second distance, the word line entity layer and the semiconductor substrate surface have a third distance, and the second distance is larger than the third distance so as to define the height of the protruding portion.
As a preferable mode of the invention, the first interval is 30-70 nanometers; the difference between the second spacing and the third spacing is 1-40 nanometers.
As a preferable mode of the present invention, in the step 3-4), the reagent for performing the wet etching includes ammonia (NH) 4 OH), hydrogen peroxide (H) 2 O 2 ) And water, wherein the proportion of the ammonia water, the hydrogen peroxide and the water in the mixed solution is sequentially 1 to 0.01 to 2 to 5 to 150.
In step 3-3), the first conductive material layer and the second conductive material layer are etched by an alternative etching process, wherein the alternative etching gas includes any two or three of sulfur hexafluoride, chlorine and argon.
As a preferred embodiment of the present invention, before the step 4), the method further comprises the steps of: and cleaning the surface of the word line entity layer by adopting a diluted hydrofluoric acid (DHF) reagent to remove surface byproducts, wherein the diluted hydrofluoric acid reagent comprises a mixed solution of hydrofluoric acid (HF) and water, and the ratio of the hydrofluoric acid to the water is 1 to 50-1000.
In a preferred embodiment of the present invention, in step 2), the material of the dielectric layer includes silicon oxide, in step 3), the material of the word line surface layer includes titanium nitride, in step 3), the material of the word line physical layer includes tungsten, and in step 4), the material of the via-filling insulating layer includes silicon nitride.
In a preferred embodiment of the present invention, in step 4), the hole-filling insulating layer is formed by an atomic layer deposition process so as not to damage the air chamber.
As a preferable scheme of the invention, the deposition rate of the atomic layer deposition process is 200-1000 nanometers/min.
The invention also provides a preparation method of the memory cell array, which comprises the following steps:
a) Forming a plurality of memory cells with transistor structures, wherein each memory cell is configured into a cell row and a cell column, the transistor structures are prepared by adopting the preparation method according to any scheme, and no active area of the transistor structures is connected with two capacitors; and
b) And connecting an address line to the word line physical layer of each memory cell in the cell row or the cell column to prepare a memory cell array, wherein the address line is used for controlling the memory cells.
The invention also provides a transistor structure comprising:
a semiconductor substrate having an active region;
a trench structure located within the active region of the semiconductor substrate;
the dielectric layer is positioned at the bottom and the side wall of the groove structure;
A word line surface layer positioned at the bottom and partial side wall of the dielectric layer, wherein the top end of the word line surface layer is lower than the upper surface of the semiconductor substrate;
the word line entity layer is positioned on the surface of the word line surface layer and comprises a filling part combined in the word line surface layer and a protruding part positioned on the top of the filling part, the top end of the protruding part is higher than the top end of the word line surface layer and lower than the upper surface of the semiconductor substrate, and a side ditch is formed between the outer side wall of the protruding part and the dielectric layer; and
and the hole filling insulating layer is filled at the upper part of the groove structure, and the bottom of the hole filling insulating layer covers the top end of the word line entity layer and the top end of the side groove to form air cavities positioned at two sides of the protruding part.
As a preferred embodiment of the present invention, the thickness of the word line surface layer is 0.8 to 5 nm to define the width of the air cavity.
As a preferable scheme of the invention, the size of the opening of the groove structure is 10-50 nanometers; the thickness of the dielectric layer is 1-9 nanometers; the height of the air cavity is 1-40 nanometers.
As a preferable mode of the invention, the material of the dielectric layer comprises silicon oxide, the material of the word line surface layer comprises titanium nitride, the material of the word line physical layer comprises tungsten, and the material of the hole filling insulating layer comprises silicon nitride.
The present invention also provides a memory cell array including:
the memory cells comprise a transistor structure according to any one of the schemes, the memory cells are configured into cell rows and cell columns, and each active area of the transistor structure is connected with two capacitors; and
an address line connected to the word line physical layer of each memory cell in the cell row or the cell column, the address line for controlling the memory cell.
The invention also provides a memory structure comprising the memory cell array according to any one of the schemes.
As described above, the transistor structure, the memory cell array and the method for manufacturing the same of the present invention have the following beneficial effects:
according to the invention, a transistor structure is prepared through deposition and wet etching processes, so that a transistor with an insulating side trench (void) is formed, and under the condition that other parts of the device structure are the same, the parts of the insulating side trench are compared, and due to the existence of the insulating side trench, the original conductive layer part is converted into air of the insulating side trench, and the middle dielectric layer of a capacitor is changed, so that parasitic capacitance is reduced; in addition, by adopting the technical scheme of the invention, the height of the metal layer serving as the grid word line can be increased while the small leakage current is ensured, so that the resistance of the transistor is reduced.
Drawings
Fig. 1 shows a flow chart of a transistor structure fabrication process of the present invention.
Fig. 2 is a schematic diagram showing a structure of a semiconductor substrate provided in the fabrication of a transistor structure according to the present invention.
Fig. 3 is a schematic diagram of a mask layer in the transistor structure fabrication according to the present invention.
Fig. 4 is a schematic structural diagram of a trench structure formed in the fabrication of a transistor structure according to the present invention.
Fig. 5 is a schematic diagram of a structure of a dielectric layer formed in the fabrication of a transistor structure according to the present invention.
Fig. 6 is a schematic structural diagram of a first conductive material layer formed in the fabrication of a transistor structure according to the present invention.
Fig. 7 is a schematic structural diagram showing formation of a second conductive material layer in the fabrication of a transistor structure according to the present invention.
Fig. 8 is a schematic diagram illustrating etching of a first second conductive material layer to a first pitch in the fabrication of a transistor structure according to the present invention.
Fig. 9 is a schematic diagram showing the structure of forming a word line surface layer and a word line physical layer in the transistor structure fabrication of the present invention.
Fig. 10 is a schematic diagram showing a structure of a hole-filling insulating layer formed in the fabrication of a transistor structure according to the present invention.
Fig. 11 is a schematic diagram showing a memory cell connection employing the transistor structure of the present invention.
Fig. 12 shows a schematic diagram of a memory structure employing the transistor structure of the present invention.
Fig. 13 shows a ringing phenomenon existing in the structure of the conventional device.
Fig. 14 (a) and 14 (b) are schematic diagrams showing capacitance changes in the transistor structures according to the prior art and the present invention.
Fig. 15 shows a schematic product diagram including a transistor structure of the present invention.
Description of element reference numerals
100. Semiconductor substrate
101. Active region
102. Isolation structure
103. Isolation structure filling layer
104. Mask layer
105. Window
106. Groove structure
107. Dielectric layer
108. A first conductive material layer
109. A second conductive material layer
110. A first conductive material part
111. Second conductive material part
112. Word line surface layer
113. Word line physical layer
1131. Filling part
1132. Raised portion
114. Side ditch
1141. Air cavity
115. Hole filling insulating layer
116. Capacitance device
117. Word line
118. Amplifier
119. Channel region
120. Shallow junction region
121. Doped drain region
S1-S4 steps 1) to 4)
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 15. It should be noted that, the illustrations provided in the present embodiment are merely schematic illustrations of the basic concepts of the present invention, and only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1, the present invention provides a method for manufacturing a transistor structure, including the following steps:
1) Providing a semiconductor substrate with an active region, and forming a groove structure in the active region;
2) Forming a dielectric layer at the bottom and the side wall of the groove structure;
3) Forming a word line surface layer on the bottom and partial side walls of the dielectric layer, and forming a word line entity layer on the surface of the word line surface layer, wherein the word line entity layer comprises a filling part combined with the surface of the word line surface layer and a protruding part positioned on the top of the filling part, the top end of the word line surface layer is lower than the upper surface of the semiconductor substrate, the top end of the protruding part is higher than the top end of the word line surface layer and lower than the upper surface of the semiconductor substrate, and a side ditch is formed between the outer side wall of the protruding part and the dielectric layer; and
4) And forming a hole filling insulating layer in the groove structure, wherein the bottom of the hole filling insulating layer covers the top end of the word line entity layer and the top end of the side groove so as to seal the side groove to form an air cavity.
The method for manufacturing the transistor structure according to the present invention will be described in detail with reference to the accompanying drawings.
As shown in S1 of fig. 1 and fig. 2 to 4, step 1) is performed first, providing a semiconductor substrate 100 having an active region 101, and forming a trench structure 106 in the active region 101;
Specifically, the present embodiment first provides a semiconductor substrate 100 having an active region 101, where the material of the semiconductor substrate 100 includes but is not limited to a monocrystalline or polycrystalline semiconductor material, and in addition, the semiconductor substrate 100 may be an intrinsic monocrystalline silicon substrate or a lightly doped silicon substrate, and further, may be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate, and in this embodiment, the semiconductor substrate 100 is a p+ type polycrystalline silicon material substrate.
Wherein, in this example, the active regions 101 are separated by isolation structures 102, the isolation structures 102 are preferably shallow trench isolation structures, and have isolation structure filling layers 103 therein, and the materials include, but are not limited to, silicon oxide. Next, the trench structure 106 is etched into the active region, as shown in fig. 4, which shows a schematic view of forming two trench structures 106 in the active region 101, and the cross-sectional shape of the trench structure 106 is preferably U-shaped, but may be any shape suitable for device performance, such as rectangular.
As an example, in step 1), the step of forming the trench structure 106 includes:
1-1) as shown in fig. 3, a mask layer 104 with a window 105 is formed on the surface of the semiconductor substrate 100, wherein the window 105 corresponds to the trench structure 106 vertically; and
1-2) as shown in fig. 4, the semiconductor substrate 100 is etched based on the window 105 to form the trench structure 106.
Specifically, the present example provides a process for forming the trench structure 106, and it should be noted that, in the process for preparing the present example, it is preferable to keep the isolation structure filling layer 103 filling the isolation structure 102, that is, there is a layer of isolation structure filling layer, such as a silicon oxide layer, on the surface of the semiconductor substrate 100, as shown in fig. 2, although in other examples, the silicon oxide layer on the surface may be removed, without specific limitation, and then, preparing the trench structure 106, forming the mask layer 104 with the window 105 on the semiconductor substrate 100 by using a photolithography and etching process, where a mask material layer is first formed on the semiconductor substrate 100, and etching the mask material layer with the window 105 using photoresist with an opening as a mask, forming the mask layer 104 with the window 105, and continuing etching the semiconductor substrate to form the trench structure 106.
As shown in S2 in fig. 1 and fig. 5, step 2) is performed to form a dielectric layer 107 on the bottom and the sidewalls of the trench structure 106;
As an example, in step 2), an in situ vapor (ISSG) process is used to form the dielectric layer 107 at the bottom and the sidewalls of the trench structure 106.
Specifically, the material of the dielectric layer 107 may be, but is not limited to, silicon oxide, silicon nitride, silicon oxide or silicon dioxide, and the resistivity of the material is preferably 2×10 11 ～1×10 25 Omega m, of course, may be other material dielectric layers, and the material of the dielectric layer 107 in this example is selected to be silicon oxide. The dielectric layer 107 may be formed by an atomic deposition process (Atomic Layer Deposition) or a plasma vapor deposition (Chemical Vapor Deposition) film or a rapid thermal oxidation (Rapid Thermal Oxidation), preferably, the dielectric layer 107 is prepared by an in-situ vapor (in-situ stream generation, ISSG) process, and a large amount of vapor-phase active radicals are generated during the preparation and participate in the oxidation of the silicon wafer, so that a film with fewer defects may be obtained, and since the insulating side trench 114 exposes a portion of the surface of the dielectric layer in this embodiment, good device performance may be obtained.
As shown in S3 in fig. 1 and fig. 6 to 9, step 3) is performed, a word line surface layer 112 is formed on the bottom and a partial sidewall of the dielectric layer 107, and a word line physical layer 113 is formed on the surface of the word line surface layer 112, wherein the word line physical layer 113 includes a filling portion 1131 bonded to the surface of the word line surface layer 112 and a protruding portion 1132 located on top of the filling portion 1131, wherein the top of the word line surface layer 112 is lower than the upper surface of the semiconductor substrate 100, the top of the protruding portion 1132 is higher than the top of the word line surface layer 112 and lower than the upper surface of the semiconductor substrate 100, and a side trench 114 is formed between the outer sidewall of the protruding portion 1132 and the dielectric layer 107;
Specifically, through the process of this step, two conductive layers are formed in the trench structure 106, the material of the word line surface layer 112 includes but is not limited to titanium nitride, the material of the word line physical layer 113 includes but is not limited to tungsten metal, and a side trench 114 is formed between the word line physical layer 113 and the dielectric layer 107, further, the thickness of the word line surface layer 112 is used to define the width of the air cavity, and the thickness of the word line surface layer 112 ranges from 0.8 nm to 5 nm.
As an example, in step 3), the method further comprises the steps of: an adhesion layer is formed between the word line surface layer 112 and the word line physical layer 113.
In particular, the material of the adhesion layer may be selected to be silane (SiH 4 ) And tetrachlorosilane (SiCl) 4 ) Of course, the two layers may be stacked, so that a good interface is formed between the word line surface layer (such as TiN) and the word line physical layer (such as W), and the word line physical layer is filled with the voids in the word line surface layer.
As an example, in step 3), the step of forming the word line surface layer 112 and the word line physical layer 113 includes:
3-1) forming a first conductive material layer 108 on the bottom, the sidewalls, and the surface of the semiconductor substrate 100 surrounding the trench structure 106 of the trench structure 106;
3-2) forming a second conductive material layer 109 on the surface of the first conductive material layer 108, wherein the second conductive material layer 109 fills the trench structure 106 and extends to cover the first conductive material layer on the surface of the semiconductor substrate;
3-3) etching the first conductive material layer 108 and the second conductive material layer 109 to form a first conductive material portion 110 and a second conductive material portion 111, respectively, wherein a first pitch Z1 is provided from a top end of the first conductive material portion 110 to an upper surface of the semiconductor substrate 100 and a top end of the second conductive material portion 111 to the upper surface of the semiconductor substrate 100; and
3-4) continuing to etch the first conductive material layer 108 and the second conductive material layer 109 by a wet etching process to form the word line surface layer 112 and the word line body layer 113, respectively, wherein a second pitch Z2 is formed from a top end of the word line surface layer 112 to an upper surface of the semiconductor substrate 100, and a third pitch Z3 is formed from a top end of the word line body layer 113 to an upper surface of the semiconductor substrate 100, and the second pitch Z2 is greater than the third pitch Z3 to define a height of the protrusion 1132.
As an example, the first pitch Z1 is between 30 and 70 nanometers; the difference between the second interval Z2 and the third interval Z3 is 1-40 nanometers.
As an example, in step 3-3), the first conductive material layer 108 and the second conductive material layer 109 are etched by an alternating etching process, wherein the etching gas used for the alternating etching includes sulfur hexafluoride, chlorine and argon (SF) 6 ) Chlorine (Cl) 2 ) And argon (Ar) and any two or three of the group consisting of argon (Ar).
Specifically, the present example provides a process for preparing the word line surface layer 112 and the word line physical layer 113, where the process is performed while the isolation structure filling layer 103 and the mask layer 104 mentioned in the example of the present invention are maintained, first, a first conductive material layer 108 is formed, as shown in fig. 6, and a second conductive material layer 109 is covered thereon, as shown in fig. 7, where the preparation of the first conductive material layer 108 and the second conductive material layer 109 includes, but is not limited to, a deposition process such as electroplating, chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and in this example, a Chemical Vapor Deposition (CVD) process is selected.
Next, a process of planarizing the two material layers on the surface of the semiconductor substrate 100 by Chemical mechanical planarization (Chemical-Mechanical Planarization, CMP) is also included. Then, the two material layers are etched once by using an alternative etching process, as shown in fig. 8, as a result of which the first conductive material layer 108 is changed into a first conductive material portion 110, the second conductive material layer 109 is changed into a second conductive material portion 111, of course, the first conductive material portion 110 and the second conductive material portion 111 may have different distances from the surface of the semiconductor substrate 100, a desired structure is formed by a subsequent process, in this example, preferably, the first conductive material portion 110 and the second conductive material portion 111 have the same distance Z1 from the surface of the semiconductor substrate 100, so as to facilitate the control of the subsequent process, the etching in this step is preferably dry etching, and gases having different etching rates for the first conductive material layer and the second conductive material layer are alternately introduced,taking the first conductive material layer as titanium nitride, the second conductive material layer as tungsten metal as an example, and SF as etching gas 6 /Cl 2 Etching is performed by adjusting the flow ratio or the individual etching time.
Finally, as shown in fig. 9, the etching rates of the two materials are controlled by an etching process, so as to finally obtain a word line surface layer 112 and a word line entity layer 113, and an insulating side trench 114 is formed between the word line entity layer 113 and the dielectric layer 107, wherein the surface of the word line surface layer 112 and the surface of the semiconductor substrate 100 have a second spacing Z2, the surface of the word line entity layer 113 and the surface of the semiconductor substrate 100 have a third spacing Z3, the difference between Z3 and Z2 is the height of the protruding portion 1132, that is, the length of the insulating side trench 114, and the thickness of the word line surface layer 112 is the width of the insulating side trench 114.
As an example, in step 3-4), the reagent for performing the wet etching includes a mixed solution of ammonia water, hydrogen peroxide and water, wherein the ammonia water (NH 4 OH), hydrogen peroxide (H) 2 O 2 ) And water (H) 2 The proportion of O) is sequentially 1 to 0.01 to 2 and 5 to 150; the wet etching is performed at a temperature ranging from 4 to 25 ℃.
Specifically, in this example, a process for forming a word line surface layer and a word line physical layer by wet etching is provided, in which APM reagent is used for wet etching, and the reagent includes ammonia (NH 4 OH), hydrogen peroxide (H) 2 O 2 ) And water (H) 2 O), adjusting the concentration range and temperature range of APM, increasing the etching rate of the first conductive material layer (such as TiN), and decreasing the etching rate of the second conductive material layer (such as W), thereby obtaining a desired structure, preferably, ammonia (NH 4 OH), hydrogen peroxide (H) 2 O 2 ) And water (H) 2 The ratio of O) comprises 1 (0.1-1.5) (20-100), and the ratio is 1:1:50 in the example; the wet etching is preferably performed at a temperature of 10 to 20 ℃, and in this example, 15 ℃.
As an example, before step 4), the method further comprises the steps of: the surface of the word line physical layer 113 is cleaned with a diluted hydrofluoric acid (DHF) agent including a mixed solution of hydrofluoric acid and water in a ratio of 1 (50-1000) to remove surface byproducts.
In particular, DHF agents are used to remove oxide layers formed during operation by oxidation, such as WO formed, thereby reducing the resistance of the word line structure. Preferably, the ratio of hydrofluoric acid (HF) to water in the mixed solution comprises 1 (100-500), and the ratio of the selected cuttlefish in the example is 1:300.
As shown in S4 in fig. 1 and fig. 10, step 4) is performed to form a hole filling insulating layer 115 in the trench structure 106, wherein the bottom of the hole filling insulating layer 115 covers the top end of the word line physical layer 113 and the top end of the side trench 114, so as to seal the side trench 114 to form an air cavity 1141;
as an example, in step 4), the hole-filling insulating layer 115 is formed by an atomic layer deposition process so as not to damage the insulating side trench 114.
As an example, the deposition rate of the atomic layer deposition process is between 200 and 1000 nm/min.
Specifically, step 4) is finally performed to form the hole-filling insulating layer 115, as shown in fig. 10, and the hole-filling insulating layer 115 is controlled not to be deposited in the insulating side trench 114, so as to ensure the integrity of the insulating side trench 114, and the hole-filling insulating layer 115 may be formed by CVD or ALD to fill GAP (in the upper portion of the trench structure), wherein the deposition rate is controlled to be 200-1000 nm/min, preferably 220-500 nm/min, and in this example, 250nm/min, and the material of the hole-filling insulating layer 115 includes, but is not limited to, silicon nitride.
It should be noted that, through this step, the side trench 114 is closed, so that an air cavity (void) 1141 is formed in the device structure, and in the case where other portions of the device structure are the same, the portions of the air cavity (void) are compared, and due to the presence of the air cavity 1141, the portion of the original conductive layer (which corresponds to the word line surface layer portion in this example) is converted into air of the air cavity, and the intermediate dielectric layer of the capacitance is changed, so that the parasitic capacitance is reduced, and an example is given in fig. 14, in which fig. 14 (a) shows the capacitance change in the device, and fig. 14 (b) shows the capacitance in the device structure of the present invention.
In addition, it should be noted that, with the technical solution of the present invention, since the word line surface layer 112 is directly formed on the surface of the dielectric layer 107, the word line surface layer 112 is used as a functional structure layer (work function) to determine the threshold voltage Vt of the device structure, and meanwhile, the word line physical layer 113 formed inside the word line surface layer 112 has a current conducting function, and since it may include the protruding portion 1132 protruding from the word line surface layer 112, the height thereof may be more flexibly selected, so that the resistance in the transistor may be reduced, the resistance of the transistor may be reduced while ensuring a small leakage current, and in addition, the word line surface layer 112 may also be used as a diffusion barrier layer of the word line physical layer 113. The dual conductive layer structure 111 serves as both a gate and a word line, and the embedded gate word line can save device space, reduce device size, and increase device speed.
As an example, in step 1), the opening of the trench structure 106 has a size of 10-50 nm; in step 2), the thickness of the dielectric layer 107 is 1-9 nm; in step 3), the width of the air chamber 1141 is between 0.8 and 5 nm, and the height of the air chamber 1141 is between 1 and 40 nm.
Specifically, in this example, the opening of the trench structure 106 is preferably 20 to 40 nm, where the opening size refers to the width of the opening in the cross-sectional pattern, as shown by D in fig. 4, and is selected to be 30 nm in this example; the thickness of the dielectric layer 107 is preferably 2-8 nm, in this example 6 nm; the width of the air chamber 1141 (the thickness of the word line surface layer 112) is preferably 1 to 4 nm, in this example 2 nm, and the height of the air chamber 1141 (the height of the protruding portion) is preferably 10 to 30 nm, in this example 20 nm.
It should be further noted that, due to the parasitic capacitance in the device, these undesirable capacitances come from various aspects in the system, such as the PCB material, thickness, board layer structure, and trace parallelism, which affect the parasitic capacitance of the PCB board, and also the parasitic capacitance of the device itself, and most likely, these things are also affected by the ambient temperature. In a high-speed circuit, the influence of parasitic capacitance cannot be ignored due to higher and higher frequency, as shown in fig. 12, a ringing phenomenon exists in a device, and the structure obtained by adopting the preparation process of the invention can effectively improve the ringing phenomenon.
The invention also provides a preparation method of the memory cell array, which comprises the following steps:
a) Forming a plurality of memory cells with transistor structures, wherein each memory cell is configured into a cell row and a cell column, the transistor structures are prepared by adopting any one of the transistor structure preparation schemes in the embodiment, and each active area of the transistor structures is respectively connected with two capacitors; and
b) And connecting an address line to the word line physical layer of each memory cell in the cell row or the cell column to prepare a memory cell array, wherein the address line is used for controlling the memory cells.
In addition, as shown in fig. 11, the present invention also provides a method for manufacturing a memory cell by using the transistor structure manufacturing process disclosed in the present invention, wherein the word line surface layer 112 and the word line entity layer 113 are used together as a gate word line structure, and are connected with the word line 117 driver, the source region is connected with the capacitor 116, the drain region is connected with the amplifier 118, and a connection mode of the memory array is shown in fig. 12, specifically, during the data reading process, data is output to a pad (pad) through the capacitor and is exported, and during the data writing process, data is stored in the capacitor through the pad.
In addition, as shown in fig. 15, the present invention further provides a method for preparing a product including the transistor structure provided in this embodiment and the product prepared by the method, where the method for preparing a product includes a step of preparing a transistor provided in this embodiment, and further includes a step of preparing a channel region 119, a shallow junction region 120, and a doped drain region 121, where B (boron) doping is performed in the active region 101 to prepare the channel region 119, as (arsenic) doping is performed in the active region 101 to prepare the shallow junction region 120, and P (phosphorus) doping is performed in the active region 101 to prepare the doped drain region 121.
The present invention also provides a transistor structure, where the transistor structure is preferably prepared by using the method for preparing a transistor structure provided in this embodiment, but not limited to this method, as shown in fig. 10, the transistor structure includes:
a semiconductor substrate 100 having an active region 101;
a trench structure 106 located within the active region 101 of the semiconductor substrate 100;
a dielectric layer 107 located at the bottom and the sidewalls of the trench structure 106;
a word line surface layer 112 located at the bottom and partial side walls of the dielectric layer 107, wherein the top of the word line surface layer 112 is lower than the upper surface of the semiconductor substrate 100;
A word line physical layer 113, located on the surface of the word line surface layer 112, and including a filling portion 1131 combined with the surface of the word line surface layer 112 and a protruding portion 1132 located on top of the filling portion 1131, wherein the top end of the protruding portion 1132 is higher than the top end of the word line surface layer 112 and lower than the upper surface of the semiconductor substrate 100, and a side trench 114 is formed between the outer side wall of the protruding portion 1132 and the dielectric layer 107; and
and a hole filling insulating layer 115 filled in the upper portion of the trench structure 106, wherein the bottom of the hole filling insulating layer 115 covers the top end of the word line physical layer 113 and the top end of the side trench 114 to form air cavities 1141 located at two sides of the protruding portion 1132.
As an example, the thickness of the word line surface layer is between 0.8 and 5 nanometers to define the width of the air chamber 1141.
As an example, the material of the dielectric layer 107 includes silicon oxide, the material of the word line surface layer 112 includes titanium nitride, the material of the word line body layer 113 includes tungsten, and the material of the via filling insulating layer 115 includes silicon nitride.
Specifically, in this example, the active regions 101 are separated by isolation structures 102, and the isolation structures 102 are preferably shallow trench isolation structures having an isolation structure filling layer 103 therein, and the material includes, but is not limited to, silicon oxide. The material of the dielectric layer 107 may be, but is not limited to, silicon oxide, silicon nitride, and the silicon oxide may be silicon monoxide or silicon dioxide.
Note that the material of the word line surface layer 112 includes, but is not limited to, titanium nitride, the material of the word line physical layer 113 includes, but is not limited to, tungsten metal, and an air cavity (void) 1141 is formed between the word line physical layer 113 and the dielectric layer 107, so that, in the case that other parts of the device structure are the same, the air cavity 1141 is compared, and the original conductive layer (e.g., the word line surface layer in this example) is partially converted into air of the air cavity, so that the intermediate dielectric layer of the capacitor is changed, and the parasitic capacitance is reduced.
In addition, since the word line surface layer 112 is directly formed on the surface of the dielectric layer 107, the word line surface layer 112 is used as a functional structure layer (work function) to determine the threshold voltage Vt of the device structure, and the word line entity layer 113 formed inside the word line surface layer 112 has a current conducting function, and since it may include the protruding portion 1132 protruding from the word line surface layer 112, the height thereof may be more flexibly selected, so that the resistance in the transistor may be reduced, the resistance of the transistor may be reduced while ensuring a small leakage current, and in addition, the word line surface layer 112 may also be used as a diffusion barrier layer of the word line entity layer 113. The dual conductive layer structure 111 serves as both a gate and a word line, and the embedded gate word line can save device space, reduce device size, and increase device speed.
As an example, an adhesion layer is further formed between the word line surface layer 112 and the word line physical layer 113. The material of the adhesion layer may be selected to be silane (SiH 4 ) And tetrachlorosilane (SiCl) 4 ) Of course, it is also possible to laminate the two layers so that a good interface is formed between the word line surface layer (such as TiN) and the word line physical layer (such as W) to allow the two layers to be laminatedThe word line physical layer is filled with voids in the word line surface layer.
As an example, the opening of the trench structure has a size of 10-50 nm; the thickness of the dielectric layer is 1-9 nanometers; the width of the air cavity is between 0.8 and 5 nanometers, and the height of the air cavity is between 1 and 40 nanometers.
Specifically, in this example, the opening of the trench structure 106 is preferably 20 to 40 nm, where the opening size refers to the width of the opening in the cross-sectional pattern, as shown by D in fig. 4, and is selected to be 30 nm in this example; the thickness of the dielectric layer 107 is preferably 2-8 nm, in this example 6 nm; the width of the air cavity 114 (the thickness of the word line surface layer 112) is preferably 1 to 4 nm, in this example 2 nm, and the height of the air cavity 114 (the height of the protruding portion) is preferably 10 to 30 nm, in this example 20 nm.
The present invention also provides a memory cell array including:
the memory cell comprises a transistor structure according to any one of the schemes in the embodiment, and each memory cell is configured into a cell row and a cell column, and each active region of the transistor structure is connected with two capacitors; and
an address line connected to the word line physical layer of each memory cell in the cell row or the cell column, the address line for controlling the memory cell.
The invention also provides a memory structure comprising the memory cell array according to any one of the schemes in the embodiment.
Further, the memory structure further comprises a plurality of shallow trench isolation structures, wherein an active region is arranged between every two adjacent shallow trench isolation structures, and two transistor structures which are distributed at intervals are arranged.
In summary, the present invention provides a transistor structure, a memory cell array and a method for manufacturing the same, wherein the transistor manufacturing method includes: providing a semiconductor substrate with an active region, and forming a groove structure in the active region; forming a dielectric layer at the bottom and the side wall of the groove structure; forming a word line surface layer on the bottom and partial side walls of the dielectric layer, and forming a word line entity layer on the surface of the word line surface layer, wherein the word line entity layer comprises a filling part combined on the surface of the word line surface layer and a protruding part positioned on the top of the filling part, the top end of the word line surface layer is lower than the upper surface of the semiconductor substrate, the top end of the protruding part is higher than the top end of the word line surface layer and lower than the upper surface of the semiconductor substrate, and a side ditch is formed between the outer side wall of the protruding part and the dielectric layer; and forming a hole filling insulating layer in the groove structure, wherein the bottom of the hole filling insulating layer covers the top end of the word line entity layer and the top end of the side groove so as to seal the side groove to form an air cavity. Through the scheme, the transistor structure is prepared through the deposition and wet etching processes, and the transistor with the air cavity (void) is formed, so that under the condition that other parts of the device structure are the same, the parts of the air cavity are compared, and due to the existence of the air cavity, the original part of the conductive layer is converted into the air of the air cavity, and the middle dielectric layer of the capacitor is changed, so that the parasitic capacitance is reduced; in addition, by adopting the technical scheme of the invention, the height of the metal layer serving as the grid word line can be increased while the small leakage current is ensured, so that the resistance of the transistor is reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (21)
1. A method of fabricating a transistor structure, comprising the steps of:
1) Providing a semiconductor substrate with an active region, forming a groove structure in the active region, wherein a channel region, a shallow junction region and a doped drain region are formed in the active region, the bottom of the groove structure is positioned in the channel region, the doped drain region is positioned on the upper surface of the channel region between two groove structures, the shallow junction region is positioned on the upper surface of the channel region at one side of the groove structure far away from the doped drain region, and the upper surface is flush with the upper surface of the semiconductor substrate;
2) Forming a dielectric layer at the bottom and the side wall of the groove structure;
3) Forming a word line surface layer on the bottom and partial side walls of the dielectric layer, and forming a word line entity layer on the surface of the word line surface layer, wherein the word line entity layer comprises a filling part combined on the surface of the word line surface layer and a protruding part positioned on the top of the filling part, the top end of the word line surface layer is lower than the upper surface of the semiconductor substrate, the top end of the protruding part is higher than the top end of the word line surface layer and lower than the upper surface of the semiconductor substrate, and a side ditch is formed between the outer side wall of the protruding part and the dielectric layer; and
4) And forming a hole filling insulating layer in the groove structure, wherein the bottom of the hole filling insulating layer covers the top end of the word line entity layer and the top end of the side groove so as to seal the side groove to form an air cavity, and the upper surface of the doped drain region is flush with the upper surface of the air cavity.
2. The method of claim 1, wherein the thickness of the word line surface layer is between 0.8 and 5 nanometers to define the width of the air cavity.
3. The method of fabricating a transistor structure according to claim 2, wherein in step 1), the opening of the trench structure has a size of 10-50 nm; in the step 2), the thickness of the dielectric layer is 1-9 nanometers; in the step 4), the height of the air cavity is 1-40 nanometers.
4. The method of manufacturing a transistor structure according to claim 1, wherein in step 1), the step of forming the trench structure comprises:
1-1) forming a mask layer with a window on the surface of the semiconductor substrate, wherein the window corresponds to the groove structure vertically; and
1-2) etching the semiconductor substrate based on the window to form the groove structure.
5. The method of claim 1, wherein in step 2), the dielectric layer is formed using an In Situ Steam (ISSG) process.
6. The method of manufacturing a transistor structure according to claim 1, further comprising the step of, in step 3): an adhesion layer is formed between the word line surface layer and the word line physical layer.
7. The method of manufacturing a transistor structure according to claim 1, wherein in step 3), the step of forming the word line surface layer and the word line physical layer includes:
3-1) forming a first conductive material layer on the bottom, the side wall and the surface of the semiconductor substrate around the trench structure;
3-2) forming a second conductive material layer on the surface of the first conductive material layer, wherein the second conductive material layer fills the groove structure and extends to cover the first conductive material layer on the surface of the semiconductor substrate;
3-3) etching the first conductive material layer and the second conductive material layer to form a first conductive material portion and a second conductive material portion respectively, wherein a first interval is formed from the top end of the first conductive material portion to the upper surface of the semiconductor substrate and from the top end of the second conductive material portion to the upper surface of the semiconductor substrate; and
3-4) continuing to etch the first conductive material layer and the second conductive material layer through a wet etching process to form the word line surface layer and the word line entity layer respectively, wherein a second interval is formed from the top end of the word line surface layer to the upper surface of the semiconductor substrate, a third interval is formed from the top end of the word line entity layer to the upper surface of the semiconductor substrate, and the second interval is larger than the third interval so as to define the height of the protruding portion.
8. The method of fabricating a transistor structure according to claim 7, wherein the first pitch is between 30 and 70 nanometers; the difference between the second spacing and the third spacing is 1-40 nanometers.
9. The method of manufacturing a transistor structure according to claim 7, wherein in step 3-4), the reagent for performing the wet etching includes ammonia (NH) 4 OH), hydrogen peroxide (H) 2 O 2 ) And water, wherein the proportion of the ammonia water, the hydrogen peroxide and the water in the mixed solution is sequentially 1 to 0.01 to 2 to 5 to 150.
10. The method of manufacturing a transistor structure according to claim 7, wherein in step 3-3), the first conductive material layer and the second conductive material layer are etched by an alternating etching process, wherein the etching gas used for the alternating etching includes any two or three of sulfur hexafluoride (SF 6), chlorine (Cl 2) and argon (Ar).
11. The method of manufacturing a transistor structure according to claim 1, further comprising, prior to step 4), the steps of: and cleaning the surface of the word line entity layer by adopting a diluted hydrofluoric acid (DHF) reagent to remove surface byproducts, wherein the diluted hydrofluoric acid reagent comprises a mixed solution of hydrofluoric acid (HF) and water, and the ratio of the hydrofluoric acid (HF) to the water is 1 to 50-1000.
12. The method of fabricating a transistor structure according to claim 1, wherein in step 2), the material of the dielectric layer comprises silicon oxide; in step 3), the material of the word line surface layer comprises titanium nitride, and the material of the word line physical layer comprises tungsten; in step 4), the material of the hole filling insulating layer comprises silicon nitride.
13. The method of any one of claims 1 to 12, wherein in step 4), the hole-filling insulating layer is formed by an atomic layer deposition process so as not to damage the air cavity.
14. The method of claim 13, wherein the atomic layer deposition process has a deposition rate of 200-1000 nm/min.
15. A method of manufacturing a memory cell array, comprising the steps of:
a) Forming a plurality of memory cells with transistor structures, wherein each memory cell is configured into a cell row and a cell column, the transistor structures are prepared by the preparation method as claimed in claim 1, and each active area of the transistor structures is respectively connected with two capacitors; and
b) And connecting an address line to the word line physical layer of each memory cell in the cell row or the cell column to prepare a memory cell array, wherein the address line is used for controlling the memory cells.
16. A transistor structure, comprising:
a semiconductor substrate having an active region in which a channel region, a shallow junction region, and a doped drain region are formed;
a trench structure located in the active region of the semiconductor substrate, wherein the bottom of the trench structure is located in the channel region, the doped drain region is located on the upper surface of the channel region between the two trench structures, and the shallow junction region is located on the upper surface of the channel region on the side of the trench structure away from the doped drain region and the upper surface is flush with the upper surface of the semiconductor substrate;
the dielectric layer is positioned at the bottom and the side wall of the groove structure;
A word line surface layer positioned at the bottom and partial side wall of the dielectric layer, wherein the top end of the word line surface layer is lower than the upper surface of the semiconductor substrate;
the word line entity layer is positioned on the surface of the word line surface layer and comprises a filling part combined in the word line surface layer and a protruding part positioned on the top of the filling part, the top end of the protruding part is higher than the top end of the word line surface layer and lower than the upper surface of the semiconductor substrate, and a side ditch is formed between the outer side wall of the protruding part and the dielectric layer; and
and the hole filling insulating layer is filled at the upper part of the groove structure, the bottom of the hole filling insulating layer covers the top end of the word line entity layer and the top end of the side groove to form an air cavity positioned at two sides of the protruding part, and the upper surface of the doped drain region is flush with the upper surface of the air cavity.
17. The transistor structure of claim 16, wherein a thickness of the word line surface layer is between 0.8 and 5 nanometers to define a width of the air cavity.
18. The transistor structure of claim 17, wherein the opening of the trench structure has a size of 10-50 nanometers; the thickness of the dielectric layer is 1-9 nanometers; the height of the air cavity is 1-40 nanometers.
19. The transistor structure of claim 16, wherein a material of the dielectric layer comprises silicon oxide, a material of the word line surface layer comprises titanium nitride, a material of the word line body layer comprises tungsten, and a material of the via fill insulating layer comprises silicon nitride.
20. A memory cell array, comprising:
a plurality of memory cells, the memory cells comprising the transistor structure of claim 16, and each of the memory cells being configured in a cell row and a cell column, each active region of the transistor structure being connected to two capacitors; and
an address line connected to the word line physical layer of each memory cell in the cell row or the cell column, the address line for controlling the memory cell.
21. A memory structure comprising the memory cell array of claim 20.
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| CN114093942B (en) * | 2020-07-30 | 2024-05-28 | 中国科学院微电子研究所 | Semiconductor structure, manufacturing method thereof and DRAM |
| EP4195273A4 (en) | 2020-08-24 | 2024-01-31 | Changxin Memory Technologies, Inc. | Semiconductor structure and manufacturing method therefor |
| CN114093818B (en) * | 2020-08-24 | 2024-10-25 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| US12041764B2 (en) | 2020-09-16 | 2024-07-16 | Changxin Memory Technologies, Inc. | Method for manufacturing buried word line transistor, transistor and memory |
| CN114267641B (en) * | 2020-09-16 | 2024-08-02 | 长鑫存储技术有限公司 | Manufacturing method of embedded word line transistor, transistor and memory |
| CN116867268B (en) * | 2021-07-08 | 2024-07-26 | 长鑫存储技术有限公司 | Semiconductor device structure and preparation method |
| CN113707612B (en) * | 2021-07-19 | 2023-10-20 | 长鑫存储技术有限公司 | Memory device and method of forming the same |
| CN113644032B (en) * | 2021-08-11 | 2023-10-10 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
| CN113871353B (en) * | 2021-09-26 | 2024-10-15 | 长鑫存储技术有限公司 | Method for preparing semiconductor structure and semiconductor structure |
| CN117529084A (en) * | 2022-07-28 | 2024-02-06 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and semiconductor structure |
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