CN107993202B - Method for realizing median filtering by using FPGA (field programmable Gate array) - Google Patents
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Abstract
The invention uses FPGA to realize the method of median filtering, 3 lines of images are cached by using asynchronous FIFO, then a sorter is used to filter one line of images, and the filtered image data is temporarily stored back to the original FIFO; after the whole line of image is processed, the FIFO holds a line of filtered image, and at this time, the line of image data is taken out of the FIFO and put into the buffer, and the FIFO continues to receive a new line of image. The invention can process image data and receive new image data while putting the processed image data into the buffer memory in the process of processing the image data.
Description
Technical Field
The invention belongs to the technical field of image processing, and particularly relates to a method for realizing median filtering through an FPGA (field programmable gate array), which can process image data and receive new image data while putting the processed image data into a cache in the process of processing the image data.
Background
The FPGA has the advantage of parallel processing due to the characteristic of a hardware structure, the defects that a single-core CPU executes instructions in series one by one or a multi-core CPU is low in parallelism degree are overcome, image processing is developed into a parallel processing structure from a basic serial structure in the hardware structure, and more image processing items select the FPGA as the core of a hardware acceleration solution.
The median filtering is a nonlinear smooth filtering technology, and can overcome the problem of blurring of image details caused by linear filtering under certain conditions, particularly for images polluted by salt and pepper noise. The median filtering algorithm is briefly described as: and scanning pixel points in the image one by one, sequencing pixel values of all elements in the neighborhood from small to large, assigning the obtained intermediate value to the pixel point corresponding to the current point in the target image, and repeating the steps until all the pixel points of the source image are processed.
Because the median filtering algorithm is not easy to be realized by adopting a pipeline technology like the algorithms such as mean filtering, and the like, even when the median filtering algorithm is realized by using the FPGA at some time, a whole image is cached and then processed, and the processing advantages of the FPGA are greatly limited.
Therefore, the method for realizing the median filtering through the FPGA is obtained, and a new improved solution is provided for the algorithm for realizing the median filtering through the FPGA aiming at the problem that the pipeline technology is not convenient to realize the median filtering or a large time overhead is caused by caching a whole image and then processing the image.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a method for realizing median filtering through an FPGA (field programmable gate array), which can process image data and receive new image data while putting the processed image data into a cache in the process of processing the image data.
In order to achieve the purpose, the invention adopts the following technical scheme:
the invention provides a method for realizing median filtering by using an FPGA (field programmable gate array), which comprises the following steps of:
(1) caching m lines of image data through m asynchronous FIFO memories;
(2) each asynchronous FIFO memory reads out m image data respectively, and the total number of the image data is m2Sending the image data to a sorting machine;
(3) forming m × m pixel matrix in sorter for m2Sorting the image data and calculating a median;
(4) replacing image data in the middle of a pixel matrix in the sorting machine with a median;
(5) respectively storing the m image data of the leftmost column of the pixel matrix in the sorting machine back to the corresponding asynchronous FIFO memories;
(6) reading out 1 image data from each asynchronous FIFO memory, and sending m image data into a sequencer;
(7) the m × m pixel matrix is formed again in the sorter for m2Sorting the image data and obtaining a median value;
(8) replacing image data in the middle of a pixel matrix in the sorting machine with a median;
(9) step (10) is carried out after all the image data in the m asynchronous FIFO memories are traversed in the circulating steps (5) - (8), and at the moment, the m multiplied by m window of the median filter is already swept by one line of image data;
(10) according to the sequence of the arrangement of the pixel lines of the original image, the asynchronous FIFO memory storing the pixels of the upper line stores the image data in the asynchronous FIFO memory into a buffer memory, and stores the unprocessed pixels of the next line of the original image into the asynchronous FIFO memory;
(11) after the step (10), each asynchronous FIFO memory stores one line of image data again, namely each asynchronous FIFO memory caches m lines of image data again, the steps (1) to (10) are circulated, and all pixel lines of the original image are traversed;
(12) the whole image stored in the buffer is the image subjected to the median filtering processing.
The value of m is odd.
The value of m is 3.
In step (10), the asynchronous FIFO memory storing the pixels in the upper row stores the image data therein into a buffer memory according to the sequence of the arrangement of the pixel rows of the original image, and the buffer memory includes: RAM, SRAM, DDR memory.
In the step (12), the whole image stored in the cache is the image after median filtering, and the cache includes a RAM, an SRAM, and a DDR memory.
The invention has the beneficial effects that: the invention can process image data and receive new image data while putting the processed image data into the cache in the process of using the FPGA to perform median filtering on the image; the method overcomes the problem that the whole image data link is seriously jammed at a certain moment due to the fact that the whole image is sometimes even required to be cached and then processed because the algorithm is not easy to realize by using a pipeline technology.
Drawings
FIG. 1 is a schematic diagram of an image pixel matrix.
Fig. 2 is a flow chart of a method of implementing median filtering using an FPGA.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention.
The present invention is further illustrated by the following examples.
Referring to fig. 1 and 2, assuming an image size of M × N, the first pixel in the first row is labeled [1,1], and the nth pixel in the mth row is labeled [ M, N ]. The image pixel matrix is illustrated in fig. 1.
(1) The image data is transmitted from one line to one line, the embodiment of the present invention uses 3 asynchronous FIFO memories as clock domain transition, each asynchronous FIFO memory buffers one line of image data, so 3 lines of image data are buffered in total, and the image data buffered by each asynchronous FIFO memory is shown in table 1:
| FIFO#1 | [B，1] | [B，2] | [B，3] | [B，4] | …… | [B，N] |
| FIFO#2 | [C，1] | [C，2] | [C，3] | [C，4] | …… | [C，N] |
| FIFO#3 | [D，1] | [D，2] | [D，3] | [D，4] | …… | [D，N] |
TABLE 1
(2) Each asynchronous FIFO memory reads 3 pieces of image data, and 9 pieces of image data in total are sent to the sorter, where the image data in the sorter is shown in table 2, and the image data stored in the FIFO is shown in table 3:
| [B，1] | [B，2] | [B，3] |
| [C，1] | [C，2] | [C，3] |
| [D，1] | [D，2] | [D，3] |
TABLE 2
| FIFO#1 | [B，4] | …… | [B，N] | |||
| FIFO#2 | [C，4] | …… | [C，N] | |||
| FIFO#3 | [D，4] | …… | [D，N] |
TABLE 3
(3) Forming a 3 multiplied by 3 pixel matrix in the sorter, sorting 9 image data and obtaining a median mid _ 1;
(4) replacing image data in the middle of a pixel matrix in the sorting machine with a median;
(5) the sorter stores 3 image data in the leftmost column of the 3 × 3 pixel matrix therein back to the corresponding asynchronous FIFO memories, respectively, where the image data in the asynchronous FIFO memories are as shown in table 4:
| FIFO#1 | [B，4] | …… | [B，N] | [B，1] |
| FIFO#2 | [C，4] | …… | [C，N] | [C，1] |
| FIFO#3 | [D，4] | …… | [D，N] | [D，1] |
TABLE 4
(6) Reading out 1 image data from each asynchronous FIFO memory, and feeding 3 image data into the sorter, wherein the pixel matrix in the sorter is shown in table 5, and the image data in the asynchronous FIFO memory is shown in table 6:
| [B，2] | [B，3] | [B，4] |
| [mid_1] | [C，3] | [C，4] |
| [D，2] | [D，3] | [D，4] |
TABLE 5
| FIFO#1 | [B，5] | …… | [B，N] | [B，1] |
| FIFO#2 | [C，5] | …… | [C，N] | [C，1] |
| FIFO#3 | [D，5] | …… | [D，N] | [D，1] |
TABLE 6
(7) Forming a 3 x 3 pixel matrix in the sorter again, sorting the 9 image data and obtaining a median;
(8) replacing image data in the middle of a pixel matrix in the sorting machine with a median;
(9) the loop of steps (5) - (8) is followed by step (10) after traversing all image data in 3 asynchronous FIFO memories, meaning that the 3 × 3 window of median filtering has swept through one line of image data, when the image data in the asynchronous FIFO memories is as in table 7:
| FIFO#1 | [B，1] | [B，2] | [B，3] | …… | [B，N-1] | [B，N] |
| FIFO#2 | [C，1] | [mid_1] | [mid_2] | …… | [mid_n-2] | [C，N] |
| FIFO#3 | [D，1] | [D2] | [D，3] | …… | [D，N-1] | [D，N] |
TABLE 7
(10) The original image is formed by arranging pixels in a line from top to bottom, according to the sequence of the arrangement of the pixel lines of the original image, an asynchronous FIFO memory which stores the pixels in the upper line stores the image data in the asynchronous FIFO memory, the cache can be a RAM, an SRAM, a DDR and other memories, and stores the unprocessed pixels in the next line of the original image into the asynchronous FIFO memory. The image data in the asynchronous FIFO memory at this time is as shown in table 8:
| FIFO#1 | [E，1] | [E，2] | [E，3] | …… | [E，N-1] | [E，N] |
| FIFO#2 | [C，1] | [mid_1] | [mid_2] | …… | [mid_n-2] | [C，N] |
| FIFO#3 | [D，1] | [D2] | [D，3] | …… | [D，N-1] | [D，N] |
TABLE 8
(11) After the step (10), 3 asynchronous FIFO memories respectively store one line of image data again, namely 3 asynchronous FIFO memories buffer 3 lines of image data again, and the steps (1) to (10) are circulated, and all pixel lines of the original image are traversed; the cache, such as a RAM, an SRAM, a DDR, etc., stores therein an entire image, which is the image after the median filtering process.
The above-described embodiments of the present invention should not be construed as limiting the scope of the present invention. Any other corresponding changes and modifications made according to the technical idea of the present invention should be included in the protection scope of the claims of the present invention.
Claims (4)
1. A method for implementing median filtering using an FPGA, comprising the steps of:
(1) caching m lines of image data through m asynchronous FIFO memories;
(2) each asynchronous FIFO memory reads out m image data respectively, and the total number of the image data is m2Sending the image data to a sorting machine;
(3) forming m × m pixel matrix in sorter for m2Sorting the image data and calculating a median;
(4) replacing image data in the middle of a pixel matrix in the sorting machine with a median;
(5) respectively storing the m image data of the leftmost column of the pixel matrix in the sorting machine back to the corresponding asynchronous FIFO memories;
(6) reading out 1 image data from each asynchronous FIFO memory, and sending m image data into a sequencer;
(7) the m × m pixel matrix is formed again in the sorter for m2Sorting the image data and obtaining a median value;
(8) replacing image data in the middle of a pixel matrix in the sorting machine with a median;
(9) step (10) is carried out after all the image data in the m asynchronous FIFO memories are traversed in the circulating steps (5) - (8), and at the moment, the m multiplied by m window of the median filter is already swept by one line of image data;
(10) according to the order of arrangement of pixel lines of an original image, an asynchronous FIFO memory storing pixels of an upper line stores image data inside the asynchronous FIFO memory into a buffer memory, and stores unprocessed pixels of a next line of the original image into the asynchronous FIFO memory, wherein the buffer memory comprises: RAM, SRAM, DDR memory;
(11) after the step (10), each asynchronous FIFO memory stores one line of image data again, namely each asynchronous FIFO memory caches m lines of image data again, the steps (1) to (10) are circulated, and all pixel lines of the original image are traversed;
(12) the whole image stored in the buffer is the image subjected to the median filtering processing.
2. The method of claim 1, wherein m is an odd number.
3. The method for implementing median filtering using FPGA of claim 1 or 2 wherein m is 3.
4. The method of claim 1, wherein in step (12), the whole image is stored in the buffer memory, and the buffer memory includes RAM, SRAM, and DDR memory.
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