CN107966644A

CN107966644A - A kind of test pattern guard method of random key and circuit

Info

Publication number: CN107966644A
Application number: CN201710990097.9A
Authority: CN
Inventors: 王辉
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2017-10-23
Filing date: 2017-10-23
Publication date: 2018-04-27

Abstract

Test pattern guard method and circuit the invention discloses a kind of random key, receptions logic which includes being used to receive test pattern sequence and key, produce the NVM control logics of NVM control signals, the NVM memory for storing information, decryption logic, the data CL Compare Logic for comparing key, the randomizer for producing random key and the related register etc. for storing for decrypting NVM key.

Description

A kind of test pattern guard method of random key and circuit

Technical field

The invention belongs to the test design field of IC chip, and in particular to design for Measurability field, by will be every The key randomization of a chip, and encrypting storing, to improve security.

Background technology

Test pattern plays a very important role in chip testing process, possesses all access rights in test mode Limit, so just can guarantee that all circuits can be tested, and test pattern access method cannot be revealed easily, avoid attacker Possess access rights, steal and distort information.Therefore it is particularly important that the security of test pattern, once test pattern is broken, Security information in whole chip can arbitrarily be stolen.

Usually we protect test circuit with Fuse circuits, its principle is the output for the register of logic 1 by constant value A part for line is placed in scribe line, then is exported and entered Enable Pin to test circuit, while is adding the resistance of a weak pull-down to protect Shield.In non-scribing, the output logic 1 of register can enter Enable Pin for transmission to test circuit, and test pattern can be at this time Enter；And the output in scribing late register disconnects, test circuit Enable Pin can only receive the logical zero of weak pull-down resistance, at this time Test pattern can not enter.Fuse circuits have only served certain safeguard function, and attacker only needs to find in scribe line in Fuse lines, then connected by FIB can be to reenter test pattern.

In view of the foregoing, Fuse circuit protections ability is limited, it is necessary to which other methods ensure the security of test pattern.

The content of the invention

It is an object of the invention to improve test pattern protection circuit safety, realize that random key is tested by software and hardware Pattern guard method.

The present invention is a kind of test pattern guard method based on random key, using the implementation of software and hardware, in detail Technical solution be described as follows：

The hardware circuit of the present invention includes：One receive logic, a NVM control logic, a NVM memory, one Decryption logic, a data CL Compare Logic, a randomizer, some groups of data register (bags for being used to load information Include：Input cipher key register and NVM cipher key registers) and other relevant combinational logics etc..

The reception logic receives the cycle tests and key of IO inputs, carries out the correctness ratio of cycle tests first Compared with, after cycle tests is correct again by the key of reception export cipher key register to input.If cycle tests mistake, does not export close Key gives input cipher key register.

The NVM control logics, there is two functions：When the first, into test pattern, control NVM memory is stored Key read；2nd, when random key initializes, true random number is received, as random key, and produces and is written to true random number In NVM memory.

The randomizer, produces random number, and exports and give NVM control logics.

The NVM memory for storage chip information, receives the control signal that NVM control logics produce, will be defeated The data entered are stored into appropriate address, or the storage data of output appropriate address.

The decryption logic receives the output of NVM memory, is decrypted by self-defined decipherment algorithm, after decryption Key is different from NVM memory output key, is output to NVM cipher key registers.

The CL Compare Logic will input data in cipher key register data and NVM cipher key registers and be compared, if phase It is 1 to export test_mode_en signals Deng then, indicates entry into test pattern success；If unequal, test_mode_en signals For 0, test pattern failure is indicated entry into.

The operation principle of the present invention is as follows：

● before chip scribing, cycle tests and key are sent by IO into test pattern.The reception logic meeting of chip Receive and compare cycle tests, if cycle tests correctly if by key export cipher key register to input.CL Compare Logic is by key The input key of register and unified key are compared, and it is 1 that test_mode_en signals are exported if equal, indicates entry into survey The success of die trial formula；If unequal, test_mode_en signals are 0, indicate entry into test pattern failure.

● after chip scribing, cycle tests and key are sent by IO into test pattern.The reception logic meeting of chip Receive and compare cycle tests, if cycle tests correctly if by key export cipher key register to input.NVM control logics can incite somebody to action The key stored in NVM is read, and is stored in after decryption logic is decrypted in NVM cipher key registers.CL Compare Logic posts key The input key of storage and the decruption key of NVM cipher key registers are compared, and test_mode_en signals are exported if equal For 1, test pattern success is indicated entry into；If unequal, test_mode_en signals are 0, indicate entry into test pattern failure.

● chip random key is initialized, it is necessary to be carried out before scribing.Into after test pattern, randomizer produces Random number is write NVM particular address by random number, NVM control logics.It is defeated by IO from NVM memory reading to retell random number Go out, be saved in file.

The test pattern guard method of random key of the present invention, is produced close using chip internal randomizer Key so that be different from per the keys of chips, need to compare key when into test being pattern, improve test pattern protection Security.

The test pattern guard method of random key of the present invention, text is stored in after random key initialization by key In part, key in file is not decrypted to cannot be introduced into test pattern.By need before testing software safe to use into It could be used after row decryption, security software is identical with decryption logic decipherment algorithm in chip, externally secrecy.

Brief description of the drawings

Fig. 1 hardware circuit principle figures

Fig. 2 chip random key initialization flowcharts

Test pattern enters flow chart after Fig. 3 scribings

Embodiment

The embodiment of the present invention is described in detail below in conjunction with Figure of description.

As shown in Fig. 1 hardware circuit principle figures of the present invention, 1 represents and receives logic, and 2 represent NVM control logics, 3 represent with Machine number generator, 4 represent input cipher key register, and 5 represent NVM memory, and 6 represent decryption logic, and 7 represent NVM key deposits Device, 8 represent CL Compare Logic.

The 1 reception logic represented in Fig. 1, there is two functions：First, receive and whether just to judge the cycle tests of IO inputs Really；2nd, the key of reception is exported when cycle tests is correct and gives input cipher key register, otherwise do not exported.

2 in Fig. 1 represent NVM control logics, there is two functions：First, test pattern is into fashionable output NVM control signals, Key in NVM memory is read；When the 2nd, initializing, random number is received as random key, and produce NVM memory Control signal, random number is written in NVM memory.

3 in Fig. 1 represent randomizer, and it is to produce random number that it, which is acted on, is made as the key being stored in NVM With.

4 in Fig. 1 represent cipher key register, for storing input key and being supplied to CL Compare Logic to use.

5 in Fig. 1 represent the NVM memory of storage chip information, receive the control signal that NVM control logics produce, will The data of input are stored into appropriate address, or the storage data of output appropriate address.

6 in Fig. 1 represent decryption logic, for the key stored in NVM to be decrypted, obtain decruption key, output Give NVM cipher key registers.

7 in Fig. 1 represent NVM cipher key registers, for storing the decruption key of decryption logic output, and export to comparing Logic.

8 in Fig. 1 represent CL Compare Logic, and after chip is by scribing, the input key of cipher key register and NVM keys are posted The decruption key of storage is compared, and it is 1 that test_mode_en signals are exported if equal, indicates entry into test pattern success； If unequal, test_mode_en signals are 0, indicate entry into test pattern failure.When chip is not by scribing, key is posted The input key of storage and unified key are compared, and it is 1 that test_mode_en signals are exported if equal, indicates entry into test Pattern success；If unequal, test_mode_en signals are 0, indicate entry into test pattern failure.

Chip random key initialization flow is illustrated in Fig. 2.In the case of the non-scribing of chip, sent first by IO Cycle tests and unified key, in the case where not drawing control of disconnected Fuse, key is unified key at this time, therefore can enter test mould Formula.In test mode, NVM control logics read the random number that randomizer produces, and are written into NVM specifically Location.Random number is read from NVM memory again, is exported by IO, is saved in file.

Test pattern enters flow after scribing is illustrated in Fig. 3, calls special-purpose software to read key from file first, goes forward side by side Row decryption.Then test pattern sequence and decruption key will be sent by IO.The NVM control logics of chip can be from NVM at this time Key is read, decryption logic is sent into and is decrypted, be then re-fed into NVM cipher key registers.The solution that CL Compare Logic can input IO Key and the key of NVM cipher key registers are compared.If test pattern sequence is correct, decruption key compares correctly, then Test_mode_en signals are 1, into test pattern success；Otherwise test_mode_en signals are 0, are lost into test pattern Lose.

Claims

A kind of 1. test pattern protection circuit of random key, it is characterised in that：Deposited by reception logic, NVM control logics, NVM Reservoir, decryption logic, data CL Compare Logic, randomizer, some groups of data register, the Yi Jiqi for being used to load information Its relevant combinational logic etc. is formed, wherein：Some groups of data registers for being used to load information include input cipher key register With NVM cipher key registers.
A kind of 2. test pattern guard method of random key, applied to the circuit described in claim 1, it is characterised in that 1) Before chip scribing, cycle tests and unified key are sent by IO into test pattern；The reception logic of chip can receive and Compare cycle tests, if cycle tests correctly if by key export cipher key register to input；CL Compare Logic is by cipher key register Input key and unified key be compared, it is 1 that test_mode_en signals are exported if equal, indicates entry into test pattern Success；If unequal, test_mode_en signals are 0, indicate entry into test pattern failure；Chip random key initialized Journey before scribing, it is necessary to carry out；Into after test pattern, randomizer produces random number, and NVM control logics are by random number Write NVM particular address；Random number is read from NVM memory again and is exported by IO, is saved in file；2) in chip scribing Afterwards, the key preserved by security software decryption, then cycle tests and key are sent by IO；The reception logic of chip can receive With compare cycle tests, if cycle tests correctly if by key export cipher key register to input；NVM control logics can be by NVM The key of middle storage is read, and is stored in after decryption logic is decrypted in NVM cipher key registers；CL Compare Logic is by cipher key register Input key and the decruption keys of NVM cipher key registers be compared, test pattern success is entered if equal；If not phase Deng then into test pattern failure.
3. according to the method described in claim 2, it is characterized in that, chip keys are produced by randomizer, if random number Digit is enough, and the key per chips is all different in theory, and safety protection function is played by the randomness of key.
4. according to the method described in claim 2, it is characterized in that, key storage exports text in NVM memory, and by IO Part preserves；The key that file preserves needs just to obtain decruption key by proprietary software decryption, can just pass through the verification of chip Into test pattern.
5. according to the method described in claim 2, it is characterized in that, key storage in NVM memory, in the chip portion need It is decrypted by decrypting circuit, decipherment algorithm secrecy, key after decryption and input key are compared, compare correct ability Into test pattern, test pattern otherwise cannot be introduced into.
6. according to the method described in claim 2, it is characterized in that, it is decrypted by self-defined decipherment algorithm, after decryption Key is different from NVM memory output key, plays safety protection function.
7. according to the method described in claim 2, it is characterized in that, chip keys facilitate disk to survey to unify key before scribing Examination stage multi-chip is tested at the same time, and unified key is determined when chip designs.
8. according to the method described in claim 2, it is characterized in that, needed cipher key initialization before scribing, into test pattern, Randomizer key is write into NVM memory, then file is output to by IO and is preserved.
9. according to the method described in claim 2, it is characterized in that, chip is needed by IO input test moulds into test pattern Formula sequence and decruption key, test pattern sequence plays the role of preventing being strayed into and secret and safe, key then play safety effect.