CN107958903A - The processing method and encapsulating structure of a kind of encapsulating structure - Google Patents
The processing method and encapsulating structure of a kind of encapsulating structure Download PDFInfo
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- CN107958903A CN107958903A CN201711190687.XA CN201711190687A CN107958903A CN 107958903 A CN107958903 A CN 107958903A CN 201711190687 A CN201711190687 A CN 201711190687A CN 107958903 A CN107958903 A CN 107958903A
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- 238000003672 processing method Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 154
- 230000006698 induction Effects 0.000 claims abstract description 35
- 238000004020 luminiscence type Methods 0.000 claims abstract description 33
- 238000004806 packaging method and process Methods 0.000 claims description 17
- 229920003023 plastic Polymers 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 16
- 238000005538 encapsulation Methods 0.000 claims description 8
- 238000004891 communication Methods 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 4
- 238000009738 saturating Methods 0.000 claims 1
- 238000012536 packaging technology Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 19
- 230000008569 process Effects 0.000 description 13
- 229910000679 solder Inorganic materials 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000012945 sealing adhesive Substances 0.000 description 6
- 239000000084 colloidal system Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 239000000411 inducer Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000686 essence Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/165—Containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Laminated Bodies (AREA)
Abstract
The present invention provides a kind of processing method and encapsulating structure of encapsulating structure, solves the problems, such as to be easily deformed using encapsulating structure made of existing packaging technology.The encapsulating structure of the present invention includes:Underlying substrate, is provided with induction chip and luminescence chip on underlying substrate;Middle laminar substrate, middle laminar substrate are located at the upper surface of underlying substrate, and the position that middle laminar substrate corresponds to induction chip is provided with the first hollow-out parts, the position of luminescence chip is provided with the second hollow-out parts;Top substrate layer, top substrate layer are located at the upper surface of middle laminar substrate, and the position that top substrate layer corresponds to each induction chip is provided with the first perforate, the position of each luminescence chip is provided with the second perforate.The encapsulating structure of the present invention stacks gradually middle laminar substrate and top substrate layer on underlying substrate, three pieces of substrates being stacked can greatly promote product strength and rigidity, prevent from producing warpage because underlying substrate is too thin, while product internal stress can be reduced, lift product reliability.
Description
Technical field
The present embodiments relate to the technical field of encapsulating structure design, more particularly to a kind of processing method of encapsulating structure
And encapsulating structure.
Background technology
With the continuous development of mobile terminal, wearable device and artificial intelligence, to the demand of various optical inducers
It is more and more.On mobile terminal and wearable device, due to the limitation of structure size itself, can only selection of small size or
Elongated optical inducer.Such as the promotion that mobile phone shields comprehensively, it is very limited to put the position of optics, so can only select
The optics of strip.The encapsulating structure of optics mainly has two kinds at present:1) produced using sealing adhesive process twice;2) one
Secondary sealing adhesive process+upper cover.
Since optics is required for the colloid of envelope layer of transparent, such transparent colloid is generally without filler or containing only non-
The filler of Chang Shaoliang, causes such transparent colloid to shrink general all bigger, and substrate causes product after encapsulating than relatively thin
It is easily deformed.The encapsulating structure such as generated by above-mentioned sealing adhesive process twice, due to the thermal expansion coefficient difference of two kinds of colloids, very
It is easy to cause colloid internal cleavage.And the encapsulating structure of a sealing adhesive process+upper cover is used, upper cover generally uses gluing or buckle
On substrate, this class formation major defect has following several note:1) superstructure is complicated, and manufacture is difficult, and 2) upper cover note dress effect
Rate is poor;3) upper cover is pasted loosely, is easily come off;4) string configuration product warpage is serious, causes to pass through surface mounting technology
(Surface Mount Technology, the abbreviation of abbreviation SMT) carries out abnormal welding during note dress, it can be seen that using existing
Encapsulating structure is easily deformed made of packaging technology, reduces the reliability of product.
The content of the invention
The embodiment of the present invention provides a kind of processing method and encapsulating structure of encapsulating structure, to solve to use existing encapsulation work
The problem of encapsulating structure is easily deformed made of skill.
In order to solve the above-mentioned technical problem, the present invention is realized in:
In a first aspect, an embodiment of the present invention provides a kind of encapsulating structure, including:
Underlying substrate, is provided with induction chip and luminescence chip on the underlying substrate;
Middle laminar substrate, the middle laminar substrate are located at the upper surface of the underlying substrate, right on the middle laminar substrate
The position of induction chip described in Ying Yu is provided with the first hollow-out parts, and the position of the luminescence chip is corresponded on the middle laminar substrate
Install and be equipped with the second hollow-out parts;
Top substrate layer, the top substrate layer are located at the upper surface of the middle laminar substrate, and the top substrate layer corresponds to every
The position of a induction chip is provided with the first perforate, and the position that the top substrate layer corresponds to each luminescence chip is set
It is equipped with the second perforate.
Second aspect, an embodiment of the present invention provides a kind of processing method of encapsulating structure, including:
At least two groups of chip is placed on underlying substrate, every group of chip includes an induction chip and a luminescence chip,
And every group of chip with the circuit communication in the underlying substrate;
In each induction chip and the transparent plastic packaging layer of surface encapsulation of each luminescence chip;
Middle laminar substrate and top substrate layer are stacked gradually on the surface of underlying substrate, forms encapsulating structure assembly;
The encapsulating structure assembly is divided at least two encapsulating structures, each encapsulating structure includes a sensing
Chip and a luminescence chip;
Wherein, the middle laminar substrate is provided with the first hollow-out parts corresponding to the position of each induction chip, described
The position that middle laminar substrate corresponds to each luminescence chip is provided with the second hollow-out parts;The top substrate layer corresponds to each
The position of the induction chip is provided with the first perforate, and the position that the top substrate layer corresponds to each luminescence chip is set
There is the second perforate.
In embodiments of the present invention, by stacking gradually middle laminar substrate and top substrate layer on underlying substrate, envelope is formed
Assembling structure assembly;The encapsulating structure assembly is divided at least two encapsulating structures, each encapsulating structure includes one
Induction chip and a luminescence chip.Three pieces of substrates being stacked in the embodiment of the present invention can greatly promote product strength
And rigidity, prevent from producing warpage because underlying substrate is too thin, while product internal stress can be reduced, product reliability is lifted, and
Shorten fabrication cycle.
Brief description of the drawings
Fig. 1 is the structure diagram of the encapsulating structure of the embodiment of the present invention;
Fig. 2 is the flow chart of the processing method of the encapsulating structure of the embodiment of the present invention;
Fig. 3 is the schematic diagram for setting chip in the embodiment of the present invention on underlying substrate;
Fig. 4 is the schematic diagram for forming transparent plastic packaging layer in the embodiment of the present invention in chip surface;
Fig. 5 is the schematic diagram for setting connecting material in the embodiment of the present invention on underlying substrate;
Fig. 6 be the embodiment of the present invention processing method in underlying substrate, middle laminar substrate and top substrate layer structural representation
Figure.
Embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Described into ground, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without creative efforts
Embodiment, belongs to the scope of protection of the invention.
As shown in Figure 1, the embodiment provides a kind of encapsulating structure, which includes:
Underlying substrate 1, is provided with induction chip 11 and luminescence chip 12 on the underlying substrate 1;
Middle laminar substrate 2, the middle laminar substrate 2 are located at the upper surface of the underlying substrate 1, the middle laminar substrate 2
The upper position corresponding to the induction chip 11 is provided with the first hollow-out parts 21, corresponds to the hair on the middle laminar substrate 2
The position of optical chip 12 is provided with the second hollow-out parts 22;
Top substrate layer 3, the top substrate layer 3 are located at the upper surface of the middle laminar substrate 2, and the top substrate layer 3 corresponds to
The position of each induction chip 11 is provided with the first perforate 31, the top substrate layer 3 corresponds to each luminous core
The position of piece 12 is provided with the second perforate 32.
Specifically, the appearance profile of the middle laminar substrate 2 is in day font, and induction chip and a luminescence chip are logical
Cross connecting line and the circuit communication in the underlying substrate.
The encapsulating structure of the embodiment of the present invention, stacks gradually middle laminar substrate and top substrate layer on underlying substrate, stacks
Three pieces of substrates together can greatly promote product strength and rigidity, prevent from producing warpage because underlying substrate is too thin, at the same time
Product internal stress can be reduced, lifts product reliability.
Further, as shown in Figure 1, the encapsulating structure of the embodiment of the present invention, further includes:
It is arranged at the transparent plastic packaging layer 14 on 12 surface of the induction chip 11 and the luminescence chip.
Specifically, using encapsulation molding techniques, using transparent capsulation material by induction chip 11, luminescence chip 12
And 13 plastic packaging of connecting line gets up, transparent plastic packaging layer 14 is formed.
Further, the height of the transparent plastic packaging layer 14 is less than the height of the middle laminar substrate 2, i.e., transparent plastic packaging layer
Respectively in the first hollow-out parts 21 of middle laminar substrate 2 and in the second hollow-out parts 22.
Further, it is respectively arranged with positioning in the underlying substrate 1, the middle laminar substrate 2 and the top substrate layer 3
Hole.
It is convenient in underlying substrate by setting location hole respectively in underlying substrate 1, middle laminar substrate 2 and top substrate layer 3
Positioned when upper stacking centre laminar substrate and top substrate layer.
The encapsulating structure of the embodiment of the present invention, stacks gradually middle laminar substrate and top substrate layer on underlying substrate, stacks
Three pieces of substrates together can greatly promote product strength and rigidity, prevent from producing warpage because underlying substrate is too thin, at the same time
Product internal stress can be reduced, lifts product reliability.
As shown in Fig. 2, the embodiment of the present invention additionally provides a kind of processing method of encapsulating structure, including:
Step 201:At least two groups of chip is set on underlying substrate, and every group of chip includes an induction chip and a hair
Optical chip, and every group of chip with the circuit communication in the underlying substrate.
Specifically, at least two groups of chip is sticked on 1 surface of underlying substrate, as shown in figure 3, every group of chip includes one
Induction chip 11 and a luminescence chip 12;Routing processing is carried out to every group of chip, obtains connecting the electricity in the underlying substrate
Road and the connecting line 13 of every group of chip.
When setting chip on underlying substrate, generally by using bonding die film (Die Attach Film, DAF) material or
Chip adhesion glue.
Step 202:In each induction chip and the transparent plastic packaging layer of surface encapsulation of each luminescence chip.
Plastic packaging processing is carried out to each induction chip and each luminescence chip using transparent encapsulation material, is formed
Transparent plastic packaging layer.
Specifically, using encapsulation molding techniques, chip and connecting line 13 are closed using transparent capsulation material,
Transparent plastic packaging layer 14 is formed, obtains structure as shown in Figure 4.
Step 203:Middle laminar substrate and top substrate layer are stacked gradually on the surface of underlying substrate, it is total to form encapsulating structure
Into.
Wherein, as shown in Figure 1, the position that the middle laminar substrate 2 corresponds to each induction chip 11 is provided with the
One hollow-out parts 21, and the position of each luminescence chip 12 is provided with the second hollow-out parts 22;The top substrate layer 3 is right
The position of each induction chip 11 should be provided with the first perforate 31, and corresponding to the position of each luminescence chip 12
It is provided with the second perforate 32.
Further, before above-mentioned steps 203, further include:
Increase connecting material on the pad of middle 2 upper surface of laminar substrate;
And/or increase connecting material on the pad of 3 lower surface of top substrate layer.
The connecting material is specially glue or solder.
At this time, above-mentioned steps 203 specifically include:As shown in figure 5, added on the pad of 1 upper surface of underlying substrate
Connecting material 15, in addition, as shown in fig. 6, in process of production, can be by the way of big sheetpile be folded, by determining on underlying substrate 1
Location hole 4 of the position hole 4 respectively with the middle laminar substrate 2 and the top substrate layer 3 aligns;After the alignment of above-mentioned location hole 4, lead to
The connecting material 15 is crossed, the middle laminar substrate 2 and the top substrate layer 3 are set gradually on the surface of the underlying substrate 1.
Top substrate layer can be substrate, or the material such as sheet metal, resin.
In a specific embodiment of the present invention, in the lower surface stud weldering of the upper surface of middle laminar substrate or cover plate of upper layer
Cementing or solder on disk, and glue or solder on the stud pad point of underlying substrate, are then determined by location hole
Position, three pieces of substrates are stacked up by upper, middle and lower, then dry glue through overbaking.Solder is such as used, then heap is folded
Reflow Soldering (reflow) is crossed afterwards to weld together three blocks of plates, forms encapsulating structure assembly.
Spray tin (pre-solder) is done on the pad of the top and bottom of middle laminar substrate in addition, can also use, then brush helps
Welded after heap is folded after solder flux by the way of Overwelding and rewelding furnace.
It should be noted that above-mentioned stud pad is by way of example only, can also be other shapes in the embodiment of the present invention
The pad of shape, and if not using solder, pad can not also be used.
Step 204:The encapsulating structure assembly is divided at least two encapsulating structures, each encapsulating structure includes
One induction chip and a luminescence chip.
As shown in fig. 6, can be folded in process of production using big sheetpile it is packaged after cut into single product again, effectively carry
Rise production efficiency.Specifically, the encapsulating structure assembly is divided at least after completing lettering in place as needed
Two encapsulating structures, obtain encapsulating structure as shown in Figure 1.
The processing method of the encapsulating structure of the embodiment of the present invention, upper cover process is replaced by the way of three laminar substrates stacking,
Three pieces of substrates bind together to form an entirety, lift the strength and stiffness of whole product, avoid the occurrence of the situation of lid,
Substrate too thin the drawbacks of being easily deformed in upper cover process is effectively solved, and is compared compared to traditional sealing adhesive process twice, in product
Stress is smaller, can lift product reliability, in addition, whole packaging technology is very simple, and can be stacked with full page, compared to upper cover
Technique and twice sealing adhesive process, production efficiency significantly improve.
Each embodiment in this specification is described by the way of progressive, what each embodiment stressed be with
The difference of other embodiment, between each embodiment identical similar part mutually referring to.
Although having been described for the preferred embodiment of the embodiment of the present invention, those skilled in the art once know base
This creative concept, then can make these embodiments other change and modification.So appended claims are intended to be construed to
Including preferred embodiment and fall into all change and modification of range of embodiment of the invention.
Finally, it is to be noted that, herein, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or order.Moreover, term " comprising ", "comprising" or its any other variant meaning
Covering non-exclusive inclusion, so that process, method, article or terminal device including a series of elements are not only wrapped
Those key elements are included, but also including other elements that are not explicitly listed, or further include as this process, method, article
Or the key element that terminal device is intrinsic.In the absence of more restrictions, wanted by what sentence "including a ..." limited
Element, it is not excluded that also there are other identical element in the process including the key element, method, article or terminal device.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
With within principle, any modification, equivalent replacement, improvement and so on, should all be included in the protection scope of the present invention god.
Claims (10)
- A kind of 1. encapsulating structure, it is characterised in that including:Underlying substrate, is provided with induction chip and luminescence chip on the underlying substrate;Middle laminar substrate, the middle laminar substrate are located at the upper surface of the underlying substrate, correspond on the middle laminar substrate The position of the induction chip is provided with the first hollow-out parts, and the position that the luminescence chip is corresponded on the middle laminar substrate is set It is equipped with the second hollow-out parts;Top substrate layer, the top substrate layer are located at the upper surface of the middle laminar substrate, and the top substrate layer corresponds to each institute The position for stating induction chip is provided with the first perforate, and the position that the top substrate layer corresponds to each luminescence chip is provided with Second perforate.
- 2. encapsulating structure according to claim 1, it is characterised in that the encapsulating structure further includes:It is arranged at the induction chip and the transparent plastic packaging layer on the luminescence chip surface.
- 3. encapsulating structure according to claim 2, it is characterised in that the height of the transparent plastic packaging layer is less than the centre The height of laminar substrate.
- 4. encapsulating structure according to claim 1, it is characterised in that the appearance profile of the middle laminar substrate is in day word Type.
- 5. encapsulating structure according to claim 1, it is characterised in that the underlying substrate, the middle laminar substrate and institute State and location hole is respectively arranged with top substrate layer.
- A kind of 6. processing method of encapsulating structure, it is characterised in that including:At least two groups of chip is placed on underlying substrate, every group of chip includes an induction chip and a luminescence chip, and often Group chip with the circuit communication in the underlying substrate;In each induction chip and the transparent plastic packaging layer of surface encapsulation of each luminescence chip;Middle laminar substrate and top substrate layer are stacked gradually on the surface of underlying substrate, forms encapsulating structure assembly;The encapsulating structure assembly is divided at least two encapsulating structures, each encapsulating structure includes an induction chip With a luminescence chip;Wherein, the middle laminar substrate is provided with the first hollow-out parts, the centre corresponding to the position of each induction chip The position that laminar substrate corresponds to each luminescence chip is provided with the second hollow-out parts;The top substrate layer corresponds to each described The position of induction chip is provided with the first perforate, and the position that the top substrate layer corresponds to each luminescence chip is provided with the Two perforates.
- 7. the processing method of encapsulating structure according to claim 6, it is characterised in that it is described set on underlying substrate to The step of few two groups of chip, including:In the underlying substrate surface mount at least two groups of chip;Routing processing is carried out to every group of chip, obtains connecting the connecting line of the circuit and every group of chip in the underlying substrate.
- 8. the processing method of encapsulating structure according to claim 6, it is characterised in that described in each induction chip The step of transparent plastic packaging layer being formed with the surface of each luminescence chip, including:Using transparent encapsulation material, plastic packaging processing is carried out to each induction chip and each luminescence chip, is formed saturating Bright plastic packaging layer.
- 9. the processing method of encapsulating structure according to claim 6, it is characterised in that set successively on the surface of underlying substrate Before the step of putting middle laminar substrate and top substrate layer, forming encapsulating structure assembly, further include:Increase connecting material on the pad of the intermediate layer upper surface of base plate;And/or increase connecting material on the pad of the top substrate layer lower surface.
- 10. the processing method of encapsulating structure according to claim 9, it is characterised in that described on the surface of underlying substrate The step of setting gradually middle laminar substrate and top substrate layer, forming encapsulating structure assembly, including:Connecting material is added on the pad of the underlying substrate upper surface;Location hole of the location hole on underlying substrate respectively with the middle laminar substrate and the top substrate layer is alignd;After location hole alignment, by the connecting material, the centre is set gradually on the surface of the underlying substrate Laminar substrate and the top substrate layer.
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108172570A (en) * | 2017-12-25 | 2018-06-15 | 维沃移动通信有限公司 | A kind of optical device, preparation method and equipment |
CN109216338A (en) * | 2018-10-25 | 2019-01-15 | 深圳市创显光电有限公司 | A kind of induction type LED matrix and its application method |
CN109378702A (en) * | 2018-11-30 | 2019-02-22 | 华天科技(西安)有限公司 | A kind of VCSEL sensor-packaging structure and its packaging method |
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