CN107919435B - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN107919435B CN107919435B CN201610882468.7A CN201610882468A CN107919435B CN 107919435 B CN107919435 B CN 107919435B CN 201610882468 A CN201610882468 A CN 201610882468A CN 107919435 B CN107919435 B CN 107919435B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/01—Manufacture or treatment
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors. Providing a semiconductor substrate and a plurality of laminated structures which are sequentially formed on the semiconductor substrate from bottom to top, wherein each laminated structure comprises a sacrificial layer and an isolation layer which are sequentially formed; sequentially forming an insulating layer and a pinning layer on the semiconductor substrate to cover the semiconductor substrate and the plurality of laminated structures; forming a middle cut cutting off the plurality of laminated structures and the insulating layer and the pinning layer positioned on the laminated structures; etching and removing the sacrificial layer exposed in the middle cut to form a groove; forming a free layer in the groove; a magnetoelectric layer is formed in the central cutout. According to the manufacturing method of the semiconductor device provided by the embodiment of the invention, the pinning layer, the insulating layer, the free layer and the magnetoelectric layer which are sequentially arranged from outside to inside are formed by deposition, etching, filling and other methods, so that a 3D magnetoelectric magnetic tunnel junction is formed, and the manufacturing method of the semiconductor device is favorable for manufacturing electronic devices with high density, high speed and low power consumption.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
In the current day-to-day information age. Large capacity, high speed, high density, and low power consumption have been inevitable trends in the development of information storage. The Magnetic Tunnel Junction (MTJs) structure has the characteristics of high resistivity, low energy consumption, stable performance and the like. Therefore, MTJs have the advantages of incomparable property no matter being used as a read head, various sensors or a Magnetic Random Access Memory (MRAM), and the application prospect is very good.
In MTJs, the generation mechanism of the Tunnel magnetoresistive effect (TMR) is a spin-dependent tunneling effect. The general structure of MTJs is a sandwich of ferromagnetic/nonmagnetic insulating/ferromagnetic (FM/I/FM) layers. In saturation magnetization, the magnetization directions of the two ferromagnetic layers are parallel to each other, but the coercive forces of the two ferromagnetic layers are usually different, so that in reverse magnetization, the magnetization vectors of the ferromagnetic layers with small coercive force are firstly inverted, so that the magnetization directions of the two ferromagnetic layers become antiparallel. The tunneling probability of electrons from one magnetic layer to the other is related to the magnetization direction of the two magnetic layers. If the magnetization directions of the two layers are parallel to each other, in one magnetic layer, electrons of a majority spin subband enter the empty state of the majority spin subband in the other magnetic layer, electrons of a minority spin subband also enter the empty state of the minority spin subband in the other magnetic layer, and the total tunneling current is larger; if the magnetization directions of the two magnetic layers are antiparallel, the situation is just opposite, namely in one magnetic layer, the electrons of the majority spin subband will enter the empty state of the minority spin subband in the other magnetic layer, and the electrons of the minority spin subband will also enter the empty state of the majority spin subband in the other magnetic layer, and the tunneling current of the state is relatively small. Thus, the tunneling conductance changes with the change in the magnetization directions of the two ferromagnetic layers, and the conductance is higher when the magnetization vectors are parallel than when they are antiparallel. The magnetization directions of the two ferromagnetic layers can be changed by applying an external magnetic field, so that the tunneling resistance is changed, and the TMR effect is caused.
An applied Electric field can change the magnetic properties of the medium, or an applied magnetic field can change the Electric polarization properties of the medium, and this effect is called a Magneto-Electric effect (Magneto-Electric effect). The magnetoelectric material is a novel magnetoelectric functional material with magnetoelectric effect, has ferromagnetism, ferroelectricity, ferroelasticity and the like, is favorable for coupling among spontaneous polarization, spontaneous magnetization and spontaneous deformation, and has great potential application value in the aspects of information recording memories, magnetic field detection, sensors and the like.
Currently, memory devices are moving toward high speed, high density trends. The manufacturing of a high-performance 3D magnetoelectric Tunnel Junction (ME-MTJ) is beneficial to manufacturing electronic devices with high density, high speed and low power consumption.
In view of the shortcomings of the prior art, the present invention provides a new method for manufacturing a semiconductor device.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the shortcomings of the prior art, the present invention provides a method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate and a plurality of laminated structures which are sequentially formed on the semiconductor substrate from bottom to top, wherein each laminated structure comprises a sacrificial layer and an isolation layer which are sequentially formed;
sequentially forming an insulating layer and a pinning layer on the semiconductor substrate to cover the semiconductor substrate and the plurality of laminated structures;
forming a middle cut cutting off the plurality of laminated structures and the insulating layer and the pinning layer positioned on the laminated structures;
etching and removing the sacrificial layer exposed in the middle cut to form a groove;
forming a free layer in the groove;
a magnetoelectric layer is formed in the central cutout.
Further, the material of the magnetoelectric layer comprises an antiferromagnetic material Cr2O3。
Further, the magnetoelectric layer is connected with a word line.
Further, the free layer connects bit lines.
Further, the sacrificial layer is removed by wet etching.
Further, the sacrificial layer comprises a silicon nitride layer and the isolation layer comprises an oxide layer.
Further, the free layer and pinned layer are ferromagnetic materials.
Further, the step of forming a protective layer on the semiconductor substrate around the plurality of stacked structures is further included before forming the central cutout.
Further, the protective layer is removed after the formation of the magneto-electric layer.
Further, the method may further include the step of forming an oxide dielectric layer disposed around the several stacked structures on the semiconductor substrate after forming the magneto-electric layer.
Further, the method further comprises the step of forming an interconnect layer on the oxide dielectric layer.
Further, the pinning layer, the insulating layer, the free layer and the magnetoelectric layer jointly form a 3D magnetoelectric magnetic tunnel junction.
The present invention also provides a semiconductor device formed by the above manufacturing method, comprising:
a semiconductor substrate;
a 3D magnetoelectric magnetic tunnel junction formed on a semiconductor substrate;
the 3D magnetoelectric magnetic tunnel junction includes: a pinning layer, an insulating layer, a free layer, and a magneto-electric layer.
According to the manufacturing method of the semiconductor device provided by the embodiment of the invention, the pinning layer, the insulating layer, the free layer and the magnetoelectric layer which are sequentially arranged from outside to inside are formed by deposition, etching, filling and other methods, so that a 3D magnetoelectric magnetic tunnel junction is formed, and the manufacturing method of the semiconductor device is favorable for manufacturing electronic devices with high density, high speed and low power consumption.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail embodiments of the present invention with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings, like reference numbers generally represent like parts or steps.
In the drawings:
fig. 1A to 1K are schematic cross-sectional views of devices respectively obtained by steps sequentially performed by a method according to an exemplary embodiment one of the present invention.
Fig. 2 is a schematic flow chart of a method of manufacturing a semiconductor device according to a first exemplary embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to provide a thorough understanding of the present invention, detailed steps and detailed structures will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In the information age, which is now changing day by day, large capacity, high speed, high density, and low power consumption have become inevitable trends in the development of information storage.
The Magnetic Tunnel Junction (MTJs) structure has the characteristics of high resistivity, low energy consumption, stable performance and the like. Therefore, MTJs have the advantages of incomparable property no matter being used as a read head, various sensors or a Magnetic Random Access Memory (MRAM), and the application prospect is very good.
The magnetoelectric material is a novel magnetoelectric functional material with magnetoelectric effect, can change the magnetic property of a medium through an external electric field, or can change the electric polarization property of the medium through an external magnetic field, has ferromagnetism, ferroelectricity, ferroelasticity and the like, is favorable for coupling among spontaneous polarization, spontaneous magnetization and spontaneous deformation, and has great potential application value in the aspects of information recording memories, magnetic field detection, sensors and the like.
In summary, manufacturing a high-performance 3D magnetoelectric tunnel Junction (ME-MTJ) is advantageous for manufacturing high-density, high-speed, and low-power electronic devices.
In view of the shortcomings of the prior art, the present invention provides a new method for manufacturing a semiconductor device.
Providing a semiconductor substrate and a plurality of laminated structures which are sequentially formed on the semiconductor substrate from bottom to top, wherein each laminated structure comprises a sacrificial layer and an isolation layer which are sequentially formed;
sequentially forming an insulating layer and a pinning layer on the semiconductor substrate to cover the semiconductor substrate and the plurality of laminated structures;
forming a middle cut cutting off the plurality of laminated structures and the insulating layer and the pinning layer positioned on the laminated structures;
etching and removing the sacrificial layer exposed in the middle cut to form a groove;
forming a free layer in the groove;
a magnetoelectric layer is formed in the central cutout.
The magneto-electric layer is made of an antiferromagnetic material, the free layer and the pinned layer are made of a ferromagnetic material, the sacrificial layer comprises a silicon nitride layer, and the isolation layer comprises an oxide layer; the magnetoelectric layer is connected with a word line, and the free layer is connected with a bit line. The pinning layer, the insulating layer, the free layer and the magnetoelectric layer jointly form a 3D magnetoelectric magnetic tunnel junction.
According to the manufacturing method of the semiconductor device provided by the embodiment of the invention, the pinning layer, the insulating layer, the free layer and the magnetoelectric layer which are sequentially arranged from outside to inside are formed by deposition, etching, filling and other methods, so that a 3D magnetoelectric magnetic tunnel junction is formed, and the manufacturing method of the semiconductor device is favorable for manufacturing electronic devices with high density, high speed and low power consumption.
[ example one ]
In order to solve the problems in the prior art, the present invention provides a method for manufacturing a semiconductor device, which is further described with reference to the accompanying drawings.
Referring to fig. 1A-1K, there are shown schematic cross-sectional views of devices respectively obtained by sequential steps of a method according to an exemplary embodiment one of the present invention.
First, as shown in fig. 1A and 1B, a semiconductor substrate 100 is provided, on which a plurality of stacked structures are sequentially formed from bottom to top, each stacked structure including a sacrificial layer 101 and an isolation layer 102 which are sequentially formed. As an example, a first sacrificial layer 101a, a first isolation layer 102a, a second sacrificial layer 101b, a second isolation layer 102b, a third sacrificial layer 101c, and a third isolation layer 102c are sequentially formed on the semiconductor substrate 100. The present embodiment is illustrated by a three-layer stacked structure, which is not intended to limit the present invention, and those skilled in the art will understand that other stacked structures with different numbers of layers can also implement the present invention.
Illustratively, the semiconductor substrate 100 includes transistors and internal interconnect structures for electrically connecting the transistors, which are not shown for simplicity of the drawing. The sacrificial layer 101 is made of silicon nitride, and the isolation layer 102 is made of silicon dioxide. The formation of the sacrificial layer 101 and the isolation layer 102 can be performed by any conventional method known to those skilled in the art, including Physical Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD), preferably Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), and Plasma Enhanced Chemical Vapor Deposition (PECVD).
An etching process is performed on the edge portions of the sacrificial layer 101 and the isolation layer 102 to form a stacked structure having a target width. Illustratively, the edge portions of the sacrificial layer 101 and the isolation layer 102 may be etched using wet etching or dry etching methods well known to those skilled in the art to reach a target width. And performing the wet etching by using a solution with the same or similar selection ratio of the isolating layer material to the sacrificial layer material. In the present embodiment, the sacrificial layer 101 and the isolation layer 102 are etched using a hydrofluoric acid solution.
Next, as shown in fig. 1C, an insulating layer 103 and a pinning layer 104 are sequentially formed on the semiconductor substrate 100 to cover the semiconductor substrate 100 and the several-layer stacked structure. Illustratively, the insulating layer 103 and the pinning layer 104 may be formed by any conventional method known to those skilled in the art, such as Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD). The insulating layer 103 can comprise a conductive material (e.g., Cu, Au, Ta, Ag, CuPt, CuMn) or a non-conductive material (e.g., Al)xOy、MgO、AlN、SiN、CaOx、NiOx、HfxOy、TaxOy、ZrxOy、NiMnOx、MgxFy、SiC、SiO2、SiOxNy) Or any combination of the above materials. The pinned layer 104 may comprise a ferromagnetic material, such as (e.g., Co, Fe, Ni, or alloys thereof NiFe, CoFe, CoNiFe, or doped alloys CoX, CoFeX, CoNiFeX (X ═ B, Cu, Re, Ru, Rh, Hf, Pd, Pt, C), or other semi-metallic ferromagnetic materials (e.g., Fe, Ni, or alloys thereof NiFe, CoFe, or alloys thereof) or other semi-metallic ferromagnetic materials (e.g., Fe3O4、CrO2NiMnSb and PtMnSb, and BiFeO).
Next, as shown in fig. 1D, a protective layer 105 disposed around the several laminated structures is formed on the semiconductor substrate 100. Illustratively, the material of the protective layer comprises an NFC ferrite wave-absorbing material. The protective layer may serve as a mask to protect the insulating layer 103 and the pinning layer 104 in a subsequent process. The protective layer can be formed by any method known to those skilled in the art, including Physical Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD), preferably Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD).
Next, as shown in fig. 1E, a central slit 106 that cuts off the several-layer laminated structure and the insulating layer 103 and the pinning layer 104 located thereon is formed. Illustratively, the several-layer stacked structure and the insulating layer 103 and the pinning layer 104 thereon may be longitudinally etched and cut from top to bottom using anisotropic dry etching to form a middle notch. Dry etching processes include, but are not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may also be used, or more than one etching method may also be used. The source gas for the dry etch may comprise HBr and/or CF4A gas.
Next, as shown in fig. 1F, the sacrificial layer 101 exposed in the middle cut is etched to form a groove. Illustratively, the sacrificial layer may be etched using wet or dry etching methods well known to those skilled in the art. And performing the wet etching by using a solution with a high selection ratio of the sacrificial layer material to the isolation layer material. As an example, 85% H heated to 180 ℃ is used3PO4The solution etches the silicon nitride.
Next, as shown in fig. 1G and 1H, a free layer 107 is formed in the groove. Illustratively, the free layer 107 may comprise a ferromagnetic material, such as (e.g., Co, Fe, Ni or alloys thereof NiFe, CoFe, CoNiFe, or doped alloys CoX, CoFeX, CoNiFeX (X ═ B, Cu, Re, Ru, Rh, Hf, Pd, Pt, C), or other semi-metallic ferromagnetic materials (e.g., Fe3O4、CrO2NiMnSb and PtMnSb, and BiFeO). In the process of forming the free layer, the method also comprises the step of etching and removing the redundant material deposited on the side wall and the bottom of the middle cut.
Next, as shown in fig. 1I, the middle notch 106 is filled with a magneto-electric layer 108. Illustratively, the magnetoelectric layer is an antiferromagnetic material comprising Cr2O3. Method for forming magnetoelectric layerThe method may be any of the techniques known to those skilled in the art, including Physical Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD), preferably Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD).
Next, as shown in fig. 1J and fig. 1K, the protection layer 105 is etched away, and an oxide dielectric layer 109 is formed at the original protection layer position. Illustratively, the material of the oxide dielectric layer comprises SiO2. The oxide layer may be removed by dry etching, and the dry etching process includes but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may also be used, or more than one etching method may also be used. The oxide layer may be formed by any conventional method known to those skilled in the art, including Physical Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD).
In the subsequent process, the method also comprises a step of connecting the magnetoelectric layer with the word line and the free layer with the bit line, and a step of forming a metal interconnection layer on the oxide dielectric layer.
Referring to fig. 2, a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown to schematically illustrate the flow of the entire manufacturing process.
In step S201, providing a semiconductor substrate, and a plurality of stacked structures sequentially formed on the semiconductor substrate from bottom to top, each stacked structure including a sacrificial layer and an isolation layer sequentially formed;
in step S202, sequentially forming an insulating layer and a pinning layer on the semiconductor substrate to cover the semiconductor substrate and the several-layer stacked structure;
in step S203, forming a middle cut cutting off the several-layer stacked structure and the insulating layer and the pinning layer thereon;
in step S204, etching and removing the sacrificial layer exposed in the middle cut to form a groove;
in step S205, a free layer is formed in the groove;
in step S206, a magnetoelectric layer is formed in the central slit.
[ example two ]
The structure of the semiconductor device provided by the embodiment of the invention is described below with reference to fig. 1K.
As shown in fig. 1K, the structure of the semiconductor device provided by the present invention includes a semiconductor substrate 100; a 3D magnetoelectric magnetic tunnel junction formed on a semiconductor substrate; the 3D magnetoelectric magnetic tunnel junction comprises a pinning layer 104, an insulating layer 103, a free layer 107 and a magnetoelectric layer 108 which are arranged from outside to inside at one time.
The semiconductor device can be manufactured by the method for manufacturing a semiconductor device according to the first embodiment. As an example, the semiconductor substrate 100 includes transistors and internal interconnect structures (not shown) for electrically connecting the transistors, and the pinning layer 104, the insulating layer 103, the free layer 107, and the magnetoelectric layer 108 may be formed by any conventional method known to those skilled in the art, including Physical Vapor Deposition (PVD) and Chemical Vapor Deposition (CVD), preferably Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), and Plasma Enhanced Chemical Vapor Deposition (PECVD). The magnetic electric layer is made of antiferromagnetic material, and the free layer and the pinning layer are made of ferromagnetic material. The magnetoelectric layer is connected with a word line, and the free layer is connected with a bit line. The pinning layer, the insulating layer, the free layer and the magnetoelectric layer jointly form a 3D magnetoelectric magnetic tunnel junction.
According to the manufacturing method of the semiconductor device provided by the embodiment of the invention, the pinning layer, the insulating layer, the free layer and the magnetoelectric layer are sequentially arranged from outside to inside through methods such as deposition, etching, filling and the like to form the 3D magnetoelectric magnetic tunnel junction, so that the manufacturing of the electronic device with high density, high speed and low power consumption is facilitated.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (13)
1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate and a plurality of laminated structures which are sequentially formed on the semiconductor substrate from bottom to top, wherein each laminated structure comprises a sacrificial layer and an isolation layer which are sequentially formed;
sequentially forming an insulating layer and a pinning layer on the semiconductor substrate to cover the semiconductor substrate and the plurality of laminated structures;
forming a middle cut cutting off the plurality of laminated structures and the insulating layer and the pinning layer positioned on the laminated structures;
etching and removing the sacrificial layer exposed in the middle cut to form a groove;
forming a free layer in the groove, and in the process of forming the free layer, etching and removing redundant materials deposited on the side wall and the bottom of the middle cut;
a magnetoelectric layer is formed in the central cutout.
2. The method of claim 1, wherein the material of the magnetoelectric layer comprises an antiferromagnetic material Cr2O3。
3. The method of claim 1, wherein the magnetoelectric layers are connected to word lines.
4. The method of claim 1, wherein the free layer connects bit lines.
5. The method of claim 1, wherein the sacrificial layer is removed using a wet etch.
6. The method of claim 1, wherein the sacrificial layer comprises a silicon nitride layer and the isolation layer comprises an oxide layer.
7. The method of claim 1, wherein the free layer and pinned layer are ferromagnetic materials.
8. The method of claim 1, wherein forming the central cutout further comprises forming a protective layer on the semiconductor substrate disposed around the stack of layers.
9. The method of claim 8, wherein the protective layer is removed after forming the magnetoelectric layer.
10. The method of claim 1, further comprising the step of forming an oxide dielectric layer disposed around the number of stacked structures on the semiconductor substrate after forming the magneto-electric layer.
11. The method of claim 10, further comprising the step of forming an interconnect layer on the oxide dielectric layer.
12. The method of claim 1, wherein the pinned layer, the insulating layer, the free layer, and the magneto-electric layer collectively form a 3D magneto-electric magnetic tunnel junction.
13. A semiconductor device formed by the manufacturing method according to any one of claims 1 to 12, comprising:
a semiconductor substrate;
a 3D magnetoelectric magnetic tunnel junction formed on a semiconductor substrate;
the 3D magnetoelectric magnetic tunnel junction includes: a pinning layer, an insulating layer, a free layer, and a magneto-electric layer.
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| CN102034829A (en) * | 2009-09-29 | 2011-04-27 | 三星电子株式会社 | Vertical-type non-volatile memory device and manufacture method |
| CN105845568A (en) * | 2015-01-12 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method therefor |
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| KR102140048B1 (en) * | 2014-02-18 | 2020-07-31 | 삼성전자주식회사 | Method for forming a magnetic tunnel junction structure for magentic memory device |
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