CN107908985B - PCB board-level protection method and structure for ensuring integrated circuit chip communication - Google Patents
PCB board-level protection method and structure for ensuring integrated circuit chip communication Download PDFInfo
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- CN107908985B CN107908985B CN201711002789.4A CN201711002789A CN107908985B CN 107908985 B CN107908985 B CN 107908985B CN 201711002789 A CN201711002789 A CN 201711002789A CN 107908985 B CN107908985 B CN 107908985B
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- 238000004891 communication Methods 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 title claims abstract description 10
- 238000004806 packaging method and process Methods 0.000 claims abstract description 6
- 238000001514 detection method Methods 0.000 claims abstract description 5
- 230000001681 protective effect Effects 0.000 claims description 2
- 230000002452 interceptive effect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 35
- 239000012528 membrane Substances 0.000 description 5
- 230000003993 interaction Effects 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000008447 perception Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/86—Secure or tamper-resistant housings
- G06F21/87—Secure or tamper-resistant housings by means of encapsulation, e.g. for integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Computer Security & Cryptography (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Storage Device Security (AREA)
- Pinball Game Machines (AREA)
Abstract
本发明涉及集成电路芯片安全防护领域，为提出一种适用于PCB板级的保护芯片间通信信息安全的防护方法与结构，防止攻击者直接接触通信走线，获取芯片间传输的密钥、关键数据等交互信息。本发明采用的技术方案是，保障集成电路芯片通信的PCB板级防护方法与结构，首先利用球状引脚栅格阵列封装BGA(Ball Grid Array)封装引脚处于芯片底部，使得攻击者无法直接接触芯片引脚，再利用多层印制电路板PCB的中间层进行重要数据通信，使得攻击者无法直接接触通信走线，同时，加入芯片防拆除检测，一旦通信芯片中一方被攻击者从PCB板上拆除，则立即终止通信。本发明主要应用于集成电路芯片安全防护。
The invention relates to the field of integrated circuit chip security protection, in order to propose a protection method and structure for protecting the security of communication information between chips, which is suitable for PCB board level, prevents attackers from directly contacting communication lines, and obtains keys and keys transmitted between chips. data and other interactive information. The technical scheme adopted in the present invention is that, for the PCB board-level protection method and structure for ensuring the communication of integrated circuit chips, firstly, the BGA (Ball Grid Array) packaging pins are used to package the pins at the bottom of the chip, so that attackers cannot directly contact them. Chip pins, and then use the middle layer of the multi-layer printed circuit board PCB to carry out important data communication, so that the attacker cannot directly contact the communication lines. At the same time, the chip anti-removal detection is added. removed, the communication is terminated immediately. The invention is mainly applied to the safety protection of integrated circuit chips.
Description
Technical Field
The invention relates to the field of integrated circuit chip safety protection, in particular to a safety protection method and a protection structure for communication information between chips on a PCB (printed circuit board) level.
Background
In recent years, information security has been receiving more and more attention. With the increasing functions of information systems, various information systems often carry various integrated circuit chips, passwords or key data often need to be transmitted among the integrated circuit chips, and the communication security among the chips often cannot be guaranteed at the PCB level, so that the security of the information systems is seriously threatened.
In order to ensure the security of communication between chips, chips requiring communication are often packaged together by using SIP packages, but the SIP packages have a large size, which virtually hinders the development of miniaturization of integrated circuit systems, and the SIP packages are expensive, so that the application range of the integrated circuit systems is limited.
In order to protect the communication safety of chips, the invention provides a PCB level protection method and a PCB level protection structure for ensuring the communication of integrated circuit chips.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a protection method and a structure which are suitable for protecting the safety of communication information between chips at a PCB level, so that an attacker is prevented from directly contacting communication routing and acquiring mutual information such as keys, key data and the like transmitted between the chips. The technical scheme adopted by the invention is that the PCB level protection method for ensuring the communication of the integrated circuit chip comprises the steps of firstly utilizing a Ball Grid Array (BGA) packaging pin to be positioned at the bottom of the chip so that an attacker cannot directly contact the chip pin, then utilizing the middle layer of a multilayer Printed Circuit Board (PCB) to carry out important data communication so that the attacker cannot directly contact communication wiring, simultaneously adding chip anti-removal detection, and immediately terminating the communication once one part of the communication chip is removed from the PCB by the attacker.
A PCB board-level protection structure for ensuring communication of an integrated circuit chip is characterized in that a protected chip selects a Ball Grid Array (BGA) packaging pin, a multi-layer Printed Circuit Board (PCB) middle layer on which the chip is supported and fixed is an important data communication wiring layer, and the chip is also provided with an anti-dismounting device.
The anti-dismantling device is characterized in that a sensing pin is arranged on a chip and is connected with a high level, and the high level of the sensing pin is pulled down to trigger communication interruption when the chip is dismantled.
The anti-dismounting device is characterized in that a thin-mode switch is arranged on the PCB, when the chip is normally connected to the PCB, the thin-mode switch below the chip is pressed, the thin-mode switch is closed, and a pin connected with the thin-mode switch is led in a high level; when the chip is detached, the thin-mode switch is in an off state, and a pin connected with the thin-mode switch is pulled down at a high level to trigger communication interruption.
The invention has the characteristics and beneficial effects that:
because the chips are packaged by BGA, and the important communication connecting wires among the chips are all positioned in the middle layer of the multilayer PCB, an attacker cannot contact pins and wires, and therefore communication information cannot be stolen. Also, if one of the communication chips is removed, the removal can be recognized as well to interrupt the communication. The protective layer is simple in structural principle, easy to implement, high in applicability of the protective method, low in cost and capable of guaranteeing communication safety, and extra packaging bodies are not needed.
Description of the drawings:
fig. 1 is a schematic cross-sectional view of a PCB board level guard structure.
Fig. 2 is a schematic cross-sectional view of a PCB-level guard structure with a membrane switch.
Detailed Description
According to the PCB level protection structure provided by the invention, firstly, the advantage that BGA (Ball Grid Array, spherical pin Grid Array package technology) package pins are positioned at the bottom of a chip is utilized, so that an attacker cannot directly contact the chip pins, then important data communication is carried out by utilizing the middle layers of a multilayer PCB, so that the attacker cannot directly contact communication wiring, meanwhile, chip removal prevention detection is added, and once one part of a communication chip is removed from the PCB by the attacker, communication is immediately terminated.
As shown in fig. 1, which is a schematic cross-sectional view of a PCB-level protection structure provided by the present invention, the structure mainly comprises a chip 1, a chip 2, and a PCB. Chip 1, chip 2 all adopt the BGA encapsulation, and the PCB board adopts the multilayer PCB board, and for the convenience of description, adopt four layers of PCB boards in the embodiment, actually can adopt the PCB board that is higher than four layers.
Pins 2 and 3 of the chip 1 are communication pins, and pins 4 and 5 are sensing pins. Pins 4 and 5 of the chip 2 are communication pins, and pins 2 and 3 are sensing pins. The communication pins are used for important data interaction between the chips, and the sensing pins are used for sensing whether the chips are detached from the PCB by an attacker or not. Four layers of PCBs are arranged from top to bottom, the first layer is a ground layer, and the layer is completely covered with copper and grounded and used for shielding attacks from the top layer, so that an attacker cannot identify the second layer of wiring. The second layer is a sensing layer and is used for communication between pins of sensing attack between chips. The third layer is a communication layer and is used for transmitting interactive data such as keys and key information among chips. The fourth layer is a ground layer, and the layer is completely covered with copper and grounded and is used for shielding the attack from the bottom layer, so that an attacker cannot identify the third layer of wiring.
Pin 2 of chip 1 links to each other with pin 5 of chip 2 through PCB board third layer communication layer, and pin 3 of chip 1 links to each other with pin 4 of chip 2 through PCB board third layer communication layer, and pin 4 of chip 1 links to each other with pin 3 of chip 2 through PCB board second layer perception layer, and pin 5 of chip 1 links to each other with pin 2 of chip 2 through PCB board second layer perception layer.
Pin 4 of chip 1 is in output state, and outputs high level, and pin 5 is in input state. Pin 2 of chip 2 is in output state, and outputs high level, and pin 3 is in input state. In normal operation, pin 5 of chip 1 inputs high level, and pin 3 of chip 2 also inputs high level. When the chip 1 and the chip 2 communicate, firstly, the input signal levels on the pin 5 and the pin 3 are respectively detected, if the input signal levels are high levels, the communication chip is in a normal state, the two chips can communicate, and at the moment, the pin 2 and the pin 3 of the chip 1 and the pin 4 and the pin 5 of the chip 2 can perform data interaction. Once the pin 5 of the chip 1 inputs a low level or the pin 3 of the chip 2 inputs a low level, which represents that one of the communication chips is removed from the PCB by an attacker, the data interaction between the chip 1 and the chip 2 is terminated immediately, i.e., the pin 2 and the pin 3 of the chip 1 and the pin 4 and the pin 5 of the chip 2 have no effective signal output.
For some chips that cannot provide sensing pins, the shielding layer structure shown in fig. 2 may be used. Chip 2 is the main control chip, and the communication between chip 1 and chip 2 is controlled by chip 2. A thin film switch with extremely thin thickness is arranged between the bottom surface of the chip 1 and the upper surface of the PCB, and when the chip 1 is welded and attached to the PCB, the thin film switch is pressed by the chip 1 to be closed, so that the thin film switch can be regarded as a lead. Pin 2 of chip 2 is connected with membrane switch right side pin, and pin 3 is connected with membrane switch left side pin. When the circuit works normally, the chip 1 and the chip 2 are connected with the PCB completely, and the film switch is closed. Pin 2 of chip 2 outputs high level, inputs pin 3 after the membrane switch, and pin 3 detects high level, and then both chips are in normal state, can communicate. Once the chip 1 is removed, the membrane switch has no external force and is in an off state, the input level of the pin 3 of the chip 2 is low level, and therefore the chip 1 is detected to be removed, and communication is immediately terminated. Once the chip 2 is removed, the pin 3 input level is low and communication is terminated.
As shown in fig. 1, the chip packages are selected to be BGA packages, sensing communication and important data communication are performed by using the intermediate layer of the multi-layer PCB, and all the upper and lower layers are copper-clad and grounded, respectively. The scope of the present invention is not limited to the above embodiments, and equivalent modifications or variations made by those skilled in the art according to the present disclosure should be included in the scope of the present invention.
Claims (3)
1. A PCB board level protection method for ensuring communication of an integrated circuit chip is characterized in that Ball Grid Array (BGA) packaging pins are positioned at the bottom of the chip, so that an attacker cannot directly contact the chip pins, important data communication is carried out by utilizing an intermediate layer of a multilayer Printed Circuit Board (PCB), so that the attacker cannot directly contact communication wiring, meanwhile, chip anti-removal detection is added, once one party of the communication chips is removed from the PCB by the attacker, communication is immediately terminated, wherein the anti-removal detection is specifically that a thin-mode switch is arranged on the PCB, when the chip is normally connected to the PCB, the thin-mode switch below the chip is pressed, the thin-mode switch is closed, and the pins connected with the thin-mode switch introduce high level; when the chip is detached, the thin-mode switch is in an off state, and a pin connected with the thin-mode switch is pulled down at a high level to trigger communication interruption.
2. A PCB board level protective structure for ensuring communication of an integrated circuit chip is characterized in that a protected chip selects a Ball Grid Array (BGA) packaging pin, an intermediate layer of a multilayer Printed Circuit Board (PCB) on which the chip is supported and fixed is an important data communication wiring layer, and the chip is also provided with an anti-dismounting device; the anti-dismounting device is characterized in that a thin-mode switch is arranged on the PCB, when the chip is normally connected to the PCB, the thin-mode switch below the chip is pressed, the thin-mode switch is closed, and a pin connected with the thin-mode switch is led in a high level; when the chip is detached, the thin-mode switch is in an off state, and a pin connected with the thin-mode switch is pulled down at a high level to trigger communication interruption.
3. The PCB level guard structure of claim 2, wherein the anti-removal device is specifically configured to set a sensing pin on the chip, the sensing pin is connected to a high level, and the sensing pin is pulled low at the high level to trigger the communication interruption when the chip is removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711002789.4A CN107908985B (en) | 2017-10-24 | 2017-10-24 | PCB board-level protection method and structure for ensuring integrated circuit chip communication |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711002789.4A CN107908985B (en) | 2017-10-24 | 2017-10-24 | PCB board-level protection method and structure for ensuring integrated circuit chip communication |
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| Publication Number | Publication Date |
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| CN107908985A CN107908985A (en) | 2018-04-13 |
| CN107908985B true CN107908985B (en) | 2021-03-16 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US11264361B2 (en) | 2019-06-05 | 2022-03-01 | Invensas Corporation | Network on layer enabled architectures |
| CN115630408B (en) * | 2022-12-21 | 2023-03-31 | 湖北工业大学 | A Secure Extraction Structure of PCB-Chip Hybrid Fingerprint |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7005742B2 (en) * | 2004-02-05 | 2006-02-28 | Texas Instruments Incorporated | Socket grid array |
| CN103136876B (en) * | 2012-12-31 | 2015-08-05 | 中国电子科技集团公司第十五研究所 | Anti-dismantle security card consumption machine |
| US9016552B2 (en) * | 2013-03-15 | 2015-04-28 | Sanmina Corporation | Method for forming interposers and stacked memory devices |
| CN104463313A (en) * | 2014-12-08 | 2015-03-25 | 重庆西南集成电路设计有限责任公司 | Ultrahigh frequency electronic tag with anti-dismantling protection function and anti-dismantling protection method |
| CN104883809B (en) * | 2015-05-15 | 2018-01-30 | 福建联迪商用设备有限公司 | A kind of guard method of pcb board secure line |
| CN204695317U (en) * | 2015-06-24 | 2015-10-07 | 福建联迪商用设备有限公司 | A kind of safety chip with Novel pin structure |
| CN106919861B (en) * | 2017-01-20 | 2020-04-03 | 大唐微电子技术有限公司 | Device and method for realizing anti-disassembly detection |
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- 2017-10-24 CN CN201711002789.4A patent/CN107908985B/en active Active
Non-Patent Citations (2)
| Title |
|---|
| JTAG-based robust PCB authentication for protection against counterfeiting attacks;Andrew Hennessy et al;《IEEE》;20160310;56-61 * |
| 安全终端的防拆机制设计;吴艳红;《广东技术师范学院学报》;20130731(第7期);第50-53页 * |
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