CN107808651A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN107808651A CN107808651A CN201711129697.2A CN201711129697A CN107808651A CN 107808651 A CN107808651 A CN 107808651A CN 201711129697 A CN201711129697 A CN 201711129697A CN 107808651 A CN107808651 A CN 107808651A
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- 101150061474 ckb-2 gene Proteins 0.000 description 7
- 238000005401 electroluminescence Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 6
- 230000005611 electricity Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
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- 210000001367 artery Anatomy 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
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- 235000008434 ginseng Nutrition 0.000 description 1
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- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
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- 230000003287 optical effect Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a display panel and a display device, wherein shift registers in a drive control circuit are grouped, the shift registers in each register group are in cascade arrangement, each register group is electrically connected with a plurality of adjacent drive signal lines, and different frame starting signal ends and different clock control signal ends are respectively arranged on each register group, so that each register group can be independently controlled to drive the electrically connected drive signal lines. When the display panel displays in the subareas, part of the register groups work independently, so that the areas corresponding to the working register groups are subjected to display driving, and the areas corresponding to the rest of the register groups are not subjected to display driving, so that the power consumption can be reduced. When the display panel displays the whole display, the register groups work sequentially to carry out the line-by-line display driving on the driving signal lines in the display panel, so that the display panel can realize the function of the whole display.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of display panel and display device.
Background technology
With the rapid development of Display Technique, display panel increasingly develops towards the direction of high integration and low cost.
Wherein, array base palte row drives (Gate Driver on Array, GOA) technology by thin film transistor (TFT) (Thin Film
Transistor, TFT) gate switch circuit is integrated on the array base palte of display panel and driven with forming scanning to display panel
It is dynamic, so as to save binding (Bonding) region of grid integrated circuits (Integrated Circuit, IC) and be fanned out to
(Fan-out) wiring space in region, not only product cost, Er Qieke can be reduced in material cost and the aspect of preparation technology two
So that display panel accomplishes that both sides are symmetrical and the design for aesthetic of narrow frame.
At present, in general gate driving circuit is made up of the shift register of multiple cascades, shift registers at different levels
A grid line is connected respectively, is realized from top to bottom successively to the grid line input scanning letter of connection by shift registers at different levels
Number to be progressively scanned, at the same source electrode drive circuit to pieces of data line load corresponding to data-signal, to complete display one
Individual picture.However, when display panel only needs to show the partial contents such as time, calendar, weather, because gate driving circuit needs
Progressive scan carried out to each grid line in display panel and carry out display driving, can just display panel is shown the above, lead
Cause power consumption increase.
The content of the invention
The embodiment of the present invention provides a kind of display panel and display device, to reduce the power consumption of display panel.
The embodiments of the invention provide a kind of display panel, the display panel includes：A plurality of drive signal line, and tool
There is the drive control circuit of multiple shift registers；Wherein, the shift register is divided into the M register group arranged successively,
Each register group correspondingly electrically connects adjacent a plurality of drive signal line；Each shift LD in each register group
Device cascade is set, and each shift register electrically connects with least one drive signal line；And each register
Group respectively from different frame start signal ends and the different corresponding connections in clock control signal end；M is the integer more than 1；
When being shown in the display panel subregion, in a vertical interval, the part in the M register group is posted
Storage group is used to work independently under the control of the frame start signal end of electrical connection and the signal at clock control signal end, to being electrically connected
The drive signal line connect drives line by line；Wherein, in addition to the component register group, the frame starting of remaining register group electrical connection
The signal of signal end is different from the signal at the frame start signal end that the component register group electrically connects；
When the display panel is integrally shown, in a vertical interval, each register group is used in electricity
Sequential working under the control of the frame start signal end of connection and the signal at clock control signal end, to the drive in the display panel
Dynamic signal wire drives line by line；Wherein, the sequential of the signal at the clock control signal end of each register group electrical connection is identical,
And in addition to first register group, the signal at the frame start signal end of remaining register group electrical connection and upper the one of arranged adjacent
The sequential of the signal of afterbody shift register output is identical in individual register group.
Correspondingly, the embodiment of the present invention additionally provides a kind of display device, including provided in an embodiment of the present invention above-mentioned aobvious
Show panel.
The present invention has the beneficial effect that：
Display panel provided in an embodiment of the present invention and display device, by the shift register in drive control circuit
Be grouped, shift register in each register group is set using cascade, and each register group electrically connect it is adjacent more
Bar drive signal line, and by setting different frame start signal ends and different clock controls respectively to each register group
Signal end, the drive signal line of electrical connection is driven so as to independent control each register group.Wherein, in display surface
When plate subregion is shown, by setting the signal at each frame start signal end and clock control signal end so that component register group
Work independently, so that region corresponding to the register group of work carries out display driving, without making area corresponding to remaining register group
Domain carries out display driving, so as to reduce power consumption.When display panel is integrally shown, by setting each frame start signal end
Signal with clock control signal end is so that each register group sequential working, is carried out line by line to the drive signal line in display panel
Display driving, so as to so that display panel realizes the function of integrally showing.
Brief description of the drawings
Fig. 1 is one of structural representation of display panel provided in an embodiment of the present invention；
Fig. 2 is the two of the structural representation of display panel provided in an embodiment of the present invention；
Fig. 3 is the three of the structural representation of display panel provided in an embodiment of the present invention；
Fig. 4 a are the four of the structural representation of display panel provided in an embodiment of the present invention；
Fig. 4 b are the five of the structural representation of display panel provided in an embodiment of the present invention；
Fig. 5 a are one of structural representation of shift register provided in an embodiment of the present invention；
Fig. 5 b are the two of the structural representation of shift register provided in an embodiment of the present invention；
Fig. 6 a are one of circuit timing diagram provided in an embodiment of the present invention；
Fig. 6 b are the two of circuit timing diagram provided in an embodiment of the present invention；
Fig. 7 is the concrete structure schematic diagram of display panel provided in an embodiment of the present invention；
Fig. 8 is the three of circuit timing diagram provided in an embodiment of the present invention；
Fig. 9 is one of structural representation of display device provided in an embodiment of the present invention；
Figure 10 is the two of the structural representation of display device provided in an embodiment of the present invention.
Embodiment
In order that the purpose of the present invention, technical scheme and advantage are clearer, below in conjunction with the accompanying drawings, to the embodiment of the present invention
The display panel of offer and the embodiment of display device are described in detail.It should be appreciated that disclosed below is excellent
Select embodiment to be merely to illustrate and explain the present invention, be not intended to limit the present invention.And in the case where not conflicting, the application
In embodiment and embodiment in feature can be mutually combined.
A kind of display panel provided in an embodiment of the present invention, as shown in Figure 1 to Figure 3, including：A plurality of drive signal line 100,
And the drive control circuit VSR with multiple shift registers；Wherein, shift register is divided into the M deposit arranged successively
(m is the integer more than or equal to 1 and less than or equal to M to device group VSR_m；Wherein, Fig. 1 and Fig. 2 is by taking M=2 as an example, and Fig. 3 is with M
Exemplified by=3), each register group VSR_m correspondingly electrically connects adjacent a plurality of drive signal line 100；Each register group VSR_m
In the cascade of each shift register set, and each shift register electrically connects with least one drive signal line 100；It is and every
Individual register group VSR_m is corresponding from different frame start signal end stv_m and different clock control signal end ckv_m respectively
Connection；M is the integer more than 1.
When being shown in display panel subregion, in a vertical interval, the component register group in M register group is used
Worked independently under the control in the frame start signal end of electrical connection and the signal at clock control signal end, the driving to electrical connection
Signal wire drives line by line；Wherein, in addition to component register group, the signal at the frame start signal end of remaining register group electrical connection
It is different from the signal at the frame start signal end of component register group electrical connection.
When display panel is integrally shown, in a vertical interval, each register group VSR_m is used for the frame in electrical connection
Sequential working under the control of initial signal end stv_m and clock control signal end ckv_m signal, to the driving in display panel
Signal wire 100 drives line by line；Wherein, the clock control signal end ckv_m of each register group VSR_m electrical connection signal when
Sequence is identical, i.e. the sequential of ck_m signal is identical, and the sequential of ckb_m signal is identical；And remove first register group VSR_1
Outside, last in the signal at frame start signal end and a upper register group for arranged adjacent of the electrical connection of remaining register group
The sequential of the signal of level shift register output is identical.
Display panel provided in an embodiment of the present invention, by being grouped to the shift register in drive control circuit,
Shift register in each register group is set using cascade, and each register group electrically connects adjacent a plurality of drive signal
Line, and by setting different frame start signal ends and different clock control signal ends respectively to each register group, with
The drive signal line of electrical connection can be driven with independent control each register group.Wherein, in display panel subregion
During display, by setting the signal at each frame start signal end and clock control signal end so that component register group independence work
Make, so that region corresponding to the register group of work carries out display driving, without carrying out region corresponding to remaining register group
Display driving, so as to reduce power consumption.When display panel is integrally shown, by setting each frame start signal end and clock
The signal of control signal end is so that each register group sequential working, carries out showing drive line by line to the drive signal line in display panel
It is dynamic, so as to so that display panel realizes the function of integrally showing.
In the specific implementation, display panel provided in an embodiment of the present invention can be liquid crystal display panel；Or can also
For electroluminescence display panel.Wherein, multiple pixel electrodes are typically provided with liquid crystal display panel, and with each pixel
The thin film transistor (TFT) of electrode connection.By thin film transistor (TFT) for pixel electrode provide display signal voltage, then with common electrical
The electric field driven liquid crystal molecule formed between common electric voltage on extremely deflects, and controls the transmitting or masking of light, so as to real
Existing display function.In electroluminescence display panel, be typically provided with multiple electroluminescent diodes and with each electroluminescent hair
The pixel-driving circuit of optical diode connection.It is provided with general pixel compensation circuit for controlling organic light-emitting diode
Light emitting control transistor and for control data signal input scan control transistor.In actual applications, pixel compensation
The concrete structure of circuit can be with having the pixel compensation of light emitting control transistor and scan control transistor electricity in the prior art
Road is identical, and therefore not to repeat here.
In the specific implementation, as shown in fig. 4 a, it is provided in an embodiment of the present invention when display panel is liquid crystal display panel
Drive signal line in display panel can include grid line gate, and drive control circuit can include gate driving circuit VSR_
GATE, so that the drive signal of shift register output is transferred to thin film transistor (TFT) by grid line gate, control thin film transistor (TFT)
Open and close.Wherein, the driving open signal in drive signal is used to control thin film transistor (TFT) to open, and drives shutdown signal
For controlling thin film transistor (TFT) to close.Also, in actual applications, while thin film transistor (TFT) is opened, in display panel
Source electrode drive circuit loads corresponding display signal to pieces of data line, so that pixel electrode write-in shows the voltage of signal, from
And display panel is set to complete to show a picture.The course of work of source electrode drive circuit can with of the prior art identical,
This is not repeated.Therefore, when being shown in subregion, the register group of autonomous working can control the grid line gate of its corresponding region
The thin film transistor (TFT) of connection is opened, and shows that signal is shown with input.And remaining register group not output driving open signal,
So as to open the thin film transistor (TFT) of the grid line gate connections of its corresponding region, input display signal is avoided, and then can be with
Shown the region, to save the power consumption of display panel.
In the specific implementation, as shown in Figure 4 b, when display panel is electroluminescence display panel, the embodiment of the present invention carries
Drive signal line in the display panel of confession can include LED control signal line emit, and drive control circuit can include luminous
Control circuit VSR_EMIT so that the drive signal of shift register output be transferred to by LED control signal line emit it is luminous
Controlling transistor, control the open and close of light emitting control transistor.Wherein, the driving open signal in drive signal is used to control
Light emitting control transistor processed is opened, and control driving transistor driving electroluminescent diode lights, and display panel is realized display
Function.Driving shutdown signal is used to control light emitting control transistor to close, to avoid driving transistor driving electroluminescent two pole
Pipe is luminous, so as to show display panel, and then further reduces power consumption.Therefore, when being shown in subregion, independent work
The register group of work can control the light emitting control transistor of its corresponding region to open, to realize display function.And remaining is deposited
Device group not output driving open signal, so as to which the display of its corresponding region will not be made to light, so as to save display panel
Power consumption.
Further, in the specific implementation, as shown in fig. 4 a, when display panel is electroluminescence display panel, this hair
Drive signal line in the display panel that bright embodiment provides can also include grid line gate, and drive control circuit can also include
Gate driving circuit VSR_GATE, so that the drive signal of shift register output is transferred to scan control crystalline substance by grid line gate
Body pipe, control the open and close of scan control transistor.Wherein, the driving open signal in drive signal is used to control and scanned
Controlling transistor is opened, and driving shutdown signal is used to control scan control transistor to close.Also, in actual applications, sweeping
While retouching controlling transistor unlatching, the source electrode drive circuit in display panel loads corresponding display letter to pieces of data line
Number, so that display panel is completed to show a picture.The course of work of source electrode drive circuit can with of the prior art identical,
Therefore not to repeat here.
In the specific implementation, in display panel provided in an embodiment of the present invention, each shifting in each register group
The cascade connection of bit register is：The input signal end of first order shift register is connected with corresponding frame start signal end；Remove
Outside first order shift register, upper level displacement adjacent thereto is posted respectively for the input signal end of remaining shift register at different levels
The output signal end of storage is connected.
In the specific implementation, in display panel provided in an embodiment of the present invention, as shown in Fig. 5 a and Fig. 5 b, shift LD
Device can include：First switch transistor M1, second switch transistor M2, the 3rd switching transistor M3, the 4th switching transistor
M4, the 5th switching transistor M5, the 6th switching transistor M6, the 7th switching transistor M7, the 8th switching transistor M8, the first electricity
Hold C1 and the second electric capacity C2.First switch transistor M1 control pole is connected with the first clock signal terminal CK, and first switch is brilliant
Body pipe M1 the first pole is connected with input signal end In, and first switch transistor M1 the second pole is connected with first node N1.The
Two switching transistor M2 control pole is connected with the first clock signal terminal CK, second switch transistor M2 the first pole and the first ginseng
Examine voltage signal end vref1 to be connected, second switch transistor M2 the second pole is connected with section point N2.3rd switching transistor
M3 control pole is connected with the first reference voltage signal end vref1, the 3rd switching transistor M3 the first pole and first node N1
It is connected, the 3rd switching transistor M3 the second pole is connected with the 3rd node N3.4th switching transistor M4 control pole and first
Node N1 is connected, and the 4th switching transistor M4 the first pole is connected with the first clock signal terminal CK, the 4th switching transistor M4's
Second pole is connected with section point N2.
5th switching transistor M5 control pole is connected with second clock signal end CKB, and the of the 5th switching transistor M5
One pole is extremely connected with the second of the 6th switching transistor M6, and the 5th switching transistor M5 the second pole is connected with first node N1.
6th switching transistor M6 control pole is connected with section point N2, and the 6th switching transistor M6 the first pole is with second with reference to electricity
Pressure signal end vref2 is connected.7th switching transistor M7 control pole is connected with the 3rd node N3, the 7th switching transistor M7's
First pole is connected with second clock signal end CKB, the 7th switching transistor M7 the second pole and the first shift register cell
Output signal end Out is connected.8th switching transistor M8 control pole is connected with section point N2, the 8th switching transistor M8's
First pole is connected with the second reference voltage signal end vref2, the 8th switching transistor M8 the second pole and the first shift register
The output signal end Out of unit is connected.First electric capacity C1 first end is connected with the 3rd node N3, the first electric capacity C1 the second end
It is connected with the output signal end Out of the first shift register cell.Second electric capacity C2 first end is connected with section point N2, the
Two electric capacity C2 the second end is connected with the second reference voltage signal end vref2.It the above is only the illustration embodiment of the present invention to carry
The concrete structure of the shift register of confession, in the specific implementation, the concrete structure of shift register are not limited to the embodiment of the present invention
The said structure of offer, can also be skilled person will appreciate that other structures, be not limited thereto.
In the specific implementation, in display panel provided in an embodiment of the present invention, as shown in Figure 5 a, above-mentioned each switch crystal
Pipe can be P-type transistor, and P-type transistor turns under the signal control of low potential, under the signal control of high potential
Cut-off.Or as shown in Figure 5 b, above-mentioned each switching transistor can also be N-type transistor, and N-type transistor is in high potential
Signal control it is lower turn on, end under the signal control of low potential.And the control of above-mentioned each switching transistor extremely its grid
Pole, according to the type of above-mentioned each switching transistor so that first extremely its source electrode, second extremely its drain, or, make the first pole
Drained for it, second extremely its source electrode, herein without distinguishing.
In actual applications, circuit timing diagram corresponding to the shift register shown in Fig. 5 a is Fig. 6 a, input signal end In
Corresponding effective impulse signal corresponds to clock signal ck, second clock for the pulse signal in, the first clock signal terminal CK of low potential
Signal end CKB corresponds to clock signal ckb, and output signal end Out corresponds to output drive signal out.Now, clock signal ck with
Efficient clock signals of the ckb within a clock cycle is low-potential signal within a clock cycle, a clock week
Low-potential signal in phase is used to produce the low-potential signal in drive signal out as driving open signal.However, inputting
When signal corresponding to signal end In is fixed high potential signal, the 7th transistor M7 is not turned on, so that output drive signal
Out is always maintained at exporting fixed high potential signal.
Circuit timing diagram corresponding to shift register shown in Fig. 5 b is Fig. 6 b, and input signal end In corresponds to effective impulse letter
Number for high potential pulse signal in, the first clock signal terminal CK correspond to clock signal ck, second clock signal end CKB to correspondence when
Clock signal ckb, output signal end Out correspond to output drive signal out.Now, clock signal ck and ckb is in a clock cycle
Interior efficient clock signal is the high potential signal within a clock cycle, and the high potential signal in a clock cycle is used
In produce in drive signal out as driving open signal high potential signal.However, in signal corresponding to the In of input signal end
During to fix low-potential signal, the 7th transistor M7 is not turned on, so that output drive signal out is always maintained at output and fixed
Low-potential signal.The course of work of above-mentioned two shift register and the course of work of the prior art are essentially identical, are ability
The those of ordinary skill in domain should be appreciated that what is had, and therefore not to repeat here, also should not be limiting for the invention.
In the specific implementation, the structure of the shift register in display panel provided in an embodiment of the present invention such as Fig. 5 a or
When shown in Fig. 5 b, with reference to Fig. 1 to Fig. 3, clock control signal end ckv_m corresponding to a register group VSR_m can include two
Individual clock control subsignal end：Ck_m and ckb_m.The clock signal terminal of each shift register in register group VSR_m with
Annexation between corresponding clock control subsignal end can be：First clock signal terminal of 2c-1 level shift registers
The second clock signal end CKB of CK and 2c level shift registers is connected with same clock control subsignal end ck_m, the
First clock signal terminal CK of second clock signal end CKB and 2c the level shift register of 2c-1 level shift registers with together
One clock control subsignal end ckb_m is connected, and c is positive integer.
In the specific implementation, in display panel provided in an embodiment of the present invention, as shown in Figure 5 a, shift register includes
Multiple P-type transistors, in order that the shift register in register group realizes displacement output services successively, as shown in Figure 6 a, should
The frame start signal end of register group electrical connection can load the pulse signal in that effective impulse signal is low potential.Also, should
The clock control subsignal end of register group electrical connection can load clock signal ck and ckb respectively.However, in order to avoid deposit
Shift register output driving open signal in device group, the frame start signal end of register group electrical connection can load fixation
High potential signal, to avoid the P-type transistor in shift register from opening.Therefore, in the specific implementation, shown in subregion
When, the frame start signal end of the component register group electrical connection of work can correspond to the arteries and veins that loading effective impulse signal is low potential
Signal is rushed, so that the component register group can be with normal work to drive drive signal line.And in addition to component register group, its
The frame start signal end of remaining register group electrical connection can load fixed high potential signal, so that the remainder register group
It can avoid driving drive signal line.
In the specific implementation, in display panel provided in an embodiment of the present invention, it is brilliant to include multiple p-types in shift register
Body pipe, and the frame start signal end of remaining register group electrical connection is when loading fixed high potential signal, remaining register group
The clock control signal end of electrical connection can load fixed high potential signal.So can frame corresponding with remaining register group
Initial signal end is uniformly controlled.Certainly, the clock control signal end of remaining register group electrical connection can also load and work
The electrical connection of component register group clock control signal end identical signal, it is dry between clock control signal line to reduce
Disturb.
In the specific implementation, in display panel provided in an embodiment of the present invention, as shown in Figure 5 b, shift register includes
Multiple N-type transistors, in order that the shift register in register group realizes displacement output services successively, as shown in Figure 6 b, should
The frame start signal end of register group electrical connection can load the pulse signal in that effective impulse signal is high potential.Also, should
The clock control subsignal end of register group electrical connection can load clock signal ck and ckb respectively.However, in order to avoid deposit
Shift register output driving open signal in device group, the frame start signal end of register group electrical connection can load fixation
Low-potential signal, to avoid the N-type transistor in shift register from opening.Therefore, in the specific implementation, shown in subregion
When, the frame start signal end of component register group electrical connection can correspond to loading effective impulse signal and believe for the pulse of high potential
Number, so that the component register group can be with normal work to drive drive signal line.And in addition to component register group, remaining is posted
The frame start signal end of storage group electrical connection can load fixed low-potential signal, so that the remainder register group can be with
Avoid driving drive signal line.
In the specific implementation, in display panel provided in an embodiment of the present invention, it is brilliant to include multiple N-types in shift register
Body pipe, and the frame start signal end of remaining register group electrical connection is when loading fixed low-potential signal, remaining register group
The clock control signal end of electrical connection can load fixed low-potential signal.So can frame corresponding with remaining register group
Initial signal end is uniformly controlled.Certainly, the clock control signal end of remaining register group electrical connection can also load and work
The electrical connection of component register group clock control signal end identical signal, it is dry between clock control signal line to reduce
Disturb.
In the specific implementation, in display panel provided in an embodiment of the present invention, shift register can be divided into successively
2 register groups of arrangement, i.e. M=2, can so make display panel be divided to two regions to be driven display.Or it can incite somebody to action
Shift register is divided into the 3 register groups arranged successively, i.e. M=3, three regions of display panel point can so driven
Dynamic display.It is of course also possible to which shift register to be divided into arrange successively 4,5 ... individual register groups, display panel point can be made
Multiple regions are driven display.In actual applications, M numerical value needs to be determined to design according to actual application environment, herein
It is not construed as limiting.
Separately below by taking M=2 and M=3 as an example, display panel provided in an embodiment of the present invention is illustrated.Under also,
Face is so that shift register includes P-type transistor as an example.
Embodiment one,
By taking M=2 as an example, display panel is conventionally arranged for the pixel of display, and drive signal line prolongs along the line direction of pixel
Stretch.In the specific implementation, in display panel provided in an embodiment of the present invention, as shown in fig. 7, display panel can be divided into two
Region, it is respectively：First area aa_1 and second area aa_2.The 1st register group VSR_1 in this 2 register groups is used
In driving the drive signal line 100 that is located in the aa_1 of first area, so that drive signal line 100 in the aa_1 of first area can be with
Driven.2nd register group VSR_2 is used to drive the drive signal line 100 being located in second area aa_2, so that the secondth area
Drive signal line 100 in the aa_2 of domain can be driven.
General display panel can use the mode of bilateral driving to realize driving function, in the specific implementation, in this hair
In the display panel that bright embodiment provides, each shift register can include being respectively arranged at same drive signal line both ends
Left side shift register and right side shift register；And when shift register works, positioned at same drive signal line both ends
Left side shift register and right side shift register work simultaneously.Display panel can be so set to realize the work(of bilateral driving
Energy.Specifically, as shown in Fig. 1 and Fig. 2 and Fig. 6, by taking shift register SR1_1 as an example, shift register SR1_1 includes being located at
Drive the left side shift register SR1_1a and right side shift register SR1_1b of the drive signal line 100 with one-row pixels.Its
The specific setting of remaining shift register is referred to shift register SR1_1 setting, and therefore not to repeat here.
General display panel sets pixel and drive signal line, in the specific implementation, the embodiment of the present invention using substrate
The display panel of offer can also include the substrate for setting drive signal line.The substrate can be glass substrate, flexible base board, silicon
Substrate etc., is not limited thereto.When display panel applications are into display device, the devices such as camera, receiver typically can be also set
Part, therefore in order to set the devices such as camera, receiver, in the specific implementation, as shown in fig. 7, provided in an embodiment of the present invention aobvious
The first subregion aa_11, the second subregion aa_12 can be included and be spaced apart the first son by showing the first area aa_1 of panel
Region aa_11 and the second subregion aa_12 the 3rd subregion aa_13.So can be in the 3rd subregion aa_13 region
The devices such as camera, receiver are set.In actual applications, the 3rd subregion aa_13 can be engraving for the substrate in display panel
Dummy section.In actual fabrication process, by the way that the 3rd subregion aa_13 of the substrate is cut away, so that the 3rd subregion aa_
13 turn into void region, for setting the devices such as camera, receiver in a display device.Certainly, the 3rd subregion aa_13
And the cover sheet as devices such as camera, receivers can be used for without cutting, now, the 3rd subregion aa_13 can be with
It is arranged to non-void region.However, in order that these proper device operations, the non-void region could be arranged to transparent display
Region or non-display area.Certainly, the 3rd subregion aa_13 of display panel specific setting needs the reality according to display panel
Border application environment determines to set, and is not limited thereto.
Due to the 3rd subregion aa_13 interval action, in the specific implementation, as shown in fig. 7, the same a line of driving can be made
The drive signal line 100 of pixel directly disconnects；Wherein, one end of the drive signal line 100 in the first subregion aa_11 connects
Left side shift register SRq_1a (Q of q=1,2,3 ...) is met, the other end extends to the first subregion aa_11 close to the 3rd subregion
Aa_13 edge, to use left side shift register SRq_1a to drive the drive signal line 100 in the first subregion aa_11.Position
One end connection right side shift register SRq_1b of drive signal line 100 in the second subregion aa_12, the other end extend to
Second subregion aa_12 is close to the 3rd subregion aa_13 edge, to use the second son of right side shift register SRq_1b drivings
Drive signal line 100 in the aa_12 of region.It is of course also possible to make driving with the drive signal line of one-row pixels along the first sub-district
Domain sets respectively close to the edge of the 3rd subregion with the second subregion and electrically connected with realizing.
At present, display panel is refreshed under the refreshing frequency of certain frequency, realizes image display function.Specific real
Shi Shi, the refreshing frequency of display panel provided in an embodiment of the present invention can be AHz.A general shift register drives one
Drive signal line is to control the display of one-row pixels and closing.As shown in fig. 7, the 1st register group VSR_1 can include Q
Shift register SRq_1, when being shown in display panel subregion, when the 1st register group VSR_1 works, i.e. first area
When aa_1 is shown, the efficient clock of the clock control signal end of the 1st register group VSR_1 electrical connection within a clock cycle
The duration of signal could be arranged toFor example, clock control subsignal end ck_1 and ckb_1 clock signal are in a clock
The duration of efficient clock signal in cycle could be arranged toBecause clock control signal end is within a clock cycle
The duration of the driving open signal of efficient clock signal corresponding displaced register output, therefore, in a vertical interval only
During the 1st register group VSR_1 work, by the way that a vertical interval is averagely assigned into each shift register SRq_1, it can make
The duration growth of the driving open signal of each shift register SRq_1 output, during so as to improve the unlatching of one-row pixels
It is long, and then make data-signal write-in abundant.For example, during A=60, the driving open signal of each shift register SRq_1 outputs
Duration can be：
Similarly, as shown in fig. 7, the 2nd register group VSR_2 can include K shift register SRk_2 (k=1,2,
3…K)；When being shown in subregion, when the 2nd register group works, i.e. when second area aa_2 is shown, the 2nd register group
Efficient clock signal of the clock control signal end within a clock cycle of VSR_2 electrical connections when it is a length ofFor example, A=
When 60, the duration of the driving commencing signal of each shift register SRk_2 outputs can be：
In the specific implementation, when display panel provided in an embodiment of the present invention is liquid crystal display panel, drive signal line
Grid line can be included, drive control circuit can include gate driving circuit.As shown in fig. 7, when being shown in subregion, wherein,
In first area, aa_1 is shown, and when second area aa_2 is not shown, frame start signal end stv_1 can be with the letter in corresponding diagram 6a
Number in.Clock control subsignal end ck_1, ckb_1 can distinguish ck, ckb in corresponding diagram 6a.The 1st deposit can so be made
The frame start signal end stv_1 that device group VSR_1 is electrically connected at it and clock control signal end (including clock control subsignal end
Ck_1 and ckb_1) signal control under work, with output drive signal, drive the grid line in the aa_1 of first area, make first
Pixel electrode write-in in the aa_1 of region shows the voltage of signal, and by coordinating with the common electric voltage on public electrode, realizes
Display function.Frame start signal end stv_2 corresponding to 2nd register group VSR_2 can load high potential signal, with its electricity
The frame start signal end stv_2 of connection and the letter at clock control signal end (including clock control subsignal end ck_2 and ckb_2)
Number control under not output drive signal, to avoid making the pixel electrode write-in in second area aa_2 from showing the voltage of signal,
So as to avoid second area aa_2 from showing, and then reduce the power consumption of display panel.In first area, aa_1 is not shown, and the
When two region aa_2 are shown, the operation principle of display panel is with above-mentioned essentially identical, and therefore not to repeat here.When integrally showing,
1st register group VSR_1 and the 2nd register group VSR_2 sequential working, to be progressively scanned to the grid line in display panel.
Now, frame start signal end stv_1 and stv_2 can distinguish the signal stv1 and stv2 in corresponding diagram 8.Clock control subsignal
End ck_1, ckb_1, ck_2, ckb_2 can distinguish ck1, ckb1, ck2, ckb2 in corresponding diagram 8.
In the specific implementation, when display panel provided in an embodiment of the present invention is electroluminescence display panel, driving letter
Number line can include LED control signal line, and drive control circuit can include emission control circuit.As shown in fig. 7, in subregion
When domain is shown, wherein, in first area, aa_1 is shown, and when second area aa_2 is not shown, frame start signal end stv_1 can be with
Signal in corresponding diagram 6a.Clock control subsignal end ck_1, ckb_1 can distinguish ck, ckb in corresponding diagram 6a.So
Can make the 1st register group VSR_1 in emission control circuit the frame start signal end stv_1 that it is electrically connected with when clock
Work under the control of the signal of signal end (including clock control subsignal end ck_1 and ckb_1) processed, with output drive signal, drive
LED control signal line in dynamic first area aa_1, makes the electroluminescent diode in the aa_1 of first area light, and realizes aobvious
Show function.Frame start signal end stv_2 corresponding to 2nd register group VSR_2 can load high potential signal, to be electrically connected at it
The frame start signal end stv_2 connect and the signal at clock control signal end (including clock control subsignal end ck_2 and ckb_2)
Control under not output drive signal, to avoid making the electroluminescent diode in second area aa_2 light, so as to keep away
Exempt from second area aa_2 to show, and then reduce the power consumption of display panel.In first area, aa_1 is not shown, and second area aa_2
During display, the operation principle of display panel is with above-mentioned essentially identical, and therefore not to repeat here.When integrally showing, the 1st register
VSR_1 and the 2nd register group VSR_2 sequential working of group, to be driven line by line to the LED control signal line in display panel.This
When, frame start signal end stv_1 and stv_2 can distinguish signal stv1 and stv2 in corresponding diagram 8.Clock control subsignal end
Ck_1, ckb_1, ck_2, ckb_2 can distinguish ck1, ckb1, ck2, ckb2 in corresponding diagram 8.
Further, similarly, when display panel is electroluminescence display panel, display surface provided in an embodiment of the present invention
Drive signal line in plate can also include grid line, and drive control circuit can also include gate driving circuit.In first area
Aa_1 shows, and when second area aa_2 is not shown, the 1st register group VSR_1 in gate driving circuit electrically connects at it
Frame start signal end stv_1 and clock control signal end (including clock control subsignal end ck_1 and ckb_1) signal
Control is lower to work, and with output drive signal, drives the grid line in the aa_1 of first area to make first area to write display signal
Electroluminescent diode in aa_1 lights, and realizes display function.The frame starting that 2nd register group VSR_2 electrically connects at it
Under the control of signal end stv_2 and the signal at clock control signal end (including clock control subsignal end ck_2 and ckb_2) not
Output drive signal, to avoid write-in from showing signal.In first area, aa_1 is not shown, and during second area aa_2 displays, show
Show the operation principle of panel with above-mentioned essentially identical, therefore not to repeat here.
Embodiment two,
By taking M=3 as an example, in the specific implementation, in display panel provided in an embodiment of the present invention, as shown in figure 3, display
Panel can be divided into three regions, be respectively：First area aa_1, second area aa_2 and the 3rd region A_3.This 3 are posted
The 1st register group VSR_1 in storage group is used to drive the drive signal line 100 being located in the aa_1 of first area, so that the
Drive signal line 100 in one region aa_1 can be driven.2nd register group VSR_2, which is used to drive, is located at second area
Drive signal line 100 in aa_2, so that the drive signal line 100 in second area aa_2 can be driven.3rd register
Group VSR_3 is used to drive the drive signal line 100 being located in the 3rd region A_3, so that the drive signal line in the 3rd region A_3
100 can be driven.
General display panel can use the mode of bilateral driving to realize driving function, in the specific implementation, in this hair
In the display panel that bright embodiment provides, each shift register can include being respectively arranged at same drive signal line both ends
Left side shift register and right side shift register；And when shift register works, positioned at same drive signal line both ends
Left side shift register and right side shift register work simultaneously.Display panel can be so set to realize the work(of bilateral driving
Energy.Specifically, as shown in figure 3, by taking shift register SR1_1 as an example, shift register SR1_1 is included positioned at driving with a line picture
The left side shift register SR1_1a and right side shift register SR1_1b of the drive signal line 100 of element.Remaining shift register
Specific setting be referred to shift register SR1_1 setting, therefore not to repeat here.
In the specific implementation, as shown in figure 3, the first area aa_1 of display panel provided in an embodiment of the present invention can be wrapped
Include the first subregion aa_11, the second subregion aa_12 and be spaced apart the first subregion aa_11 and the second subregion aa_12
The 3rd subregion aa_13.3rd subregion aa_13 specific setting may refer to embodiment one, and therefore not to repeat here.
Due to the 3rd subregion aa_13 interval action, in the specific implementation, as shown in figure 3, the same a line of driving can be made
The drive signal line 100 of pixel directly disconnects；Wherein, one end of the drive signal line 100 in the first subregion aa_11 connects
Left side shift register SRx_1a (X of x=1,2,3 ...) is met, the other end extends to the first subregion aa_11 close to the 3rd subregion
Aa_13 edge, to use left side shift register SRx_1a to drive the drive signal line 100 in the first subregion aa_11.Position
One end connection right side shift register SRx_1b of drive signal line 100 in the second subregion aa_12, the other end extend to
Second subregion aa_12 is close to the 3rd subregion aa_13 edge, to use the second son of right side shift register SRx_1b drivings
Drive signal line 100 in the aa_12 of region.It is of course also possible to make driving with the drive signal line of one-row pixels along the first sub-district
Domain sets respectively close to the edge of the 3rd subregion with the second subregion and electrically connected with realizing.
In the specific implementation, the refreshing frequency of display panel provided in an embodiment of the present invention can be B Hz.General one
Shift register drives a drive signal line to control the display of one-row pixels and closing.As shown in figure 3, the 1st register
Group VSR_1 can include X shift register SRx_1, when being shown in display panel subregion, as the 1st register group VSR_1
During work, i.e. when first area aa_1 is shown, the clock control signal end of the 1st register group VSR_1 electrical connection is at one
The duration of efficient clock signal in the clock cycle could be arranged toFor example, clock control subsignal end ck_1 and ckb_1 when
The duration of efficient clock signal of the clock signal within a clock cycle could be arranged toBecause clock control signal end is one
The duration of the driving open signal of efficient clock signal corresponding displaced register output in the individual clock cycle, therefore, in a frame
In sweep time during only the 1st register group VSR_1 work, by the way that a vertical interval is averagely assigned into each shift LD
Device SRx_1, it can increase the duration of the driving open signal of each shift register SRx_1 outputs, so as to improve one
The opening time of row pixel, and then make data-signal write-in abundant.For example, during B=60, each shift register SRx_1 outputs
The duration of driving open signal can be：
Similarly, as shown in figure 3, the 2nd register group VSR_2 can include Y shift register SRy_2 (y=1,2,
3…Y)；When being shown in subregion, when the 2nd register group VSR_2 works, i.e. when second area aa_2 is shown, the 2nd is posted
Efficient clock signal of the clock control signal end within a clock cycle of storage group VSR_2 electrical connections when it is a length ofExample
Such as, during B=60, the duration of the driving commencing signal of each shift register SRy_2 outputs can be：
Similarly, as shown in figure 3, the 3rd register group VSR_3 can include Z shift register SRz_3 (z=1,2,
3…Z)；When being shown in subregion, when the 3rd register group VSR_3 works, i.e. when the 3rd region aa_3 is shown, the 3rd is posted
Efficient clock signal of the clock control signal end within a clock cycle of storage group VSR_3 electrical connections when it is a length ofExample
Such as, during B=60, the duration of the driving commencing signal of each shift register SRz_3 outputs can be：
In the specific implementation, when display panel provided in an embodiment of the present invention is liquid crystal display panel, drive signal line
Grid line can be included, drive control circuit can include gate driving circuit.Shown in display panel subregion and overall aobvious
Course of work when showing may be referred to the course of work in embodiment one, and therefore not to repeat here.
In the specific implementation, when display panel provided in an embodiment of the present invention is electroluminescence display panel, driving letter
Number line can include LED control signal line, and drive control circuit can include emission control circuit.In display panel subregion
Course of work when display and overall display may be referred to the course of work in embodiment one, and therefore not to repeat here.Further
Ground, the drive signal line in display panel provided in an embodiment of the present invention can also include grid line, and drive control circuit can be with
Including gate driving circuit.Also, course of work when showing in display panel subregion and integrally showing may be referred to reality
The course of work in example one is applied, therefore not to repeat here.
Based on same inventive concept, the embodiment of the present invention additionally provides a kind of display device, including the embodiment of the present invention carries
The above-mentioned display panel supplied.The implementation of the display device may refer to the embodiment of above-mentioned display panel, and it is no longer superfluous to repeat part
State.
In the specific implementation, display device provided in an embodiment of the present invention can be comprehensive screen as shown in Figures 9 and 10
Mobile phone.Wherein, in the mobile phone shown in Fig. 9, display panel has the 3rd subregion a13, can in the 3rd subregion a13
To set it in camera, receiver, light sensor, range sensor, iris recognition sensor and fingerprint Identification sensor
One or combination.It is, of course, also possible to above-mentioned device is arranged on to the other positions of mobile phone, such as the side or the back side of mobile phone center,
Now display panel can be not provided with the 3rd subregion a13, i.e., comprehensive screen mobile phone as shown in Figure 10.Certainly, the present invention is implemented
The display device that example provides can also be thought：Tablet personal computer, television set, display, notebook computer, DPF, navigator etc.
Any product or part with display function.Other essential parts for the display device are this area
Those of ordinary skill should be appreciated that what is had, will not be described here, also should not be taken as limiting the invention.
Display panel provided in an embodiment of the present invention and display device, by the shift register in drive control circuit
Be grouped, shift register in each register group is set using cascade, and each register group electrically connect it is adjacent more
Bar drive signal line, and by setting different frame start signal ends and different clock controls respectively to each register group
Signal end, the drive signal line of electrical connection is driven so as to independent control each register group.Wherein, in display surface
When plate subregion is shown, by setting the signal at each frame start signal end and clock control signal end so that component register group
Work independently, so that region corresponding to the register group of work carries out display driving, without making area corresponding to remaining register group
Domain carries out display driving, so as to reduce power consumption.When display panel is integrally shown, by setting each frame start signal end
Signal with clock control signal end is so that each register group sequential working, is carried out line by line to the drive signal line in display panel
Display driving, so as to so that display panel realizes the function of integrally showing.
Obviously, those skilled in the art can carry out the essence of various changes and modification without departing from the present invention to the present invention
God and scope.So, if these modifications and variations of the present invention belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these changes and modification.
Claims (13)
1. a kind of display panel, it is characterised in that the display panel includes：A plurality of drive signal line, and there are multiple shiftings
The drive control circuit of bit register；Wherein, the shift register is divided into the M register group arranged successively, each described
Register group correspondingly electrically connects adjacent a plurality of drive signal line；Each shift register cascade in each register group is set
Put, and each shift register electrically connects with least one drive signal line；And each register group respectively with
Different frame start signal ends and the different corresponding connections in clock control signal end；M is the integer more than 1；
When being shown in the display panel subregion, in a vertical interval, the component register in the M register group
Group is used to work independently under the control of the frame start signal end of electrical connection and the signal at clock control signal end, to electrical connection
Drive signal line drives line by line；Wherein, in addition to the component register group, the frame start signal of remaining register group electrical connection
The signal at end is different from the signal at the frame start signal end that the component register group electrically connects；
When the display panel is integrally shown, in a vertical interval, each register group is used to electrically connect
Frame start signal end and clock control signal end signal control under sequential working, in the display panel driving believe
Number line drives line by line；Wherein, the sequential of the signal at the clock control signal end of each register group electrical connection is identical, and removes
Outside first register group, the signal at frame start signal end of remaining register group electrical connection and upper one of arranged adjacent post
The sequential of the signal of afterbody shift register output is identical in storage group.
2. display panel as claimed in claim 1, it is characterised in that the display panel is divided into first area and the secondth area
Domain；
M=2, wherein, the 1st register group in 2 register groups is used to drive the drive being located in the first area
Dynamic signal wire；2nd register group is used to drive the drive signal line being located in the second area.
3. display panel as claimed in claim 1, it is characterised in that the 1st register group includes Q shift LD
Device, the 2nd register group include K shift register；The refreshing frequency of the display panel is A Hz；
When being shown in the subregion, when the 1st register group works, the 1st register group electrical connection when
Efficient clock signal of the clock control signal end within a clock cycle when it is a length of
When being shown in the subregion, when the 2nd register group works, the 2nd register group electrical connection when
Efficient clock signal of the clock control signal end within a clock cycle when it is a length of
4. display panel as claimed in claim 1, it is characterised in that the display panel is divided into first area, second area
And the 3rd region；
M=3, wherein, the 1st register group in 3 register groups is used to drive the drive being located in the first area
Dynamic signal wire；2nd register group is used to drive the drive signal line being located in the second area；3rd register group is used
It is located at the drive signal line in the 3rd region in driving.
5. display panel as claimed in claim 4, it is characterised in that the 1st register group includes X shift LD
Device, the 2nd register group include Y shift register, and the 3rd register group includes Z shift register；It is described
The refreshing frequency of display panel is B Hz；
When being shown in the subregion, when the 1st register group works, the 1st register group electrical connection when
Efficient clock signal of the clock control signal end within a clock cycle when it is a length of
When being shown in the subregion, when the 2nd register group works, the 2nd register group electrical connection when
Efficient clock signal of the clock control signal end within a clock cycle when it is a length of
When being shown in the subregion, when the 3rd register group works, the 3rd register group electrical connection when
Efficient clock signal of the clock control signal end within a clock cycle when it is a length of
6. display panel as claimed in claim 1, it is characterised in that the shift register includes multiple P-type transistors；
When being shown in the subregion, the frame start signal end of the component register group electrical connection correspondingly loads effective impulse letter
Number be low potential pulse signal；In addition to the component register group, the frame start signal end of remaining register group electrical connection
Load fixed high potential signal.
7. display panel as claimed in claim 6, it is characterised in that the clock control letter of remaining register group electrical connection
Number end loads fixed high potential signal.
8. display panel as claimed in claim 1, it is characterised in that the shift register includes multiple N-type transistors；
When being shown in the subregion, the frame start signal end of the component register group electrical connection correspondingly loads effective impulse letter
Number be high potential pulse signal；In addition to the component register group, the frame start signal end of remaining register group electrical connection
Load fixed low-potential signal.
9. display panel as claimed in claim 8, it is characterised in that the clock control letter of remaining register group electrical connection
Number end loads fixed low-potential signal.
10. the display panel as described in claim any one of 1-9, it is characterised in that the drive signal line includes grid line, institute
Stating drive control circuit includes gate driving circuit.
11. the display panel as described in claim any one of 1-9, it is characterised in that the drive signal line includes luminous control
Signal wire processed, the drive control circuit include emission control circuit.
12. the display panel as described in claim any one of 1-9, it is characterised in that each shift register includes setting respectively
It is placed in the left side shift register and right side shift register at same drive signal line both ends；And in the shift register work
When making, left side shift register and right side shift register positioned at same drive signal line both ends work simultaneously.
13. a kind of display device, it is characterised in that including the display panel as described in claim any one of 1-12.
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