CN107768320A - Electronic packing piece and its preparation method - Google Patents
Electronic packing piece and its preparation method Download PDFInfo
- Publication number
- CN107768320A CN107768320A CN201610686258.0A CN201610686258A CN107768320A CN 107768320 A CN107768320 A CN 107768320A CN 201610686258 A CN201610686258 A CN 201610686258A CN 107768320 A CN107768320 A CN 107768320A
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- Prior art keywords
- insulating barrier
- electronic
- packing piece
- conductive
- preparation
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention discloses a kind of electronic packing piece and its preparation method, the electronic packing piece includes insulating barrier, the electronic component being embedded into the insulation and conductive projection and is formed on the insulating barrier and is electrically connected with the line construction of the conductive projection, avoid the plate body using known package substrate, to reduce the integral thickness of the electronic packing piece, meets the needs of lightening.
Description
Technical field
The present invention relates to a kind of semiconductor packaging, more particularly to a kind of electronic packing piece and its preparation method.
Background technology
With the evolution of semiconductor packaging, semiconductor device (Semiconductor device) has developed difference
Encapsulation kenel, it is another for lifting electrical functionality and to save encapsulated space, develop flip (flip chip) technology then.
Fig. 1 is the diagrammatic cross-section of known semiconductor packaging part 1.As shown in figure 1, the preparation method of the semiconductor package part 1 is first
There is provided one has plate body 10a and line construction 10b a package substrate 10, then by flip mode combination semiconductor element 11 in
On line construction 10b, formed afterwards packing colloid 13 on the package substrate 10 to coat the semiconductor element 11.
Specifically, there is the semiconductor element 11 relative acting surface 11a and non-active face 11b, acting surface 11a to have
Multiple electrode pads 110, to pass through multiple circuits that the electronic pads 110 and line construction 10b are electrically connected with such as solder bump 12
Layer 100, and the packing colloid 13 is also formed between the semiconductor element 11 and the package substrate 10, it is convex to coat above-mentioned scolding tin
Block 12.
It is well known, however, that in the processing procedure of semiconductor package part 1, when the semiconductor element 11 is large scale or high pin number
When (high pin count), the flowing of the packing colloid 13 is not easy to fill up between the semiconductor element 11 and the package substrate 10
Space, cause between the semiconductor element 11 and the package substrate 10 produce cavity (void) 14, therefore in subsequent cure this
During packing colloid 13, popcorn effect (popcorn effect) easily occurs for the cavity 14, causes under product yield
Drop.
Furthermore it is known that in semiconductor package part 1, because the package substrate 10 has plate body 10a, cause the semiconductor packages
The integral thickness of part 1 is difficult to effectively reduce, and can not meet the needs of electronic product is lightening now.
Therefore, the defects of how overcoming prior art, actually current all circles desire most ardently the technical problem of solution.
The content of the invention
In view of the defects of above-mentioned prior art, the present invention provides a kind of electronic packing piece and its preparation method, to reduce the electronics
The integral thickness of packaging part, meets the needs of lightening.
The electronic packing piece of the present invention includes：Insulating barrier；The electronic component of multiple conductive projections is combined with, it is embedded into this
In insulating barrier, and the part surface of the conductive projection is made to expose to the insulating barrier；And line construction, it is formed at the insulating barrier
And the conductive projection exposes on the part surface of the insulating barrier and is electrically connected with the conductive projection.
The present invention also provides a kind of preparation method of electronic packing piece, and it comprises the following steps：One is set to be combined with multiple conductions
The electronic component of projection is on a bearing part；Insulating barrier is formed on the bearing part, to make the insulating barrier coat the electronic component,
And the part surface of the conductive projection is made to expose to the insulating barrier；It is exposed in the insulating barrier and the conductive projection to form line construction
In on the part surface of the insulating barrier, and the line construction is made to be electrically connected with the conductive projection；And remove the bearing part.
In foregoing electronic packing piece and its preparation method, the electronic component has relative acting surface and non-active face, and should
Acting surface is bound to the conductive projection, and the electronic component is electrically connected with the conductive projection.For example, in the removal bearing part
Afterwards, the non-active face of the electronic component exposes to the insulating barrier；Or radiating is combined on the non-active face of the electronic component
Part.
In foregoing electronic packing piece and its preparation method, after the bearing part is removed, the electronic component exposes to the insulation
Layer.
In foregoing electronic packing piece and its preparation method, the conductive projection is solder bump.
In foregoing electronic packing piece and its preparation method, in addition to multiple conducting elements are formed on the line construction.
In addition, in foregoing electronic packing piece and its preparation method, in addition to multiple conductive poles are formed in the insulating barrier, and should
Conductive pole is electrically connected with the line construction.For example, after the bearing part is removed, the end face of the conductive pole exposes to the insulation
Layer.Further, in addition to connect and put electronic installation on the end face of the conductive pole.
From the foregoing, it will be observed that the electronic packing piece and its preparation method of the present invention have advantages below and beneficial effect：The electricity of the present invention
Sub- packaging part and its preparation method mainly coat the electronic component and the conductive projection by elder generation with the insulating barrier, on the insulating barrier
Form the line construction, therefore the insulating barrier need not be flowed through between the electronic component and the line construction, thus the electronic component with
Cavity will not be produced between the line construction, therefore product yield can be effectively lifted compared to prior art, the present invention.
In addition, the electronic packing piece of the present invention only forms line construction, without the plate body using known package substrate, therefore
Compared to prior art, the integral thickness of the electronic packing piece can be greatly decreased, to meet the needs of lightening.
Brief description of the drawings
Fig. 1 is the diagrammatic cross-section of known semiconductor packaging part；And
Fig. 2A to Fig. 2 E is the diagrammatic cross-section of the preparation method of the first embodiment of the electronic packing piece of the present invention；Wherein, scheme
2E ' and Fig. 2 E " is Fig. 2 E different embodiments；And
Fig. 3 A to Fig. 3 C are the diagrammatic cross-section of the preparation method of the second embodiment of the electronic packing piece of the present invention；Wherein, scheme
3C ' is Fig. 3 C another embodiment.
Description of reference numerals
1 semiconductor package part
10 package substrates
10a plate bodys
10b, 24,24 ' line constructions
100,240 line layers
11 semiconductor elements
11a, 21a acting surface
The non-active face of 11b, 21b
110,210 electronic padses
12 solder bumps
13 packing colloids
14 cavities
2,3 electronic packing pieces
20 bearing parts
200 metal levels
21 electronic components
22 conductive projections
22a top surfaces
23 insulating barriers
23a first surfaces
23b second surfaces
241 electric conductors
242 dielectric layers
25 conducting elements
26,26 ' radiating pieces
30 conductive poles
30a, 30b end face
31 electronic installations
32 connection projections.
Embodiment
Illustrate embodiments of the present invention below by way of particular specific embodiment, those skilled in the art can be by this explanation
Book disclosure of that understands other advantages and effect of the present invention easily.
It should be clear that structure, ratio, size depicted in this specification institute accompanying drawings etc., only coordinating specification institute public
The content opened, for skilled in the art realises that with reading, being not limited to the enforceable qualifications of the present invention, therefore not
Have technical essential meaning, the modification of any structure, the change of proportionate relationship or the adjustment of size, do not influenceing institute of the present invention
In the case of the effect of producing and the purpose that can reach, it all should still fall and obtain what can be covered in technology contents disclosed in this invention
In the range of.Meanwhile in this specification it is cited such as " on ", " first ", the term of " second " and " one ", be merely convenient to chat
That states understands, and is not used to limit the enforceable scope of the present invention, and its relativeness is altered or modified, and skill is being changed without essence
In the case of art content, when being also considered as the enforceable category of the present invention.
Fig. 2A to Fig. 2 E is the diagrammatic cross-section of the preparation method of the first embodiment of the electronic packing piece 2 of the present invention.
As shown in Figure 2 A, one is set to be combined with the electronic component 21 of multiple conductive projections 22 on a bearing part 20.
In the present embodiment, the surface of the bearing part 20 is formed with a metal level 200.In the present embodiment, the bearing part
20 be base material, such as copper clad laminate or other plate bodys, but is not particularly limited, and the present embodiment is explained with copper clad laminate, its both sides
With metal level 200.
In addition, it is active member, passive device or combination both it that the electronic component 21, which is semiconductor element, and this is actively
Element is such as semiconductor wafer, and the passive device is such as resistance, electric capacity and inductance.For example, the electronic component 21 is half
Conductor chip, it has relative acting surface 21a and non-active face 21b, and acting surface 21a has multiple electrode pads 210 to tie
Close and state conductive projection 22, and the conductive projection 22 is electrically connected with the electronic component 21, and the electronic component 21 is with its non-work
It is cemented on the metal level 200 by binder course (figure omit) with face 21b.
Also, the conductive projection 22 is solder bump.
As shown in Figure 2 B, an insulating barrier 23 is formed on the metal level 200 of the bearing part 20, to make the insulating barrier 23 coat
The electronic component 21 and above-mentioned conductive projection 22.
In the present embodiment, the insulating barrier 23 definition has relative first surface 23a and second surface 23b, with make this
Two surfaces are bound on the metal level 200 of the bearing part 20.
In addition, the insulating barrier 23 is the packing colloid of epoxy resin (epoxy), its available pressing (lamination) or mould
The mode of pressure (molding) is formed on the bearing part 20.
Also, the top surface 22a of the conductive projection 22 exposes to the insulating barrier 23.For example, by flattening processing procedure this can be made to lead
The top surface 22a of electric projection 22 flushes the first surface 23a of the insulating barrier 23.Specifically, the leveling processing procedure can be by grinding side
Formula, remove the part material of the conductive projection 22 and the part material of the insulating barrier 23.
As shown in Fig. 2 C to Fig. 2 D, a line construction 24 is formed in the insulating barrier 23 and the top surface of the conductive projection 22
On 22a, and the line construction 24 is electrically connected with above-mentioned conductive projection 22.
In the present embodiment, the line construction 24 includes one located at the insulating barrier 23 and the line layer on the conductive projection 22
240th, multiple electric conductors 241 and one on the line layer 240 coat the dielectric of the line layer 240 and above-mentioned electric conductor 241
Layer 242, and the line layer 240 is electrically connected with above-mentioned conductive projection 22, and make the part surface of above-mentioned electric conductor 241 expose to this
Dielectric layer 242.
In addition, the material for forming the line layer 240 is copper, and the electric conductor 241 is copper post body.
Also, the dielectric layer 242 is formed on the insulating barrier 23 with die cast, coating method or pressing mode, and formed
The material of the dielectric layer 242 is casting die compound (Molding Compound), subbing (Primer) or such as epoxy resin
(Epoxy) dielectric material.
As shown in Figure 2 E, the bearing part 20 and its metal level 200 are removed, to make the electronic component 21 expose to the insulating barrier
23, to complete the electronic packing piece 2 of the present invention.
In the present embodiment, the non-active face 21b of the electronic component 21 exposes to the second surface 23b of the insulating barrier 23,
And multiple conducting elements 25 such as soldered balls can be formed on the electric conductor 241 of the line construction 24, so that rear continued access is put such as circuit
The electronic installation of plate, encapsulating structure or other structures (such as another chip) (figure omits).
In addition, as the line construction 24 ' shown in Fig. 2 E ', being formed on insulating barrier 23 can also have multiple line layers 240 with
Multiple dielectric layers 242.
Also, as shown in Fig. 2 E ", can also be in the non-active face 21b and the insulating barrier 23 of the electronic component 21 second surface
A radiating piece 26 is combined on 23b.In an embodiment, the bearing part as used in Fig. 2A of the present invention can be metallic plate, and in
The part bearing part is only removed in processing procedure, retain to should be at the non-active face 21b of electronic component 21 bearing part, to be used as this
Radiating piece 26.The preparation method of the electronic packing piece 2 of the present invention coats the electronic component 21 and the conduction by elder generation with the insulating barrier 23
Projection 22, the line construction 24 is formed on the insulating barrier 23, therefore the insulating barrier 23 need not flow through the electronic component 21 with being somebody's turn to do
Between line construction 24.Therefore, when the electronic component 21 is large scale or high pin number, the electronic component 21 and the circuit knot
Cavity will not be produced between structure 24, thus is avoided that the problem of penetrating into aqueous vapor, popcorn effect will not more occur, therefore can effectively carry
Rise product yield.
In addition, the electronic packing piece 2 of the present invention only forms line construction 24, without making the plate of known package substrate
Body, therefore compared to prior art, the integral thickness of the electronic packing piece 2 can be greatly decreased, to meet the needs of lightening.
Fig. 3 A to Fig. 3 C are the diagrammatic cross-section of the preparation method of the second embodiment of the electronic packing piece 3 of the present invention.This implementation
The difference of example and first embodiment is newly-increased conductive pole, and other processing procedures are roughly the same, therefore only illustrate deviation below, and no longer
Repeat and mutually exist together.
As shown in Figure 3A, set multiple conductive poles 30 to be combined with the electronic component 21 of multiple conductive projections 22 with one to hold in one
In holder 20.
In the present embodiment, the conductive pole 30 is copper post.
As shown in Figure 3 B, the processing procedure such as Fig. 2 B to Fig. 2 D is carried out, to make above-mentioned conductive pole 30 be formed in the insulating barrier 23,
And the conductive pole 30 is electrically connected with the line layer 240 of the line construction 24.
In the present embodiment, when the leveling processing procedure such as Fig. 2 B is carried out, the part material of the conductive pole 30 can be removed, make this
The wherein end face 30a of conductive pole 30 flushes the first surface 23a of the insulating barrier 23.
In addition, after the bearing part 20 is removed, the other end 30b of the conductive pole 30 exposes to the of the insulating barrier 23
Two surface 23b.
Also, as shown in Figure 3 C, it can be formed multiple if the conducting element 25 of soldered ball is in the electric conductor 241 of the line construction 24
On, so that the electronic installation such as circuit board, encapsulating structure or other structures (such as another chip) is put in rear continued access (figure omits).
In addition, in successive process, as shown in Figure 3 C, can by connect projection 32 connect put an electronic installation 31 in respectively this lead
On the end face 30b of electric post 30, the electronic installation 31 is set to be electrically connected with the respectively conductive pole 30.For example, the electronic installation 31 is encapsulation
Part, active member or passive device.
, also can be in combining a radiating piece on the non-active face 21b of the electronic component 21 as shown in Fig. 3 C ' it should be appreciated that ground
26’.In an embodiment, the radiating piece 26 ' can be to retain the bearing part to should be at the non-active face 21b of electronic component 21
(being, for example, metallic plate).
The present invention provides a kind of electronic packing piece 2,3, and it includes：One insulating barrier 23, the electricity with multiple conductive projections 22
The line construction 24 of subcomponent 21 and one.
Described insulating barrier 23 has relative first surface 23a and second surface 23b.
Described electronic component 21 is embedded into the insulating barrier 23 with conductive projection 22, to make the part of the conductive projection 22
Surface (top surface 22a) exposes to the first surface 23a of the insulating barrier 23.
Described line construction 24 is formed on the first surface 23a of the insulating barrier 23 and is electrically connected with the conductive projection
22。
In an embodiment, the electronic component 21 has relative acting surface 21a and non-active face 21b, and the acting surface
21a combines above-mentioned conductive projection 22.
In an embodiment, a radiating piece 26,26 ' is combined on the non-active face 21b of the electronic component 21.
In an embodiment, the electronic component 21 exposes to the insulating barrier 23.For example, the non-active face of the electronic component 21
21b exposes to the second surface 23b of the insulating barrier 23.
In an embodiment, the conductive projection 22 is solder bump.
In an embodiment, described electronic packing piece 2,3 also includes the multiple conductions being formed on the line construction 24
Element 25.
In an embodiment, described electronic packing piece 3 also includes the multiple conductive poles 30 being formed in the insulating barrier 23,
And the conductive pole 30 is electrically connected with the line construction 24.
In an embodiment, the end face 30b of the conductive pole 30 exposes to the second surface 23b of the insulating barrier 23.
In an embodiment, described electronic packing piece 3 also connects the electricity on the end face 30b for being placed in the conductive pole 30 including one
Sub-device 31.
In summary, electronic packing piece of the invention and its preparation method, by elder generation with the insulating barrier coat the electronic component with
The conductive projection, the line construction is formed on the insulating barrier, therefore will not be produced between the electronic component and the line construction
Cavity, thus can effectively lift product yield.
In addition, the electronic packing piece of the present invention only forms line construction, without making the plate body of known package substrate, therefore
The integral thickness of the electronic packing piece can be greatly decreased, to meet the needs of lightening.
Above-described embodiment is only to the principle and its effect of the illustrative present invention, not for the limitation present invention.This
Art personnel can modify under the spirit and scope without prejudice to the present invention to above-described embodiment.Therefore the present invention
Rights protection scope, should be as listed by claims.
Claims (10)
1. a kind of electronic packing piece, it is characterized in that, the electronic packing piece includes：
Insulating barrier；
The electronic component of multiple conductive projections is combined with, it is embedded into the insulating barrier, and makes the part surface of the conductive projection
Expose to the insulating barrier；And
Line construction, it is formed at the insulating barrier and the conductive projection is exposed on the part surface of the insulating barrier and is electrically connected with
The conductive projection.
2. electronic packing piece as claimed in claim 1, it is characterized in that, the electronic component have relative acting surface with it is non-active
Face, and the acting surface is bound to the conductive projection, and the electronic component is electrically connected with the conductive projection.
3. electronic packing piece as claimed in claim 1, it is characterized in that, the conductive projection is solder bump.
4. electronic packing piece as claimed in claim 1, it is characterized in that, the electronic packing piece also includes being formed in the insulating barrier
Multiple conductive poles, and the conductive pole is electrically connected with the line construction.
5. electronic packing piece as claimed in claim 4, it is characterized in that, the electronic packing piece also includes connecing being placed in the conductive pole
Electronic installation on end face.
6. a kind of preparation method of electronic packing piece, it is characterized in that, the preparation method comprises the following steps：
One is set to be combined with the electronic component of multiple conductive projections on a bearing part；
Insulating barrier is formed on the bearing part, to make the insulating barrier coat the electronic component, and makes the part table of the conductive projection
Face exposes to the insulating barrier；
Line construction is formed on the part surface that the insulating barrier and the conductive projection expose to the insulating barrier, and makes the circuit knot
Structure is electrically connected with the conductive projection；And
Remove the bearing part.
7. the preparation method of electronic packing piece as claimed in claim 6, it is characterized in that, the electronic component have relative acting surface with
Non-active face, and the acting surface is bound to the conductive projection, and the electronic component is electrically connected with the conductive projection.
8. the preparation method of electronic packing piece as claimed in claim 6, it is characterized in that, the conductive projection is solder bump.
9. the preparation method of electronic packing piece as claimed in claim 6, it is characterized in that, the preparation method also includes forming multiple conducting elements
In on the line construction.
10. the preparation method of electronic packing piece as claimed in claim 9, it is characterized in that, the preparation method also include connecing put electronic installation in
On the end face of the conductive pole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610686258.0A CN107768320A (en) | 2016-08-18 | 2016-08-18 | Electronic packing piece and its preparation method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610686258.0A CN107768320A (en) | 2016-08-18 | 2016-08-18 | Electronic packing piece and its preparation method |
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| CN107768320A true CN107768320A (en) | 2018-03-06 |
Family
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| CN201610686258.0A Pending CN107768320A (en) | 2016-08-18 | 2016-08-18 | Electronic packing piece and its preparation method |
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