CN107743101A - The retransmission method and device of a kind of data - Google Patents
The retransmission method and device of a kind of data Download PDFInfo
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- CN107743101A CN107743101A CN201710880563.8A CN201710880563A CN107743101A CN 107743101 A CN107743101 A CN 107743101A CN 201710880563 A CN201710880563 A CN 201710880563A CN 107743101 A CN107743101 A CN 107743101A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding in a switch fabric
- H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
- H04L49/254—Centralised controller, i.e. arbitration or scheduling
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Abstract
The present invention provides a kind of retransmission method and device of data, and method includes：If the first memory module needs to forward data, request instruction is sent to control module by the first memory module；It is that the first inbound port corresponding to the first memory module determines the first exit port and the first index value by control module if control module receives request instruction；The response instruction for carrying the first index value is sent to the first memory module by control module；If the first memory module receives response instruction, the data for needing to forward and the first index value are sent to control module by the first memory module；First exit port is determined based on the first index value by control module；Data are forwarded by the second memory module corresponding to control module to the first exit port.Using the embodiment of the present invention, the processing procedure of multiple data forwardings can realize parallel processing by control module, substantially increase the disposed of in its entirety performance of fpga chip, and treatment effeciency is high.
Description
Technical field
The present invention relates to the retransmission method and device of network communication technology field, more particularly to a kind of data.
Background technology
Generally, fpga chip includes multiple memory modules, and data need to be forwarded between different memory modules.Due to
The quantity of memory module is larger, and how data are efficiently carried out to forwarding between different memory modules and is asked as vital
Topic.
In the prior art, the data that the needs stored in multiple memory modules forward, stored successively to a stage die
In block, transitional module is successively by the data forwarding that needs forward to corresponding memory module.The forwarding speed of fpga chip depends on
In the processing speed of transitional module.Due to the limitation of transitional module processing speed, the disposed of in its entirety of fpga chip is greatly reduced
Performance, treatment effeciency are low.
The content of the invention
In view of this, the present invention provides a kind of retransmission method and device of data, is the first inbound port by control module
The first exit port is determined, the processing procedure of multiple data forwardings can realize parallel processing by control module, to solve FPGA
The disposed of in its entirety performance of chip, the problem for the treatment of effeciency is low.
To achieve the above object, it is as follows to provide technical scheme by the present invention：
According to the first aspect of the invention, it is proposed that a kind of retransmission method of data, methods described include：
If the first memory module needs to forward data, being sent by first memory module to the control module please
Instruction is asked, first memory module is one of memory module in the multiple memory module；
It is first memory module by the control module if the control module receives the request instruction
Corresponding first inbound port determines the first exit port and the first index value；
The response instruction for carrying first index value is sent to first memory module by the control module；
If first memory module receives the response instruction, by first memory module to the control
Module sends the data for needing to forward and first index value；
First exit port is determined based on first index value by the control module；
The data are forwarded by the second memory module corresponding to the control module to first exit port, described the
Two memory modules are one of module in the multiple memory module.
According to the second aspect of the invention, it is proposed that a kind of retransmission unit of data, including：Control module, multiple storages
Module；
Wherein, the first memory module, if being configured as the first memory module needs to forward data, to the control module
Request instruction is sent, first memory module is one of memory module in the multiple memory module；
The control module, if being configured as receiving the request instruction, for corresponding to first memory module
First inbound port determines the first exit port and the first index value, is sent to first memory module and carries first index value
Response instruction；
First memory module, if being additionally configured to receive the response instruction, sent to the control module
Need the data that forward and first index value；
The control module, it is additionally configured to determine first exit port based on first index value, to described
Second memory module corresponding to one exit port forwards the data, and second memory module is in the multiple memory module
One of module.
From above technical scheme, fpga chip goes out end by control module for corresponding to the determination of the first inbound port first
Mouth and the first index value, fpga chip pass through the first memory module corresponding to control module to the first inbound port and send the first index
Value, start to send data to control module to trigger the first memory module, when control module receives data, fpga chip is based on
First index value, the first exit port is found by control module, fpga chip passes through corresponding to control module to the first exit port
Second memory module sends data.Control module is that the first inbound port determines the first exit port, and multiple data forwardings treat
Journey can realize parallel processing by control module, substantially increase the disposed of in its entirety performance of fpga chip, and treatment effeciency is high.
Brief description of the drawings
Figure 1A is the embodiment flow chart of the retransmission method of a data provided by the invention；
Figure 1B is the exemplary scenario figure of Figure 1A illustrated embodiments；
Fig. 2 is the embodiment flow chart of the retransmission method of another data provided by the invention；
Fig. 3 is the embodiment flow chart of the retransmission method of another data provided by the invention；
Fig. 4 is a kind of hardware structure diagram of fpga chip provided by the invention；
Fig. 5 is the embodiment block diagram of the retransmission unit of a data provided by the invention.
Embodiment
Here exemplary embodiment will be illustrated in detail, its example is illustrated in the accompanying drawings.Following description is related to
During accompanying drawing, unless otherwise indicated, the same numbers in different accompanying drawings represent same or analogous key element.Following exemplary embodiment
Described in embodiment do not represent and the consistent all embodiments of the present invention.On the contrary, they be only with it is such as appended
The example of the consistent apparatus and method of some aspects being described in detail in claims, of the invention.
It is only merely for the purpose of description specific embodiment in terminology used in the present invention, and is not intended to be limiting the present invention.
It is also intended in " one kind " of the singulative of the invention with used in appended claims, " described " and "the" including majority
Form, unless context clearly shows that other implications.It is also understood that term "and/or" used herein refers to and wrapped
Containing the associated list items purpose of one or more, any or all may be combined.
It will be appreciated that though various information, but this may be described using term first, second, third, etc. in the present invention
A little information should not necessarily be limited by these terms.These terms are only used for same type of information being distinguished from each other out.For example, do not departing from
In the case of the scope of the invention, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as
One information.Depending on linguistic context, word as used in this " if " can be construed to " ... when " or " when ...
When " or " in response to determining ".
Figure 1A is the embodiment flow chart of the retransmission method of a data provided by the invention；Figure 1B is implemented shown in Figure 1A
The exemplary scenario figure of example.The retransmission method of the data can be applied in fpga chip, and fpga chip includes：Control module,
Multiple memory modules.Wherein control module can be the module for having in fpga chip control function, and memory module can be
FIFO memory, as shown in Figure 1A, comprise the following steps：
Step 101：If the first memory module needs to forward data, being sent by the first memory module to control module please
Instruction is asked, the first memory module is one of memory module in multiple memory modules.
Step 102：It is the corresponding to the first memory module by control module if control module receives request instruction
One inbound port determines the first exit port and the first index value.
Step 103：The response instruction for carrying the first index value is sent to the first memory module by control module.
Step 104：If the first memory module receives response instruction, sent by the first memory module to control module
Need data and the first index value forwarded.
Step 105：First exit port is determined based on the first index value by control module.
Step 106：Data, the second storage mould are forwarded by the second memory module corresponding to control module to the first exit port
Block is one of module in multiple memory modules.
In a step 101, in one embodiment, it will be appreciated by persons skilled in the art that memory module and storage mould
The data stored in block need forwarding mutually.If one of memory module in multiple memory modules needs to forward data,
One of memory module in the plurality of memory module is the first memory module.Fpga chip by the first memory module to
Control module sends the request instruction for forwarding data.
In a step 102, in one embodiment, if control module receives request instruction, fpga chip passes through control
Module is that the first inbound port corresponding to the first memory module determines the first exit port, and the first exit port is used to subsequently forward first to deposit
The data forwarded are needed in storage module, the first inbound port is, for example, 00, and the first exit port is, for example, 55；Fpga chip passes through control
Module is the first index value corresponding to the first memory module determines, the first index value goes out end for corresponding first inbound port and first
Mouthful, the first index value is, for example, 2.Specifically, fpga chip is first to enter end corresponding to the first memory module by control module
Mouth determines associated description of the step of the first exit port and the first index value referring to following step 201- steps 202, herein first not
Repeat.It should be noted that when the first index value determines the corresponding relation with the first inbound port and the first exit port, control
Module stops receiving the request instruction from the first inbound port, avoids multiple memory modules simultaneously by the first inbound port to control
Module sends request instruction and produces conflict.
In step 103, in one embodiment, fpga chip is sent to the first memory module by control module and carries the
The response instruction of one index value, represents that fpga chip has had built up corresponding with the first index value first by control module
Inbound port and the first exit port.
At step 104, in one embodiment, if the first memory module receives response instruction, represent that fpga chip leads to
Cross control module and determined the first exit port for the first inbound port corresponding to the first memory module, data can be carried out and turned
Send out, then fpga chip sends the data for needing to forward and the first index value by the first memory module to control module.
In step 105, in one embodiment, the first index is based on by control module with reference to step 102, fpga chip
Value 2 determines and 00 corresponding first exit port 55 of the first inbound port.
In step 106, in one embodiment, the second memory module is memory module corresponding to the first exit port, second
Memory module is one of module in multiple memory modules.Fpga chip passes through corresponding to control module to the first exit port
Second memory module forwards data, and the second memory module stores to data.Wherein, fpga chip is forwarded by control module
Data, can control data to a certain extent forwarding speed, and data forwarding successively.
Specifically, the exemplary scenario figure with reference to shown in Figure 1B, using memory module as fifo register, fpga chip 11 wraps
Control module 111, fifo register 112, fifo register 113, fifo register 114, fifo register 115, FIFO is included to post
Storage 116, fifo register 117 amount to exemplified by 6 memory modules.Control module 111 includes inbound port 1111, inbound port
1112nd, inbound port 1113, exit port 1114, exit port 1115.If fifo register 112 (can be considered that first in the application deposits
Storage module) need forward data, fifo register 112 by inbound port 1111 (can be considered the first inbound port in the application) to
The request instruction that control module 111 is sent, request control module 111 are the data turn that fifo register 112 builds entry/exit port
Send out path.Control module 111 determines an exit port and the first rope from exit port 1114, exit port 1115 for inbound port 1111
Draw value, such as determine exit port 1114 (can be considered the first exit port in the application) and the first index value 2, control module 111
Forward-path from inbound port 1111 to exit port 1114, the first index value 2 are established for the data forwarding of fifo register 112
To should forward-path.Control module 111 sends the response instruction for carrying the first index value 2 to fifo register 112, represents number
According to forward-path it has been determined that data can be transmitted.Fifo register 112 receives response instruction, and being sent to control module 111 needs
The data to be forwarded and the first index value 2.Control module 111 is based on exit port 1114 corresponding to the determination of the first index value 2.Control
Fifo register 116 corresponding to module 111 to exit port 1114 (can be considered the second memory module in the application) forwards data.
In the embodiment of the present invention, fpga chip by control module be the first inbound port determine corresponding to the first exit port and
First index value, fpga chip send the first index value by the first memory module corresponding to control module to the first inbound port,
Start to send data to control module to trigger the first memory module, when control module receives data, fpga chip is based on the
One index value, the first exit port is found by control module, fpga chip passes through corresponding to control module to the first exit port
Two memory modules send data.Control module is that the first inbound port determines the first exit port, the processing procedure of multiple data forwardings
Parallel processing can be realized by control module, substantially increase the disposed of in its entirety performance of fpga chip, treatment effeciency is high.
Fig. 2 is the embodiment flow chart of the retransmission method of another data provided by the invention, and how fpga chip is led to
Cross control module and determine that the first exit port and the progress of the first index value are exemplary for the first inbound port corresponding to the first memory module
Illustrate, as shown in Fig. 2 comprising the following steps：
Step 201：First preset rules are based on by control module, at least one recorded from first the presets list
The first index value is determined in two index values.
Step 202：Second preset rules are based on by control module, at least one recorded from second the presets list
The first exit port is determined in two exit ports.
Step 203：The corresponding pass established by control module between the first inbound port, the first exit port and the first index value
System.
In step 201, at least one second index value is have recorded in first the presets list, each second index value can
For the corresponding relation of corresponding a pair of entry/exit ports, therefore, control module can provide end for the forwarding of multiple data simultaneously
The support of mouth corresponding relation.First preset rules can be：It is preferential to choose the second index value for not recording corresponding relation.Such as table 1
It is shown, it is the topology example of first the presets list：
Table 1
| Second index value | Inbound port | Exit port |
| 1 | 44 | 33 |
| 2 | - | - |
| 3 | - | - |
The second index value in table 1 includes 1,2,3 three the second index value, the corresponding inbound port 44 of the second index value 1, goes out end
Mouth corresponding 33."-" represents entry/exit port not yet corresponding to determination.Fpga chip is based on the first preset rules by control module：
It is preferential to choose the second index value for not recording corresponding relation, the second index value recorded from first the presets list shown in table 1
1st, it is 2 that the first index value is determined in 2,3.
In step 202, fpga chip is based on the second preset rules by control module, is recorded from second the presets list
At least one second exit port in determine the first exit port.Wherein, at least one second recorded in second the presets list goes out
The corresponding status indicator of the exit port of each in port second, each second exit port also correspond to a called number,
The called number of status indicator corresponding to each second exit port and port is based on by control module and determines that first goes out end
Mouthful, specifically, status indicator is used for the occupancy situation for representing port, such as status indicator " 1 " represents that port is occupied, state mark
Know " 0 " and represent that port is idle.Second preset rules can be：Preferentially choose the port of idle condition and the end that called number is few
Mouthful.As shown in table 2, it is the topology example of second the presets list：
Table 2
| Second exit port | Status indicator | Call number |
| 55 | 0 | 1 |
| 77 | 1 | 4 |
| 22 | 0 | 3 |
The second exit port in table 2 includes 22,55,77, wherein, status indicator corresponding to the second exit port 55 is " 0 ", is adjusted
It is " 1 " with number；Status indicator corresponding to second exit port 77 is " 1 ", and call number is " 4 "；Second exit port " 22 " is corresponding
Status indicator be " 0 ", call number is " 3 ".According to the second preset rules：Preferentially choose the port of idle condition and be called
The few port of number, then the second exit port 55 be confirmed as the first exit port.
In step 203, fpga chip establishes the first inbound port, the first exit port and the first index value by control module
Between corresponding relation, the corresponding relation can be recorded in first the presets list shown in table 1.With reference to step 201- steps
202, using the first inbound port as 00, the first exit port is 55, and exemplified by the first index value is 2, fpga chip will by control module
First inbound port 00, the first exit port 55, the first index value are recorded in first the presets list for 2, are first as shown in table 3
The example after corresponding relation is recorded in the presets list：
Table 3
| Second index value | Inbound port | Exit port |
| 1 | 44 | 33 |
| 2 | 00 | 55 |
| 3 | - | - |
In table 3, fpga chip by control module by the first inbound port 00, the first exit port 55, the first index value be 2 it
Between corresponding relation be recorded in first the presets list.
In the embodiment of the present invention, fpga chip is based on the first preset rules by control module, determines the first index value, leads to
Cross control module and be based on the second preset rules, determine the first exit port, by adjusting the first preset rules and the second preset rules
Different port can be selected according to demand；First inbound port, the first exit port and the first rope are established by control module
Draw the corresponding relation between value, the corresponding relation of entry/exit port can be recorded in first the presets list, pass through acquisition
First the presets list, the service condition into/port can be grasped, is adjusted in time into/port number.
Fig. 3 is the embodiment flow chart of the retransmission method of another data provided by the invention, and the embodiment of the present invention combines
Figure 1A, Fig. 2, on the basis of step 101- steps 106, fpga chip is performed corresponding to the first exit port by control module
The second memory module forwarding data the step of after disposition it is illustrative, as shown in figure 3, including as follows walk
Suddenly：
Step 301：Detect in data whether carry the end of identification terminated for flag data by the second memory module.
Step 302：When detected by the second memory module carry end of identification in data when, terminate data storage.
Step 303：The END instruction forwarded for end is sent to control module by the second memory module.
Step 304：If control module receives END instruction, gone out by the first inbound port of control module releasing, first
Corresponding relation between port and the first index value.
Step 305：It is pre- to judge whether the residual memory space of the second memory module is less than or equal to by control module
If amount of storage.
Step 306：When the residual memory space of the second memory module is less than or equal to preset stored amount, pass through control
The state of first exit port is arranged to idle by module.
In step 301, whether carried in the data that fpga chip is received by the detection of the second memory module for marking
Remember the end of identification of end of data.It will be appreciated by persons skilled in the art that each packet has end mark, terminate mark
Such as can be：1111st, 0000 etc..
In step 302, when fpga chip is detected by the second memory module carries end of identification in data, knot
Beam data storage.
In step 303, fpga chip sends the end for terminating forwarding by the second memory module to control module
Instruction, so that control module stops sending data to the second memory module.
In step 304, if control module receives END instruction, fpga chip releases first by control module and entered
Corresponding relation between port, the first exit port and the first index value.Specifically, with reference to the table 3 in Fig. 2, on the basis of table 3
On, as shown in table 4, first between the first inbound port of releasing, the first exit port and the first index value after corresponding relation is pre-
If list example：
Table 4
| Second index value | Inbound port | Exit port |
| 1 | 44 | 33 |
| 2 | - | - |
| 3 | - | - |
In table 4, the first inbound port 00 in first the presets list, the first exit port 55 is deleted.
In step 305, fpga chip releases the first inbound port, the first exit port and the first index value by control module
Between corresponding relation the step of after, fpga chip judges that the residual memory space of the second memory module is by control module
It is no to be less than or equal to preset stored amount, if it will be appreciated by persons skilled in the art that the memory space of the second memory module
For completely state, the second memory module data will can not be continued to.Preset stored amount is that the second memory module can continue to
The lowest threshold of data, as the second memory module, which are more than preset stored amount, can ensure to continue to simultaneously data storage.
Within step 306, when the residual memory space of the second memory module is less than or equal to preset stored amount, represent
Second memory module has enough memory spaces, can continue to simultaneously data storage, therefore fpga chip passes through control module
The state of first exit port is arranged to idle, specifically, being represented with reference to the associated description of step 202, such as status indicator " 1 "
Port is occupied, and status indicator " 0 " represents that port is idle, and status indicator corresponding to the first exit port is arranged to " 0 ".
In the embodiment of the present invention, if the second memory module terminates data storage, fpga chip is released by control module
Corresponding relation between first inbound port, the first exit port and the first index value, when the residual memory space of the second memory module
During less than or equal to preset stored amount, the state of the first exit port is arranged to idle by fpga chip by control module, is made
Obtain entry/exit port to be multiplexed, as early as possible release port resource, improve the overall treatment efficiency of fpga chip.
Corresponding to the retransmission method of above-mentioned data, the invention also provides the hardware structure diagram of the fpga chip shown in Fig. 4.
Fig. 4 is refer to, in hardware view, the fpga chip includes processor, internal bus, network interface, internal memory and non-volatile
Memory, the hardware being also possible that certainly required for other business.Corresponding to processor is read from nonvolatile memory
Computer program is into internal memory and then runs, and the retransmission unit of data is formed on logic level.Certainly, except software realization side
Outside formula, the present invention is not precluded from other implementations, such as mode of logical device or software and hardware combining etc., that is,
Say that the executive agent of following handling process is not limited to each logic unit or hardware or logical device.
Fig. 5 is the embodiment block diagram of the retransmission unit of a data provided by the invention, as shown in figure 5, the data turn
Transmitting apparatus can include：Control module 51 and multiple memory modules, such as multiple memory modules include memory module 52, storage mould
55 4 block 53, memory module 54, memory module memory modules are, it is necessary to illustrate, four storages in embodiment illustrated in fig. 5
Device is merely illustrative, and it can not form the limitation to the application, and multiple memory modules in the application can be two
Any number of memory module above, wherein, it is the first memory module described herein, storage mould with memory module 52
Block 53 is exemplified by the second memory module described herein；
Wherein, memory module 52, if being configured as memory module 52 needs to forward data, being sent to control module 51 please
Instruction is asked, memory module 52 is one of memory module in multiple memory modules；
Control module 51, it is true for the first inbound port corresponding to memory module 52 if being configured as receiving request instruction
Fixed first exit port and the first index value, the response instruction for carrying the first index value is sent to memory module 52；
Memory module 52, if being additionally configured to receive response instruction, the number for needing to forward is sent to control module 51
According to and the first index value；
Control module 51, it is additionally configured to determine the first exit port based on the first index value, to corresponding to the first exit port
Memory module 53 forwards data, and memory module 53 is one of module in multiple memory modules.
In one embodiment, control module 51 is additionally configured to be based on the first preset rules, remembers from first the presets list
The first index value is determined at least one second index value of record, based on the second preset rules, is recorded from second the presets list
At least one second exit port in determine the first exit port.
In one embodiment, control module 51 is additionally configured to establish the first inbound port, the first exit port and the first index
Corresponding relation between value.
In one embodiment, memory module 53 is configured as by storing mould corresponding to control module 51 to the first exit port
After block 53 forwards the step of data, detect in data whether carry the end of identification terminated for flag data, when by depositing
Storage module 53 is detected when end of identification is carried in data, terminates data storage, is sent to control module 51 for terminating to turn
The END instruction of hair；
Control module 51, if being additionally configured to control module 51 receives END instruction, release the first inbound port, first
Corresponding relation between exit port and the first index value.
In one embodiment, control module 51 is additionally configured to releasing the first inbound port, the first exit port and the first rope
After the step of drawing the corresponding relation between value, judge whether the residual memory space of memory module 53 is less than or equal to and preset
Amount of storage, when the residual memory space of memory module 53 is less than or equal to preset stored amount, by the state of the first exit port
It is arranged to idle.
The function of unit and the implementation process of effect specifically refer to and step are corresponded in the above method in said apparatus
Implementation process, it will not be repeated here.
For device embodiment, because it corresponds essentially to embodiment of the method, so related part is real referring to method
Apply the part explanation of example.Device embodiment described above is only schematical, wherein described be used as separating component
The unit of explanation can be or may not be physically separate, can be as the part that unit is shown or can also
It is not physical location, you can with positioned at a place, or can also be distributed on multiple NEs.Can be according to reality
Need to select some or all of module therein to realize the purpose of the present invention program.Those of ordinary skill in the art are not paying
In the case of going out creative work, you can to understand and implement.
As seen from the above-described embodiment, fpga chip is the first exit port corresponding to the first inbound port determines by control module
And first index value, fpga chip pass through the first memory module corresponding to control module to the first inbound port and send the first index
Value, start to send data to control module to trigger the first memory module, when control module receives data, fpga chip is based on
First index value, the first exit port is found by control module, fpga chip passes through corresponding to control module to the first exit port
Second memory module sends data.Control module is that the first inbound port determines the first exit port, and multiple data forwardings treat
Journey can realize parallel processing by control module, substantially increase the disposed of in its entirety performance of fpga chip, and treatment effeciency is high.
Those skilled in the art will readily occur to the present invention its after considering specification and putting into practice invention disclosed herein
Its embodiment.It is contemplated that cover the present invention any modification, purposes or adaptations, these modifications, purposes or
Person's adaptations follow the general principle of the present invention and including undocumented common knowledges in the art of the invention
Or conventional techniques.Description and embodiments are considered only as exemplary, and true scope and spirit of the invention are by following
Claim is pointed out.
It should also be noted that, term " comprising ", "comprising" or its any other variant are intended to nonexcludability
Comprising so that process, method, commodity or equipment including a series of elements not only include those key elements, but also wrapping
Include the other element being not expressly set out, or also include for this process, method, commodity or equipment intrinsic want
Element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that wanted including described
Other identical element also be present in the process of element, method, commodity or equipment.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
God any modification, equivalent substitution and improvements done etc., should be included within the scope of protection of the invention with principle.
Claims (10)
1. a kind of retransmission method of data, is applied in fpga chip, the fpga chip includes：Control module, multiple storage moulds
Block, it is characterised in that methods described includes：
If the first memory module needs to forward data, request is sent to the control module by first memory module and referred to
Order, first memory module are one of memory module in the multiple memory module；
It is corresponding for first memory module by the control module if the control module receives the request instruction
The first inbound port determine the first exit port and the first index value；
The response instruction for carrying first index value is sent to first memory module by the control module；
If first memory module receives the response instruction, by first memory module to the control module
Send the data for needing to forward and first index value；
First exit port is determined based on first index value by the control module；
The data are forwarded by the second memory module corresponding to the control module to first exit port, described second deposits
It is one of module in the multiple memory module to store up module.
2. according to the method for claim 1, it is characterised in that described that mould is stored for described first by the control module
First inbound port corresponding to block determines the first exit port and the first index value, including：
First preset rules are based on by the control module, at least one second index value recorded from first the presets list
The first index value of middle determination；
Second preset rules are based on by the control module, at least one second exit port recorded from second the presets list
The first exit port of middle determination.
3. according to the method described in claim 1 or claim 2, it is characterised in that described to pass through the control module base
Before the step of first index value determines first exit port, methods described also includes：
Pair established by the control module between first inbound port, first exit port and first index value
It should be related to.
4. according to the method for claim 3, it is characterised in that it is described by the control module to first exit port
After corresponding second memory module forwards the step of data, methods described also includes：
Detect in the data whether carry the end of identification terminated for flag data by second memory module；
When detected by second memory module carry the end of identification in the data when, terminate to store the number
According to；
The END instruction forwarded for end is sent to the control module by second memory module；
If the control module receives the END instruction, first inbound port, institute are released by the control module
State the corresponding relation between the first exit port and first index value.
5. according to the method for claim 4, it is characterised in that described that end is entered by control module releasing described first
Mouthful, corresponding relation between first exit port and first index value the step of after, in addition to：
Whether the residual memory space for judging second memory module by the control module is less than or equal to default deposit
Reserves；
When the residual memory space of second memory module is less than or equal to preset stored amount, pass through the control module
The state of first exit port is arranged to idle.
6. a kind of retransmission unit of data, it is characterised in that described device includes：Control module, multiple memory modules；
Wherein, the first memory module, if being configured as the first memory module needs to forward data, sent to the control module
Request instruction, first memory module are one of memory module in the multiple memory module；
The control module, if being configured as receiving the request instruction, for first corresponding to first memory module
Inbound port determines the first exit port and the first index value, and the sound for carrying first index value is sent to first memory module
It should instruct；
First memory module, if being additionally configured to receive the response instruction, being sent to the control module needs
The data of forwarding and first index value；
The control module, it is additionally configured to determine first exit port based on first index value, goes out to described first
Second memory module corresponding to port forwards the data, second memory module be in the multiple memory module wherein
One module.
7. device according to claim 6, it is characterised in that
The control module, it is additionally configured to be based on the first preset rules, at least one recorded from first the presets list
The first index value is determined in two index values, based on the second preset rules, at least one second recorded from second the presets list
The first exit port is determined in exit port.
8. according to the device described in claim 6 or claim 7, it is characterised in that
The control module, it is additionally configured to establish first inbound port, first exit port and first index value
Between corresponding relation.
9. device according to claim 8, it is characterised in that
Second memory module, it is configured as described depositing by corresponding to the control module to first exit port second
After the step of storing up data described in module forwards, the end mark for whether carrying in the data and terminating for flag data is detected
Know, when detected by second memory module carry the end of identification in the data when, terminate to store the number
According to, to the control module send for terminate forwarding END instruction；
The control module, if being additionally configured to the control module receives the END instruction, release described first and enter
Corresponding relation between port, first exit port and first index value.
10. device according to claim 9, it is characterised in that
The control module, it is additionally configured to releasing first inbound port, first exit port and first index
After corresponding relation between value, judge whether the residual memory space of second memory module is less than or equal to default deposit
Reserves, when the residual memory space of second memory module is less than or equal to preset stored amount, go out end by described first
The state of mouth is arranged to idle.
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