CN107703819A - A kind of single-chip microcomputer - Google Patents
A kind of single-chip microcomputer Download PDFInfo
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- CN107703819A CN107703819A CN201711047504.9A CN201711047504A CN107703819A CN 107703819 A CN107703819 A CN 107703819A CN 201711047504 A CN201711047504 A CN 201711047504A CN 107703819 A CN107703819 A CN 107703819A
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- 238000005457 optimization Methods 0.000 abstract description 3
- 210000001367 artery Anatomy 0.000 description 3
- 210000003462 vein Anatomy 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P8/00—Arrangements for controlling dynamo-electric motors rotating step by step
- H02P8/14—Arrangements for controlling speed or speed and torque
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
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Abstract
The present invention provides a kind of single-chip microcomputer, and the single-chip microcomputer includes the first timer and second timer using cascade mode connection, wherein, the first timer produces the pulse signal of specific frequency and exported to outside；The second timer counts to pulse signal caused by the first timer, when count value reaches preset value, triggering interrupt service routine is modified to the related register of the first timer and the second timer, to set the frequency and number of follow-up output pulse.Pulse output is completed by timer hardware in technical scheme provided by the invention, software only needs just intervene to modify to follow-up pulse frequency, number when the output of default pulse number finishes, during the pulse signal of preset frequency, number is exported, completely without the operation of software, realize the soft or hard piece optimization of system, hardware configuration is enormously simplify, reduces system cost.
Description
Technical field
The present invention relates to hardware circuit field, more particularly to a kind of single-chip microcomputer.
Background technology
With the progress of electronics technology, stepper motor has been widely used, but stepper motor can not be as common straight
Stream motor, alternating current generator is the same is used under routine.Because the speed of stepper motor operation is determined by pulse frequency, the rotation of operation
Gyration determines by pulse number, therefore when controlling stepper motor, it is necessary to provide it with all controllable arteries and veins of pulse number, frequency
Rush signal.
Traditional mode is built using Digital Logical Circuits, one kind be using signal generator (such as NE555 or
The resonance circuit formed with 74HC04 phase inverters), frequency divider (such as d type flip flop), logic gates, decoder, counter etc.,
But circuit structure is extremely complex.Another kind is taken using programmable logic chips such as CPLD/FPGA, although circuit structure obtains
Simplification has been arrived, but has used CPLD/FPGA to produce the pulse signal of Driving Stepping Motor with them, has been difficult to realize outside system
The functions such as display, communication, Row control required for enclosing, it is also necessary to additional single-chip microcomputer or other microcontrollers could realize,
System is equally complex and expensive.In addition, also a kind of is to produce pulse signal using 51 common single-chip microcomputers, it is real
Existing method is that low and high level signal is constantly exported from I/O port using delay plus by way of counting software program, so as to realize arteries and veins
Punching output, for example want the pulse signal that output frequency is 200K, pulse period 5us, then software needs to turn over IO per 2.5us
Turn once, therefore this mode extremely consumes the software resource of single-chip microcomputer, makes it not have unnecessary computing capability to realize substantially
Other functions, can not realize it is controllable while pulse frequency and number, therefore application be also very limited.
The content of the invention
In view of this, it is an object of the invention to provide a kind of single-chip microcomputer, it is intended to which solution needs consumption big in the prior art
The software resource of amount could realize the controllable output of the number and frequency of pulse signal, and circuit structure is sufficiently complex, cost
The problem of higher.
The present invention proposes a kind of single-chip microcomputer, wherein, the single-chip microcomputer includes the first timer using cascade mode connection
And second timer, wherein,
The first timer produces the pulse signal of specific frequency and exported to outside；
The second timer counts to pulse signal caused by the first timer, when count value reaches pre-
If during value, triggering interrupt service routine is modified to the related register of the first timer and the second timer,
To set the frequency and number of follow-up output pulse.
Preferably, the first timer includes the first pre-divider and the first counter register, wherein, described first is pre-
Frequency divider divides to internal clocking, and is supplied to first counter register to be counted the signal after frequency dividing.
Preferably, first counter register includes clear input and counting input end, wherein, have when resetting input
By count value be zero clearly during effect, when reset input it is invalid when count value is continuously increased the maximum until reaching bit wide permission,
And overflowed after the maximum is reached and return to zero.
Preferably, the first timer also includes first comparator and the second comparator, wherein, first counting is posted
The count value of storage is connected to the first comparator and second comparator simultaneously.
Preferably, the first timer also includes the first comparand register, wherein, the value of first comparand register
The first comparator is connected to, and compared with the count value of first counter register, and comparative result is OCREF
Signal.
Preferably, the first timer also includes automatic reload registers, wherein, the value of the automatic reload registers
Second comparator is input to, and compared with the count value of first counter register.
Preferably, count value and the automatic reload registers of second comparator to first counter register
Value be compared, if the two is equal, the output signal of second comparator is by the meter of first counter register
Numerical value is reset.
Preferably, the first timer also includes the first output module, wherein, the OCREF signals are by described the
Export to form actual pulse output signals from I/O port after one output module, so that the stepper motor being connected with the single-chip microcomputer drives
Dynamic device uses.
Preferably, the second timer includes the second pre-divider and the second counter register, wherein, described second is pre-
Frequency divider receives the OCREF signals of its output from the first comparator and the OCREF signals is divided in advance,
It is and the output of pulse signal after frequency dividing to second counter register, pulse of second counter register to output is individual
Number is counted.
Preferably, the second timer also includes the second comparand register and the 3rd comparator, wherein, second ratio
The 3rd comparator is connected to compared with register, the count value of second counter register is exported to the 3rd comparator,
3rd comparator is compared to the value of second comparand register and the count value of second counter register, and
Interrupt trigger signal is being produced when the two is equal.
Pulse output is completed by timer hardware in technical scheme provided by the invention, and software is only needed default
Pulse number output can be just intervened to be modified to follow-up pulse frequency, number when finishing, in output preset frequency, number
Pulse signal during, completely without the operation of software, realize the soft or hard piece optimization of system, enormously simplify hardware knot
Structure, reduce system cost.
Brief description of the drawings
Fig. 1 is the structural representation of single-chip microcomputer in an embodiment of the present invention.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
A kind of single-chip microcomputer provided by the present invention will be described in detail below.
Referring to Fig. 1, the structural representation for single-chip microcomputer in an embodiment of the present invention.
In the present embodiment, single-chip microcomputer includes the first timer and second timer using cascade mode connection, its
In,
First timer produces the pulse signal of specific frequency and exported to outside；
Second timer counts to pulse signal caused by first timer, when count value reaches preset value,
Triggering interrupt service routine is modified to the related register of first timer and second timer, to set follow-up output arteries and veins
The frequency and number of punching.
In the present embodiment, single-chip microcomputer for example can be STM32 single-chip microcomputers, naturally it is also possible to it is other single-chip microcomputers,
Do not limit herein.
In the present embodiment, first timer includes the first pre-divider and the first counter register, wherein, first is pre-
Frequency divider divides to internal clocking, and is supplied to the first counter register to be counted the signal after frequency dividing.
In the present embodiment, the first counter register includes clear input and counting input end, wherein, it is defeated when resetting
By count value be zero clearly when entering effective, when reset input it is invalid when count value is continuously increased the maximum until reaching bit wide permission
Value, and overflow return to zero after reaching a maximum value.
In the present embodiment, first timer also includes first comparator and the second comparator, wherein, the first counting is posted
The count value of storage is connected to first comparator and the second comparator simultaneously.
In the present embodiment, first timer also includes the first comparand register, wherein, the value of the first comparand register
First comparator is connected to, and compared with the count value of the first counter register, and comparative result is OCREF signals.
In the present embodiment, first timer also includes automatic reload registers, wherein, the value of automatic reload registers
The second comparator is input to, and compared with the count value of the first counter register.
In the present embodiment, the second comparator is to the count value of the first counter register and the value of automatic reload registers
It is compared, if the two is equal, the output signal of the second comparator resets the count value of the first counter register.
In the present embodiment, first timer also includes the first output module, wherein, OCREF signals are defeated by first
Export to form actual pulse output signals from I/O port after going out module, so that the stepper motor driver being connected with single-chip microcomputer makes
With.
In the present embodiment, second timer includes the second pre-divider and the second counter register, wherein, second is pre-
Frequency divider receives the OCREF signals of its output from first comparator and OCREF signals is divided in advance, and by after frequency dividing
Output of pulse signal to the second counter register, the second counter register counts to the pulse number of output.
In the present embodiment, second timer also includes the second comparand register and the 3rd comparator, wherein, the second ratio
The 3rd comparator is connected to compared with register, the count value of the second counter register is exported to the 3rd comparator, the 3rd comparator pair
The value of second comparand register and the count value of the second counter register are compared, and are touched producing to interrupt when the two is equal
Signal.
In the present embodiment, on the one hand interrupt trigger signal is connected to the clear input of the second counter register, to it
It is zeroed out, on the other hand triggers the interrupt service routine of the second timer in single-chip microcomputer, makes it to first timer and the
The related register of two timers is made an amendment, with the pulse output frequencies and number after setting.
Wherein, the operation principle of the single-chip microcomputer shown in Fig. 1 is as follows：
The internal clocking of single-chip microcomputer is supplied to first timer, after the frequency dividing by the first pre-divider, to the first meter
Number registers are counted, and the first counter register has individual clear input, by it by the first counter register when initial
Value is 0 clearly, and during the pulse signal for first pre-divider of often arriving afterwards, the value of the first counter register will increase by 1, should
Value is compared with the value of the first comparand register, when the value of the first counter register is less than the value of the first comparand register,
The output OCREF signals of first comparator are high level.With the increase of the value of the first counter register, the first meter is finally had
The value of number register is equal to the value step-down of the value, now OCREF signals of the first comparand register, is low level.OCREF signals pass through
Cross the first output module to be output on I/O port, i.e., externally generate pulse signal.The value of first counter register simultaneously with it is automatic
The value of reload registers is compared, and when the value of the first counter register is equal to the value of automatic reload registers, second compares
Device produces reset signal, is zero clearly by the value of the first counter register, and the first counter register is started from scratch again to be counted up,
Carry out next pulse output.
The output signal OCREF of first comparator is exported to second timer as clock pulses simultaneously, pre- by second
After the frequency dividing of frequency divider, the second counter register is inputed to, the value of the second counter register can be with OCREF signal output
And increase, the value is compared with the value of the second comparand register, when the value of the second counter register compares deposit equal to second
During the value of device, interrupt trigger signal is produced, the signal can trigger the interrupt service routine of second timer, in interrupt service routine
In, the first comparand register in first timer and automatic reload registers are changed, therefore change follow-up pulse output
Frequency.The second comparand register in second timer is also changed simultaneously, and the value of the register is determined after first timer
The interrupt service routine of second timer can just be triggered again by exporting how many individual pulses.It can also turn off in interrupt service routine
First timer, to stop outwards entering horizontal pulse output.The interrupt trigger signal of second timer be also connected to simultaneously its second
The clear input of counter register, the second counter register can quilt when so entering second timer interrupt service routine every time
Clearing restarts to count.
Pulse output is completed by timer hardware in a kind of single-chip microcomputer provided by the invention, and software is only needed default
Pulse number output can just intervene to be modified to follow-up pulse frequency, number when finishing, in output preset frequency, individual
During several pulse signals, completely without the operation of software, than believing if desired for 100 frequencies of output for 200KHz pulses
Number, then the cycle for triggering interrupt service routine is 500us, and therefore, the complete having time of scm software removes completion system needs
Other communication, detection, display, control etc. function, realize the soft or hard piece optimization of system, enormously simplify hardware configuration, drop
Low system cost.
It is worth noting that, in above-described embodiment, included unit is simply divided according to function logic,
But above-mentioned division is not limited to, as long as corresponding function can be realized；In addition, the specific name of each functional unit
Only to facilitate mutually distinguish, the protection domain being not intended to limit the invention.
In addition, one of ordinary skill in the art will appreciate that realize all or part of step in the various embodiments described above method
It is that by program the hardware of correlation can be instructed to complete, corresponding program can be stored in a computer-readable storage and be situated between
In matter, described storage medium, such as ROM/RAM, disk or CD.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement made within refreshing and principle etc., should be included in the scope of the protection.
Claims (10)
1. a kind of single-chip microcomputer, it is characterised in that the single-chip microcomputer includes the first timer and second using cascade mode connection
Timer, wherein,
The first timer produces the pulse signal of specific frequency and exported to outside；
The second timer counts to pulse signal caused by the first timer, when count value reaches preset value
When, triggering interrupt service routine is modified to the related register of the first timer and the second timer, to set
The frequency and number of fixed follow-up output pulse.
2. single-chip microcomputer as claimed in claim 1, it is characterised in that the first timer includes the first pre-divider and first
Counter register, wherein, first pre-divider divides to internal clocking, and the signal after frequency dividing is supplied to described
First counter register is counted.
3. single-chip microcomputer as claimed in claim 2, it is characterised in that first counter register includes clear input and meter
Number input, wherein, when reset input it is effective when by count value be zero clearly, when reset input it is invalid when be continuously increased count value
Maximum until reaching bit wide permission, and overflowed after the maximum is reached and return to zero.
4. single-chip microcomputer as claimed in claim 3, it is characterised in that the first timer also includes first comparator and second
Comparator, wherein, the count value of first counter register is connected to the first comparator and described second simultaneously and compared
Device.
5. single-chip microcomputer as claimed in claim 4, it is characterised in that the first timer also includes the first comparand register,
Wherein, the value of first comparand register is connected to the first comparator, and with the counting of first counter register
Value is compared, and comparative result is OCREF signals.
6. single-chip microcomputer as claimed in claim 5, it is characterised in that the first timer also includes automatic reload registers,
Wherein, the value of the automatic reload registers is input to second comparator, and with the counting of first counter register
Value is compared.
7. single-chip microcomputer as claimed in claim 6, it is characterised in that second comparator is to first counter register
Count value and the value of the automatic reload registers are compared, if the two is equal, the output letter of second comparator
Number the count value of first counter register is reset.
8. single-chip microcomputer as claimed in claim 7, it is characterised in that the first timer also includes the first output module, its
In, the OCREF signals export to form actual pulse output signals after first output module from I/O port, for
The connected stepper motor driver of the single-chip microcomputer uses.
9. single-chip microcomputer as claimed in claim 8, it is characterised in that the second timer includes the second pre-divider and second
Counter register, wherein, second pre-divider receives the OCREF signals of its output simultaneously from the first comparator
The OCREF signals are divided in advance, and by the output of pulse signal after frequency dividing to second counter register, described
Two counter registers count to the pulse number of output.
10. single-chip microcomputer as claimed in claim 9, it is characterised in that the second timer also includes the second comparand register
With the 3rd comparator, wherein, second comparand register is connected to the 3rd comparator, second counter register
Count value is exported to the 3rd comparator, value and second meter of the 3rd comparator to second comparand register
The count value of number register is compared, and is producing interrupt trigger signal when the two is equal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711047504.9A CN107703819A (en) | 2017-10-31 | 2017-10-31 | A kind of single-chip microcomputer |
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| CN201711047504.9A CN107703819A (en) | 2017-10-31 | 2017-10-31 | A kind of single-chip microcomputer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110244588A (en) * | 2018-03-09 | 2019-09-17 | 华大半导体有限公司 | Multifunctional timer |
| CN111122969A (en) * | 2020-03-10 | 2020-05-08 | 南京立超软件科技有限公司 | High-precision pulse output method based on three-phase electric energy meter |
| CN115001325A (en) * | 2022-04-20 | 2022-09-02 | 北京瑞祺皓迪技术股份有限公司 | Timed interrupt control method and multi-step motor synchronous control system and method |
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| CN111122969A (en) * | 2020-03-10 | 2020-05-08 | 南京立超软件科技有限公司 | High-precision pulse output method based on three-phase electric energy meter |
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Application publication date: 20180216 |