CN107680933A - MOS type power device and its manufacture method - Google Patents
MOS type power device and its manufacture method Download PDFInfo
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- CN107680933A CN107680933A CN201610624767.0A CN201610624767A CN107680933A CN 107680933 A CN107680933 A CN 107680933A CN 201610624767 A CN201610624767 A CN 201610624767A CN 107680933 A CN107680933 A CN 107680933A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 75
- 238000010276 construction Methods 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 239000002019 doping agent Substances 0.000 claims abstract description 6
- 230000008021 deposition Effects 0.000 claims description 26
- 239000012535 impurity Substances 0.000 claims description 21
- 238000001259 photo etching Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 5
- 230000000717 retained effect Effects 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000005192 partition Methods 0.000 claims description 2
- MXSJNBRAMXILSE-UHFFFAOYSA-N [Si].[P].[B] Chemical group [Si].[P].[B] MXSJNBRAMXILSE-UHFFFAOYSA-N 0.000 claims 1
- 238000005530 etching Methods 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of MOS type power device and its manufacture method.Methods described includes：The first insulating medium layer, the first semiconductor layer, the second insulating medium layer and the second semiconductor layer are sequentially generated above substrate, forms the first sandwich construction；It is etched on the first sandwich construction, until exposing the subregion of the first insulating medium layer, forms the second sandwich construction；The implanted dopant into substrate so that form well region and source region in the substrate, obtain the 3rd sandwich construction；In the insulating medium layer of disposed thereon the 3rd of the 3rd sandwich construction, the 4th sandwich construction is formed；The 4th sandwich construction is etched by self aligned mode, forms connecting hole, forms the 5th sandwich construction；In the disposed thereon metal level of the 5th sandwich construction, emitter stage is formed.So, avoid and offset, ensure that the uniformity and stability of MOS type power device performance parameter.
Description
Technical field
The present invention relates to semiconductor applications, and in particular to a kind of MOS type power device and its manufacture method.
Background technology
MOS refers in particular to a kind of metal-oxide-semiconductor structure, every device with this structures of MOS, we term it
MOS type power device.Existing MOS type power device such as IGBT (Insulated Gate Bipolar Transistor, absolutely
Edge grid bipolar transistor), MOSFET (Metal Oxide Semiconductor Field Effect Transistor, gold
Belong to oxide semiconductor-type FET), mos capacitance etc., using voltage control mode, have that switching speed is fast, control circuit
The advantages that simple, had a very wide range of applications in modern power electronic system.
Fig. 1 is the structural representation of existing MOS type power device.As shown in figure 1, existing MOS type power device bag
Include silicon substrate 101, dielectric 102, grid 103, well region 104, source region 105, dielectric 106 and metal emitting 107.Figure
2a- Fig. 2 h are the schematic diagram of the manufacturing process of existing MOS type power device.The manufacturing process of existing MOS type power device
Generally include following steps：
In the table of the first type (for example, N-type, manufactured power device is N-type MOS power devices) Semiconductor substrate 201
Face, one layer of insulating medium layer 202 is grown, such as Fig. 2 a；
On the surface of insulating medium layer 202, one layer of polysilicon layer 203 is deposited, and is doped, as grid, such as Fig. 2 b；
Photoresist, photoetching development are covered, then etches polysilicon gate, grid step 203 is formed, then removes photoresist,
Such as Fig. 2 c；
Second-Type (for example, p-type) impurity is injected in autoregistration, and carries out High temperature diffusion, well region 204 is formed, such as Fig. 2 d；
The first type impurity is injected in autoregistration, shallow source region 205 is formed, such as Fig. 2 e；
Insulating medium layer 206 is deposited, such as Fig. 2 f；
Photoresist is covered, alignment grid step carries out photoetching development, then etches insulating medium layer 206, forms connecting hole,
Etch again backing material until source region cut through, remove remaining photoresist, such as Fig. 2 g；
Deposited metal layer 207, emitter stage is formed, such as Fig. 2 h.
This is arrived, completes the manufacturing process of whole mos semiconductor power device.
In the manufacturing process of above-mentioned existing mos semiconductor power device, to ensure mos semiconductor power device
Each Rotating fields precisely form, and each Rotating fields of mos semiconductor power device all pass through the step of photoetching development pre-structure therewith
It is aligned.Operation principle and board ability are limited to, this lithography alignment is inevitably present to inclined problem.It is common at present
Lithography alignment deviation in the range of 0.2um to 1um.Connecting hole in existing MOS type power unit structure, is exactly based on alignment
What the step of polycrystalline grid was lithographically formed, therefore, inevitably, the relative position of connecting hole and polysilicon gate is present partially
Move.
This skew may bring the problem of two aspects：1st, different times manufacture device, its offset direction and away from
From difference, cause device architecture inconsistent, performance parameter is unstable；2nd, to ensure the security isolation between grid and emitter stage,
Need to consider maximum offset, so, the distance between connecting hole and grid must be very big in design.In existing manufacture work
In skill, this usual distance can not be less than 2um.Therefore, the size of whole MOS type power device is larger, and manufacturing cost is higher.
The content of the invention
It is an object of the invention to provide the MOS type power device that a kind of technique is simple, cost is low and its manufacture method.
To achieve the above object, the invention provides a kind of manufacture method of MOS type power device, methods described to include：
The first insulating medium layer, the first semiconductor layer, the second insulating medium layer and the second semiconductor are sequentially generated above substrate
Layer, form the first sandwich construction；It is etched on first sandwich construction, until exposing first insulating medium layer
Subregion, form the second sandwich construction；The implanted dopant into the substrate so that well region and source are formed in the substrate
Area, obtain the 3rd sandwich construction；In the insulating medium layer of disposed thereon the 3rd of the 3rd sandwich construction, the 4th multilayer knot is formed
Structure；The 4th sandwich construction is etched by self aligned mode so that second semiconductor layer is possible to determine when the sample has been completely etched,
3rd insulating medium layer is retained in the part of first semiconductor layer and the second insulating medium layer medial surface, shape
It is eclipsed and cuts through into the subregion of connecting hole, and the source region, the subregion of the well region is exposed, and forms the 5th multilayer knot
Structure；In the disposed thereon metal level of the 5th sandwich construction, emitter stage is formed.
Alternatively, it is described to be etched on first sandwich construction, until the part of first insulating medium layer
Region is exposed, formed the second sandwich construction the step of include：By way of photoetching development on first sandwich construction
It is etched, until the subregion of first insulating medium layer is exposed, forms the second sandwich construction.
Alternatively, the implanted dopant into the substrate so that well region and source region are formed in the substrate, obtains the
The step of three sandwich constructions, includes：The first type impurity is injected into the substrate, forms well region；Second is injected into the well region
Type impurity, top in the well region and forms source region with the first insulating medium layer adjacent.
Alternatively, the type of the first type impurity and the type of the substrate on the contrary, and with the Second-Type impurity
Type is opposite.
Alternatively, described the step of being etched by self aligned mode to the 4th sandwich construction, includes：Pass through
Self aligned mode is etched to the 3rd insulating medium layer so that the 3rd insulating medium layer is only described the first half
The part of conductor layer and the second insulating medium layer medial surface is retained, and the subregion of the well region is exposed, the company of being formed
Connect hole；Second semiconductor layer is etched by self aligned mode so that second semiconductor layer is lost completely
Carve；The source region is etched by self aligned mode, so that the source region is located at the subregion quilt below connecting hole
Etching is worn, and the subregion of the well region is exposed.
Alternatively, first semiconductor layer and second semiconductor layer are generated by polysilicon doping.
Alternatively, described the step of being etched by self aligned mode to the 4th sandwich construction, includes：Pass through
Self aligned mode carries out dry etching to the 4th sandwich construction.
The present invention also provides a kind of MOS type power device.The MOS type power device includes substrate, well region, source region, the
One insulating medium layer, the first semiconductor layer, the second insulating medium layer, the 3rd insulating medium layer and metal level, wherein, the gold
Belonging to layer includes covering part and deposition portion, and the well region is formed at the outer of the lower section in the deposition portion and the lower section in the deposition portion
Side, and part covers the substrate；The source region is formed at the upper of the well region and the outside in the deposition portion, and
Part covers the outside in the deposition portion；First insulating medium layer covers well region, the source region and the substrate,
And it is formed at the outside in the deposition portion；First semiconductor layer is formed on first insulating medium layer, and described second
Insulating medium layer is formed on first semiconductor layer, and first semiconductor layer and second insulating medium layer are formed at
The outside in the deposition portion, and be connected respectively by the 3rd insulating medium layer with the deposition portion；The covering part covering
In on second insulating medium layer and the 3rd insulating medium layer.
Alternatively, the 3rd insulating medium layer and the joint face in the deposition portion are globoidal structure.
Alternatively, the 3rd insulating medium layer is boron-phosphorosilicate glass.
It is other after grid step is formed during MOS type power device is formed by above technical scheme
In etching, carried out using self-aligned manner.So, the connecting hole of formation and the complete phase of the distance between the grid on the outside of it
Together.Therefore, avoid and offset, ensure that the uniformity and stability of MOS type power device performance parameter, and reduce
The size of trap, so as to reduce the size of MOS type power device, gully density is improved, the conduction voltage drop of device is reduced, enters
And the loss of MOS type power device is reduced, the technological process of manufacture is simplified, reduces manufacturing cost.
Other features and advantages of the present invention will be described in detail in subsequent specific embodiment part.
Brief description of the drawings
Accompanying drawing is for providing a further understanding of the present invention, and a part for constitution instruction, with following tool
Body embodiment is used to explain the present invention together, but is not construed as limiting the invention.In the accompanying drawings：
Fig. 1 is the structural representation of the MOS type power device of prior art.
Fig. 2 a- Fig. 2 h are the schematic diagram of the manufacturing process of existing MOS type power device.
Fig. 3 is the flow chart of the manufacture method for the MOS type power device that an illustrative embodiments of the invention provide.
Fig. 3 a-3i are the schematic diagram of the manufacturing process for the MOS type power device that an illustrative embodiments of the invention provide.
Fig. 3 i are the structural representation for the MOS type power device that an illustrative embodiments of the invention provide.
Embodiment
The embodiment of the present invention is described in detail below in conjunction with accompanying drawing.It should be appreciated that this place is retouched
The embodiment stated is merely to illustrate and explain the present invention, and is not intended to limit the invention.
Embodiments of the present invention are described with reference now to accompanying drawing, similar element numbers represent similar element in accompanying drawing.
The manufacture method of MOS type power device of the present invention is described in detail with reference to reference to figure 3 and Fig. 3 a-3i.Fig. 3 is the present invention one
The flow chart of the manufacture method for the MOS type power device that illustrative embodiments provide.As shown in figure 3, methods described can wrap
Include following steps.
Step S101：The first insulating medium layer 302, the first semiconductor layer 303, second are sequentially generated above substrate 301
The semiconductor layer 309 of insulating medium layer 308 and second, the first sandwich construction is formed, as shown in Fig. 3 a- Fig. 3 b.In this step
In, after the first semiconductor layer 303 are formed, it is doped on the first semiconductor layer 303.First semiconductor layer 303, second is exhausted
The semiconductor layer 309 of edge dielectric layer 308 and second forms a kind of sandwich structure, i.e. the upper and lower of the second insulating medium layer 308 is equal
For semiconductor layer, the second insulating medium layer 308 has been effectively isolated the first semiconductor layer 303 and the second semiconductor layer 309.It is described
First sandwich construction includes substrate 301, insulating medium layer 302, the first semiconductor layer 303, the second insulating medium layer 308 and the
Two semiconductor layers 309, as shown in Figure 3 b.
First semiconductor layer 303, second layer semiconductor 309 can be that polysilicon doping generates, so that the first semiconductor
The 303, second semiconductor layer 309 of layer has good service behaviour.
Step S102：It is etched on the first sandwich construction, until exposing the part area of the first insulating medium layer 302
Domain, form the second sandwich construction.In one embodiment of the present invention, can be by way of photoetching development in the first multilayer knot
It is etched on structure so that the subregion of the first insulating medium layer 302 is exposed, and forms the second sandwich construction.This second
In sandwich construction, the subregion that the first insulating medium layer 302 is exposed is located at the first semiconductor layer 303 and the second dielectric
The inner side of layer 308, as shown in Figure 3 c.
Specifically, photoresist can be coated on the second semiconductor layer 309, etches successively by way of photoetching development
Two semiconductor layers 309, the second insulating medium layer 308, the first semiconductor layer 303, and cause the part of the first insulating medium layer 302
Region is exposed, and forms grid step.Second sandwich construction can include substrate 301, insulating medium layer 302, the first semiconductor
The structure that the 303, second insulating medium layer 308 of layer and the second semiconductor layer 309 are formed after the etching of this step, such as Fig. 3 c
It is shown.In addition, it is necessary to remaining photoresist on the second semiconductor layer 309 be removed in addition, to avoid remaining light after the completion of etching
Photoresist influences being normally carried out for subsequent technique.
Step S103：The implanted dopant into substrate 301 so that form well region 304 and source region 305 in the substrate, obtain the
Three sandwich constructions.As shown in Fig. 3 d- Fig. 3 e.In the illustrative embodiments of the present invention, the step can include：To substrate
The first type impurity of injection in 301, by forming well region 304 after High temperature diffusion, as shown in Figure 3 d；Second is injected into well region 304
Type impurity, top in well region 304 and forms source region 305 with the adjacent of the first insulating medium layer 302, as shown in Figure 3 e.Example
Such as, the first type impurity is p type impurity, and Second-Type impurity is N-type impurity.It is exhausted that 3rd sandwich construction can include substrate 301, first
Edge dielectric layer 302, the first semiconductor layer 303, well region 304, source region 305, the second insulating medium layer 308 and the second semiconductor layer
309 structures formed after this step, as shown in Figure 3 e.
Wherein, the type of the first type impurity with the type of substrate 301 on the contrary, and opposite with the type of Second-Type impurity.
It is exactly that the type of Second-Type impurity is identical or related with the type of substrate 301.For example, the type of the first type impurity is p-type, the
The type of two type impurity and the type of substrate 301 are all N-type.
Step S104：In the insulating medium layer 306 of disposed thereon the 3rd of the 3rd sandwich construction, the 4th sandwich construction is formed.
Wherein, the 3rd insulating medium layer 306 can be boron-phosphorosilicate glass.4th sandwich construction can include the insulation of substrate 301, first and be situated between
Matter layer 302, the first semiconductor layer 303, well region 304, source region 305, the second insulating medium layer 308, the 3rd insulating medium layer 306 with
And second structure that is formed after this step of semiconductor layer 309, as illustrated in figure 3f.
Step S105：The 4th sandwich construction is etched by self aligned mode so that the quilt of the second semiconductor layer 309
It is fully etched, the 3rd insulating medium layer 306 is in the first semiconductor layer 303 and the part quilt of the medial surface of the second insulating medium layer 308
Retain, form connecting hole, and the subregion of source region 305 is eclipsed and cut through, the subregion of well region 304 is exposed, and forms the 5th
Sandwich construction.5th sandwich construction can include substrate 301, the first insulating medium layer 302, the first semiconductor layer 303, well region
304th, source region 305, the second insulating medium layer 308, the 3rd insulating medium layer 306 and the second semiconductor layer 309 pass through this step
The structure formed afterwards, as illustrated in figure 3h.
In one embodiment of the present invention, the 4th sandwich construction is etched and can included by self aligned mode
Following steps：
Step S1051：The 3rd insulating medium layer 306 is etched by self aligned mode so that the 3rd insulation is situated between
Matter layer 306 is only retained in the part of the first semiconductor layer 303 and the medial surface of the second insulating medium layer 308, the part of well region 304
Region is exposed, and forms connecting hole, and the connecting hole is autoregistration connecting hole, as shown in figure 3g.In this step, can use
The insulating medium layer 306 of autoregistration dry etching the 3rd, and the 3rd insulating medium layer 306 is only remained with grid platform after the completion of etching
The part of rank side (namely medial surface of the first semiconductor layer 303 and the second insulating medium layer 308).
Step S1052：The second semiconductor layer 309 is etched by self aligned mode so that the second semiconductor layer
309 are possible to determine when the sample has been completely etched.In this step, the second semiconductor layer 309 is now completely etched away from the second insulating medium layer 308, such as
Shown in Fig. 3 h.
Step S1053：Source region 305 is etched by self aligned mode, so that source region 305 is located at below connecting hole
Subregion be eclipsed and cut through, the subregion of well region 304 is exposed, as illustrated in figure 3h.
Step S106：In the disposed thereon metal level 307 of the 5th sandwich construction, emitter stage is formed, as shown in figure 3i.So far
Complete the manufacturing process of the MOS type power device of the present invention.
It is understood that the manufacture method of above-mentioned MOS type power device is not limited to manufacture N-type or p-type MOS type power
Device.Specifically, when the substrate 301 provided is the substrate of n-type doping, the above method is used for manufacturing N-type MOS type power device
Part；And when the substrate 301 provided is the substrate of p-type doping, the above method is used for manufacturing p-type MOS type power device.Specifically
The substrate of which kind of model is selected depending on actual use situation.
It is other after grid step is formed during MOS type power device is formed by above technical scheme
In etching, carried out using self-aligned manner.So, the connecting hole of formation and the complete phase of the distance between the grid on the outside of it
Together.Therefore, avoid and offset, ensure that the uniformity and stability of MOS type power device performance parameter, and reduce
The size of trap, so as to reduce the size of MOS type power device, gully density is improved, the conduction voltage drop of device is reduced, enters
And the loss of MOS type power device is reduced, the technological process of manufacture is simplified, reduces manufacturing cost.
The structure of MOS type power device provided by the invention described in detail below.Fig. 3 i are an exemplary implementation of the invention
The structural representation for the MOS type power device that mode provides.As shown in figure 3i, MOS type power device of the invention can include
Substrate 301, well region 304, source region 305, the first insulating medium layer 302, the first semiconductor layer 303, the second insulating medium layer 308,
3rd insulating medium layer 306 and metal level 307.
Wherein, metal level 307 includes covering part 307a and deposition portion 307b, and well region 304 is formed under deposition portion 307b
Side and the outside of deposition portion 307b lower section, and part covering substrate 301.
Source region 305 is formed at the upper of well region 304 and deposition portion 307b outside, and part covering deposition portion
307b outside.
First insulating medium layer 302 covering well region 304, source region 305 and substrate 301, and it is formed at deposition portion 307b's
Outside.
First semiconductor layer 303 is formed on the first insulating medium layer 302, and the second insulating medium layer 308 is formed at first
On semiconductor layer 303.First semiconductor layer 303 and the second insulating medium layer 308 are formed at deposition portion 307b outside, and respectively
It is connected by the 3rd insulating medium layer 306 with deposition portion 307b.
Covering part 307a is covered on the second insulating medium layer 308 and the 3rd insulating medium layer 306.
In one embodiment of the present invention, the 3rd insulating medium layer 306 and deposition portion 307b joint face is cambered surface knot
Structure (referring to Fig. 3 i).3rd insulating medium layer 306 is only remained on the inside of connecting hole, and is cambered surface with deposition portion 307b joint face
Structure, without step.So allowing for the 3rd insulating medium layer 306 itself size can be made than step of the prior art
Shape is smaller, so as to reduce the distance between connecting hole and grid, reduces the size of device, improves gully density, reduces
The conduction voltage drop of device.In addition, the size of the 3rd insulating medium layer 306 is smaller, and after electricity on MOS type power device, electric current
Source region 305 quickly can be flowed through from well region 304, flow to the emitter stage of metal level 307, so as to reduce whole MOS type power device
The possibility of failure.
Wherein, the 3rd insulating medium layer 306 can be boron-phosphorosilicate glass, and the first semiconductor layer 303 can be mixed for polysilicon
Miscellaneous generation.When selection substrate 301 for n-type doping substrate when, it is possible to produce N-type MOS type power device；And when selection
When substrate 301 is the substrate of p-type doping, it is possible to produce p-type MOS type power device.
By taking N-type MOS type power device as an example, in an embodiment of MOS type power device of the present invention, the doping of the first type
Adulterated for N, substrate 301 is N-type substrate.First insulating medium layer 302 is the silica of growth, and its thickness is 0.1um.First
Semiconductor layer 303 is DOPOS doped polycrystalline silicon in the thick N-types of 0.6um, and the second insulating medium layer 308 is the thick silica of 0.6um.Trap
The well region that area 304 is adulterated for p-type, junction depth 5um.Source region 305 be n-type doping source region, junction depth 0.3um.3rd dielectric
Layer 306 is the thick boron-phosphorosilicate glass of 1.5um.Metal level 307 is metallic aluminium.
And in one embodiment, when photoetching development forms grid step, the distance that can design two steps is
6um.After being etched using self-registered technology, the 3rd insulating medium layer 306 its lateral dimension of grid step side is about
0.7um, the connection hole width of formation is 4.6um, and the depth that substrate 301 is etched by connecting hole is 0.5um.
It is other after grid step is formed during MOS type power device is formed by above technical scheme
In etching, carried out using self-aligned manner.So, the connecting hole of formation and the complete phase of the distance between the grid on the outside of it
Together.Therefore, avoid and offset, ensure that the uniformity and stability of MOS type power device performance parameter, and reduce
The size of trap, so as to reduce the size of MOS type power device, gully density is improved, the conduction voltage drop of device is reduced, enters
And the loss of MOS type power device is reduced, the technological process of manufacture is simplified, reduces manufacturing cost.
Above in association with preferred forms, invention has been described, but the invention is not limited in reality disclosed above
Mode is applied, and modification, the equivalent combinations that the various essence according to the present invention are carried out should be covered.It is described in detail above in association with accompanying drawing
The preferred embodiment of the present invention, still, the present invention are not limited to the detail in above-mentioned embodiment, the present invention's
In range of the technology design, a variety of simple variants can be carried out to technical scheme, these simple variants belong to this hair
Bright protection domain.
It is further to note that each particular technique feature described in above-mentioned embodiment, in not lance
In the case of shield, it can be combined by any suitable means.In order to avoid unnecessary repetition, the present invention to it is various can
The combination of energy no longer separately illustrates.
In addition, various embodiments of the present invention can be combined randomly, as long as it is without prejudice to originally
The thought of invention, it should equally be considered as content disclosed in this invention.
Claims (10)
1. a kind of manufacture method of MOS type power device, it is characterised in that methods described includes：
The first insulating medium layer, the first semiconductor layer, the second insulating medium layer are sequentially generated above substrate and the second half is led
Body layer, form the first sandwich construction；
It is etched on first sandwich construction, until expose the subregion of first insulating medium layer, forms the
Two sandwich constructions；
The implanted dopant into the substrate so that well region and source region are formed in the substrate, obtains the 3rd sandwich construction；
In the insulating medium layer of disposed thereon the 3rd of the 3rd sandwich construction, the 4th sandwich construction is formed；
The 4th sandwich construction is etched by self aligned mode so that second semiconductor layer is lost completely
Carve, the 3rd insulating medium layer is protected in the part of first semiconductor layer and the second insulating medium layer medial surface
Stay, form connecting hole, and the subregion of the source region is eclipsed and cut through, the subregion of the well region is exposed, and forms the 5th
Sandwich construction；
In the disposed thereon metal level of the 5th sandwich construction, emitter stage is formed.
2. according to the method for claim 1, it is characterised in that it is described to be etched on first sandwich construction, directly
The step of being exposed to the subregion of first insulating medium layer, forming the second sandwich construction includes：
It is etched by way of photoetching development on first sandwich construction, until the portion of first insulating medium layer
Subregion is exposed, and forms the second sandwich construction.
3. manufacture method according to claim 1, it is characterised in that the implanted dopant into the substrate so that
The step of well region and source region are formed in the substrate, obtains three sandwich constructions includes：
The first type impurity is injected into the substrate, forms well region；
Inject Second-Type impurity into the well region, top in the well region and adjacent with first insulating medium layer
Place forms source region.
4. manufacture method according to claim 3, it is characterised in that the type of the first type impurity and the substrate
Type is on the contrary, and opposite with the type of the Second-Type impurity.
5. manufacture method according to claim 1, it is characterised in that it is described by self aligned mode to more than the described 4th
The step of Rotating fields are etched includes：
The 3rd insulating medium layer is etched by self aligned mode so that the 3rd insulating medium layer is only in institute
The part for stating the first semiconductor layer and the second insulating medium layer medial surface is retained, and the subregion of the well region is revealed
Go out, form connecting hole；
Second semiconductor layer is etched by self aligned mode so that second semiconductor layer is lost completely
Carve；
The source region is etched by self aligned mode, so that the source region is located at the part area below the connecting hole
Domain, which is eclipsed, to be cut through, and the subregion of the well region is exposed.
6. manufacture method according to claim 1, it is characterised in that first semiconductor layer and second semiconductor
Layer is generated by polysilicon doping.
7. manufacture method according to claim 1, it is characterised in that it is described by self aligned mode to more than the described 4th
The step of Rotating fields are etched includes：
Dry etching is carried out to the 4th sandwich construction by self aligned mode.
8. a kind of MOS type power device, it is characterised in that the MOS type power device includes substrate, well region, source region, first exhausted
Edge dielectric layer, the first semiconductor layer, the second insulating medium layer, the 3rd insulating medium layer and metal level,
Wherein, the metal level includes covering part and deposition portion, and the well region is formed at the lower section in the deposition portion and described heavy
The outside of the lower section in product portion, and part covers the substrate；
The source region is formed at the upper of the well region and the outside in the deposition portion, and part covers the deposition portion
Outside；
First insulating medium layer covers well region, the source region and the substrate, and is formed at the deposition portion
Outside；
First semiconductor layer is formed on first insulating medium layer, and second insulating medium layer is formed at described
In semi-conductor layer, first semiconductor layer and second insulating medium layer are formed at the outside in the deposition portion, and divide
It is not connected by the 3rd insulating medium layer with the deposition portion；
The covering part is covered on second insulating medium layer and the 3rd insulating medium layer.
9. MOS type power device according to claim 8, it is characterised in that the 3rd insulating medium layer sinks with described
The joint face in product portion is globoidal structure.
10. MOS type power device according to claim 8, it is characterised in that the 3rd insulating medium layer is boron phosphorus silicon
Glass.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109887880A (en) * | 2019-01-04 | 2019-06-14 | 长江存储科技有限责任公司 | A kind of semiconductor connection structure and preparation method thereof |
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