CN107645121B - Ridge array semiconductor laser and its making method - Google Patents
Ridge array semiconductor laser and its making method Download PDFInfo
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- CN107645121B CN107645121B CN201610578278.6A CN201610578278A CN107645121B CN 107645121 B CN107645121 B CN 107645121B CN 201610578278 A CN201610578278 A CN 201610578278A CN 107645121 B CN107645121 B CN 107645121B
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Abstract
The invention provides a ridge array semiconductor laser, which comprises a substrate and an epitaxial structure formed on the substrate, wherein a ridge semiconductor layer is arranged at the top of the epitaxial structure and comprises a plurality of ridge parts, and the widths of the ridge parts are not equal. According to the ridge array semiconductor laser provided by the invention, the plurality of ridge parts are arranged at the top of the epitaxial structure, and the widths of the plurality of ridge parts are unequal, so that the temperature difference between the center of the active region and the two sides of the active region can be reduced when the laser works, the temperature distribution of the whole laser structure is uniform, and the output characteristics of the laser when the laser works are consistent.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a ridge array semiconductor laser and a manufacturing method thereof.
Background
Gallium nitride (GaN) -based lasers are a very important based optoelectronic device, and since the light waves emitted by the GaN-based lasers cover the wavelength band from ultraviolet light to green light, the GaN-based lasers have important application values in high-density optical information storage, projection display, laser printing, underwater communication, activation of biochemical reagents and medical treatment.
In the existing semiconductor laser, the gan-based laser adopts a ridge waveguide structure, which can limit light and current in the direction parallel to the junction, so that the injected current is limited in the active region under the ridge, the lateral diffusion of carriers is limited, and the threshold current is reduced. However, for the conventional gan-based laser structure, the ridge waveguide layer generates a high temperature rise due to a large threshold current and poor thermal conductivity of the substrate, and large temperature steps are formed inside and outside the ridge. For GaN-based lasers, the series resistance is large, almost all comes from the P-type AlGaN confinement layer, and the P confinement layer is narrow, so the highest temperature in the laser is usually distributed in the P confinement layer of the laser. The P limiting layer of the laser is adjacent to the active region, and the temperature difference between the P limiting layer and the active region is small, so that the temperature distribution of the internal structure of the laser is uneven. The temperature steps inside and outside the ridge affect the limitation of the waveguide on the high-order mode of the laser, the threshold current is reduced, the slope efficiency is increased, the temperature rise of the active region can cause the slope efficiency to be seriously reduced, and the application of the laser in actual life and production is seriously affected.
Disclosure of Invention
In order to solve the problems, the ridge array semiconductor laser provided by the invention can reduce the temperature difference between the central temperature of the active region and the temperatures at the two sides of the outer side of the active region, so that the temperature distribution of the whole device structure is uniform and the output characteristics are consistent.
The specific technical scheme provided by the invention is as follows: the ridge array semiconductor laser comprises a substrate and an epitaxial structure formed on the substrate, wherein a ridge semiconductor layer is arranged on the top of the epitaxial structure and comprises a plurality of ridge portions of the array, and the widths of the ridge portions are unequal.
Further, in the plurality of ridge portions of the array, the width of the ridge portions increases in order of position from the middle to both sides.
Furthermore, a plurality of ridge parts of the array are distributed in a left-right symmetrical mode.
Furthermore, among the plurality of ridges of the array, the width of a first ridge positioned at the outermost edge is 10-12 μm; and/or the width of the second ridge part positioned at the middle part is 6-8 mu m; and/or the width of a third ridge part between the first ridge part and the second ridge part is 7-9 mu m.
Further, the heights of the plurality of ridges are equal.
Further, the distance between two adjacent ridge parts in the ridge array is 100-180 nanometers.
Further, epitaxial structure including set up in proper order in buffer layer, lower limiting layer, lower waveguide layer, active layer, electron barrier layer, upper waveguide layer and the last limiting layer on the substrate, it is to go up the limiting layer the ridge semiconductor layer.
Further, a bottom electrode is formed on the bottom of the substrate; a top electrode is formed on the ridge semiconductor layer, a covering layer is arranged between each ridge portion of the ridge semiconductor layer and the top electrode, and an insulating layer is arranged between two sides of each ridge portion of the ridge semiconductor layer and the top electrode.
Further, the substrate is made of N-type self-supporting gallium nitride, the buffer layer is made of N-type doped gallium nitride, the lower limiting layer is made of N-type doped aluminum gallium nitride, the lower waveguide layer is made of N-type doped gallium nitride, the electron blocking layer is made of P-type doped aluminum gallium nitride, the upper waveguide layer is made of P-type doped gallium nitride, the upper limiting layer is made of P-type doped aluminum gallium nitride, the covering layer is made of P-type doped gallium nitride, the insulating layer is made of silicon dioxide, and the active layer is a quantum well and comprises a gallium nitride barrier layer and an indium gallium nitride potential well layer which are alternately grown.
The invention also provides a manufacturing method of the ridge array semiconductor laser, which comprises the following steps:
providing a substrate and growing an epitaxial structure on the top of the substrate;
and etching the epitaxial structure by using an etching process, and forming the ridge-shaped semiconductor layer on the top of the epitaxial structure.
According to the ridge array semiconductor laser provided by the invention, the plurality of ridge parts are arranged at the top of the epitaxial structure, and the widths of the plurality of ridge parts are unequal, so that the temperature difference between the center of the active region and the two sides of the active region can be reduced when the laser works, the temperature distribution of the whole laser structure is uniform, and the output characteristics of the laser when the laser works are consistent.
Drawings
The above and other aspects, features and advantages of embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:
fig. 1 is a schematic structural diagram of a ridge array semiconductor laser of the present invention;
fig. 2 is a schematic structural diagram of a ridge array semiconductor laser according to the present invention;
fig. 3a to 3e are flow charts of fabricating a ridge array semiconductor laser according to the present invention.
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. Rather, these embodiments are provided to explain the principles of the invention and its practical application to thereby enable others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated.
Referring to fig. 1 and 2, the present embodiment provides a ridge array semiconductor laser, including a substrate 10, an epitaxial structure 11 formed on top of the substrate 10; the top of the epitaxial structure 11 has a ridge semiconductor layer 80, and the ridge semiconductor layer 80 includes a plurality of ridge portions 110, 111, 112, 113, 114, wherein widths of the plurality of ridge portions 110, 111, 112, 113, 114 are not equal.
Preferably, among the plurality of ridge portions 110, 111, 112, 113, and 114 of the array, the width of the ridge portions 110, 111, 112, 113, and 114 increases in order from the middle to both sides. The plurality of ridges 110, 111, 112, 113, and 114 of the array are symmetrically distributed. Specifically, as shown in fig. 1, of the plurality of ridge portions 110, 111, 112, 113, 114 of the array, the width of the first ridge portion 110, 111 located at the outermost edge is 10 to 12 μm; the width of the second ridge part 114 positioned at the middle is 6-8 mu m; the third ridge portions 112, 113 located between the first ridge portions 110, 111 and the second ridge portion 114 have a width of 7 to 9 μm. The ridge semiconductor layer 80 has a plurality of ridge portions 110, 111, 112, 113, and 114 having the same height, and the distance between two adjacent ridge portions 110, 111, 112, 113, and 114 is 100 to 180 nm. In an actual manufacturing process, a user may set the height and width of each ridge 110, 111, 112, 113, 114 and the distance between two adjacent ridges 110, 111, 112, 113, 114 as needed.
As a specific example, the ridge array in the present embodiment includes 5 ridge portions, as shown in fig. 1, two first ridge portions 110 and 111 located at the outermost edges, one second ridge portion 114 located at the innermost center, and two third ridge portions 112 and 113 located between the first ridge portions 110 and 111 and the second ridge portion 114. The two third ridge portions 112 and 113 are distributed bilaterally symmetrically with respect to the second ridge portion 114, and the two first ridge portions 110 and 111 are distributed bilaterally symmetrically with respect to the second ridge portion 114. The widths of the first ridge portions 110 and 111 can be selected within a range of 10 to 12 μm, the widths of the third ridge portions 112 and 113 can be selected within a range of 7 to 9 μm, and the width of the second ridge portion 114 can be selected within a range of 6 to 8 μm, and the conditions are satisfied: the widths of the first ridge portions 110 and 111 are larger than the widths of the third ridge portions 112 and 113, and the widths of the third ridge portions 112 and 113 are larger than the width of the second ridge portion 114. Further, the first ridge portions 110, 111, the second ridge portion 114, and the third ridge portions 112, 113 have the same height, and the distance between any two adjacent ridge portions 110, 111, 112, 113, 114 may be 100 to 180 nm.
Referring to fig. 2, the epitaxial structure 11 includes a buffer layer 20, a lower confinement layer 30, a lower waveguide layer 40, an active layer 50, an electron blocking layer 60, an upper waveguide layer 70, and an upper confinement layer 80a, which are sequentially disposed on the top of the substrate 10. The upper stopper layer 80a is a ridge semiconductor layer 80, and a plurality of ridge portions 110, 111, 112, 113, and 114 are formed on the top of the upper stopper layer 80 a. A bottom electrode 12 is formed on the bottom of the substrate 10, a top electrode 14 is formed on the ridge semiconductor layer 80 (upper limiting layer 80a), and a cover layer 13 is provided between each of the plurality of ridge portions 110, 111, 112, 113, and 114 and the top electrode 14; an insulating layer 15 is provided between both sides of each ridge portion 110, 111, 112, 113, 114 and the top electrode 14.
Specifically, the material of the substrate 10 is gallium nitride, sapphire or silicon carbide, and preferably, the material of the substrate 10 is N-type self-supporting gallium nitride. The capping layer 13 is P-type doped gan, which is used to form an ohmic contact with the top electrode 14. The insulating layer 15 is made of silicon dioxide, and is used for preventing current leakage. The bottom electrode 12 and the top electrode 14 are metal electrodes for forming ohmic contact, so as to lead out electrode leads. The buffer layer 20 is made of N-doped gan, and is used for buffering stress generated by lattice mismatch to facilitate growth of the rest of the epitaxial layer. The material of the lower limiting layer 30 is N-type doped aluminum gallium nitride, and the material of the upper limiting layer 80a is P-type doped aluminum gallium nitride, wherein the lower limiting layer 30 is used for limiting the optical field from expanding in the direction towards the substrate 10, and the upper limiting layer 80a is used for limiting the optical field from expanding in the direction away from the substrate 10. The lower waveguide layer 40 is made of N-type doped gallium nitride, the upper waveguide layer 70 is made of P-type doped gallium nitride, and the lower waveguide layer 40 and the upper waveguide layer 70 are used for increasing the limiting effect on current carriers, increasing the distribution of the current carriers in an active region, improving the light limiting factor, reducing the threshold value and increasing the light emitting efficiency. The active layer 50 is a quantum well, and includes 1-10 periods of alternately grown gallium nitride barrier layers and indium gallium nitride potential well layers for providing optical gain. The electron blocking layer 60 is made of P-type doped aluminum gallium nitride, and is used for blocking electrons overflowing from the active layer 50.
Referring to fig. 3a to fig. 3e, this embodiment further provides a method for manufacturing the ridge array semiconductor laser, which takes a gallium nitride-based blue laser with an operating wavelength of 450nm as an example, and the method includes the following steps:
step S1, a substrate 10 is provided and an epitaxial structure 11 is grown on the substrate 10.
Specifically, step S1 includes sequentially depositing the buffer layer 20, the lower confinement layer 30, the lower waveguide layer 40, the active layer 50, the electron blocking layer 60, the upper waveguide layer 70, the upper confinement layer 80a, and the capping layer 13 on the substrate 10 (as shown in fig. 3 a), where the deposition process is a Metal Organic Chemical Vapor Deposition (MOCVD) process or a Molecular Beam Epitaxy (MBE) process. Wherein the buffer layer 20 has a thickness of 5 μm, is made of N-type doped GaN and has a doping concentration of 3 × 1018cm-3(ii) a The lower limiting layer 30 has a thickness of 0.8 μm and is made of N-type doped Al0.1Ga0.9N, doping concentration of 3X 1018cm-3(ii) a The lower waveguide layer 40 has a thickness of 0.08 μm and is made of N-type doped GaN with a doping concentration of 5 × 1015cm-3(ii) a The active layer 50 includes 5 periods of alternately grown gallium nitride barrier layers and indium gallium nitride well layers, wherein the thickness of the gallium nitride barrier layers is 8nm, and the doping concentration is 3 × 1017cm-3The InGaN well layer has a thickness of 3nm and is made of In0.17Ga0.83N; the electron blocking layer 60 has a thickness of 20nm and is made of P-type doped AlxGa1-xN, doping concentration of 5X 1015cm-3(ii) a The upper waveguide layer 70 has a thickness of 0.08 μm and is made of P-type doped GaN with a doping concentration of 3 × 1017cm-3(ii) a The upper limiting layer 80a has a thickness of 0.6 μm and is made of P-type doped Al0.08Ga0.92N, doping concentration of 8 x 1019cm-3(ii) a The thickness of the covering layer 13 is 0.2 μm, and the material is P-type doped GaN with a doping concentration of 2.4 × 1020cm-3。
Step S2, an etching process is applied to etch the epitaxial structure 11 from the top of the capping layer 13, and the ridge semiconductor layer 80 is formed on the top of the epitaxial structure 11 (as shown in fig. 3 b).
Specifically, an etching process is applied to etch the upper confinement layer 80a from the top of the cover layer 13, so that the top of the upper confinement layer 80a has a plurality of ridges 110, 111, 112, 113, 114, forming the ridge semiconductor layer 80. Among the plurality of ridge parts 110, 111, 112, 113 and 114 of the array, the width of the first ridge part 110 and 111 positioned at the outermost edge is 10-12 mu m; the width of the second ridge part 114 positioned at the middle is 6-8 mu m; the third ridge portions 112, 113 located between the first ridge portions 110, 111 and the second ridge portion 114 have a width of 7 to 9 μm, and satisfy the condition: the widths of the first ridge portions 110 and 111 are larger than the widths of the third ridge portions 112 and 113, and the widths of the third ridge portions 112 and 113 are larger than the width of the second ridge portion 114. The ridge semiconductor layer 80 has a plurality of ridge portions 110, 111, 112, 113, and 114 having the same height, and the distance between two adjacent ridge portions 110, 111, 112, 113, and 114 is 100 to 180 nm. Wherein the etching process is a reactive ion etching process.
Step S3 is to sequentially grow and form the insulating layer 15 and the top electrode 14 on the ridge semiconductor layer 80, with the insulating layer 15 being located between the top electrode and both sides of each ridge portion of the ridge semiconductor layer 80 (as shown in fig. 3 c). Wherein, the insulating layer 15 is prepared by an evaporation process, and the top electrode 14 is prepared by an evaporation or magnetron sputtering process.
Step S4, thinning the substrate 10 from the bottom of the substrate 10 (as shown in fig. 3 d). Specifically, the bottom of the substrate 10 is thinned to 60-100 μm.
Step S5, depositing the bottom electrode 12 on the bottom of the substrate 10 (as shown in fig. 3 e).
In the actual preparation process, the laser prepared by the method is cleaved along the m-plane to form a cavity surface, and then [11-20 ] of gallium nitride is subjected to surface treatment]Surface cleavage to form a laser tube core with a cavity length of 800 μm, and evaporating a pair of TiO on the front cavity surface of the laser tube core2/SiO2Reflecting film, back cavity surface evaporation plating three pairs of TiO2/SiO2The film was reflected and the laser chip was attached to the AlN heat sink with Au/Sn solder. And finally, leading out an electrode and packaging to form the laser device.
We compared the ridge array semiconductor laser of this example with a single ridge gallium nitride laser by using a method of analog temperature calculation, in which:
for a single ridge gallium nitride laser, the junction temperature versus thermal resistance relationship is used:
Rth＝△T/(IH*VH-Popt)
according to the calculation of the gallium nitride-based blue laser of the embodiment, the width of the ridge step is 10 μm, the thermal resistance is 22K/W, the ambient temperature is 24 ℃, and the surface temperature of the device is approximately equal to the ambient temperature. For a single ridge gallium nitride laser, calculating the temperature difference between the surface temperature of the device and the active region by about 40K; for the ridge array semiconductor laser in the embodiment, the temperature difference between the surface temperature and the active region is calculated in a simulated mode, the thermal resistance is 6-7K/W, the thermal resistance of the device is reduced, the internal temperature distribution of the device structure is obviously uniform compared with that of a single ridge gallium nitride laser, the internal temperature difference of the whole device is reduced, when the same current density is injected, the heat generated by the laser is in direct proportion to the strip width, the current on the ridge with the narrowest strip width is the smallest, the heat generation is less, the temperature difference between the active region and the temperature on two sides is reduced compared with that of the single ridge gallium nitride laser, and the temperature distribution is almost the same for the whole structure.
The foregoing is directed to embodiments of the present application and it is noted that numerous modifications and adaptations may be made by those skilled in the art without departing from the principles of the present application and are intended to be within the scope of the present application.
Claims (9)
1. A ridge array semiconductor laser comprises a substrate and an epitaxial structure formed on the substrate, wherein a ridge semiconductor layer is arranged on the top of the epitaxial structure, the ridge semiconductor layer comprises a plurality of ridge parts of an array, and the widths of the plurality of ridge parts are not equal;
the epitaxial structure comprises a buffer layer, a lower limiting layer, a lower waveguide layer, an active layer, an electron blocking layer, an upper waveguide layer and an upper limiting layer which are sequentially arranged on the substrate, wherein the upper limiting layer is the ridge-shaped semiconductor layer;
a top electrode is formed on the ridge semiconductor layer; the ridge array semiconductor laser includes a cap layer located only between each ridge portion of the ridge semiconductor layer and the top electrode;
the ridge array semiconductor laser includes an insulating layer located only between both sides of each ridge portion of the ridge semiconductor layer and the top electrode.
2. A ridge array semiconductor laser as claimed in claim 1, wherein the plurality of ridges of the array have widths that increase in order from the middle to both sides.
3. A ridge array semiconductor laser as claimed in claim 2, wherein the plurality of ridge portions of the array are arranged in bilateral symmetry.
4. A ridge array semiconductor laser as claimed in claim 2, wherein of the plurality of ridges of the array, a first ridge located at an outermost edge has a width of 10 to 12 μm; and/or the width of the second ridge part positioned at the middle part is 6-8 mu m; and/or the width of a third ridge part between the first ridge part and the second ridge part is 7-9 mu m.
5. A ridge array semiconductor laser as claimed in claim 1, wherein the heights of the plurality of ridge portions are equal.
6. A ridge array semiconductor laser as claimed in claim 1, wherein a distance between two adjacent ridges in the ridge array is 100 to 180 nm.
7. A ridge array semiconductor laser as defined in claim 6, wherein a bottom electrode is formed on the bottom of the substrate.
8. A ridge array semiconductor laser as claimed in claim 7, wherein the substrate is N-type free standing GaN, the buffer layer is N-type doped GaN, the lower confinement layer is N-type doped AlGaN, the lower waveguide layer is N-type doped GaN, the electron blocking layer is P-type doped AlGaN, the upper waveguide layer is P-type doped GaN, the upper confinement layer is P-type doped AlGaN, the cap layer is P-type doped GaN, the insulating layer is silicon dioxide, and the active layer is quantum well comprising alternatively grown GaN barrier layers and InGaN well layers.
9. A method of fabricating a ridge array semiconductor laser as claimed in any one of claims 1 to 8, comprising the steps of: providing a substrate and growing an epitaxial structure on the top of the substrate; and etching the epitaxial structure by using an etching process, and forming the ridge-shaped semiconductor layer on the top of the epitaxial structure.
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| CN102611002A (en) * | 2012-03-23 | 2012-07-25 | 中国科学院长春光学精密机械与物理研究所 | Low divergence angle full Bragg reflector waveguide semiconductor laser array |
| JP2015046467A (en) * | 2013-08-28 | 2015-03-12 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102611002A (en) * | 2012-03-23 | 2012-07-25 | 中国科学院长春光学精密机械与物理研究所 | Low divergence angle full Bragg reflector waveguide semiconductor laser array |
| JP2015046467A (en) * | 2013-08-28 | 2015-03-12 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
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