CN107611133B - Memory and forming method thereof, semiconductor devices - Google Patents
Memory and forming method thereof, semiconductor devices Download PDFInfo
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- CN107611133B CN107611133B CN201710963663.7A CN201710963663A CN107611133B CN 107611133 B CN107611133 B CN 107611133B CN 201710963663 A CN201710963663 A CN 201710963663A CN 107611133 B CN107611133 B CN 107611133B
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Abstract
The present invention provides a kind of memory and forming method thereof, semiconductor devices.It is formed self-aligned the first isolation barrier using the wordline mask for defining word line conductor, and by forming thickening layer to increase the thickness of the formation substrate of the second isolation barrier, so that the top surface for the second isolation barrier being formed in substrate is higher than the top surface of the first isolation barrier.In this way, not only define node contact window using the first isolation barrier of intersection and the second isolation barrier, the problem of to obviate offset deviation caused by photoetching process；Also, using the lower top surface of the first isolation barrier, it can be achieved that the top of node contact extends, arrangement mode of multiple node contacts on its joint face with capacitor is formed by with adjustment, so as to advanced optimize the dense degree of capacitor arrangement.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of memory and forming method thereof and a kind of semiconductor
Device.
Background technology
Memory generally includes storage and the memory transistor for being connected to the memory element, the storage electricity
Container is used for storing the charge for representing storage information.Active area, drain region and grid, the grid are formed in the memory transistor
For controlling the electric current flowing between the source region and drain region, and it is connected to word line conductor, the source region connects for constituting bit line
Area is touched, to be connected to a bit line conductors with by bit line contact, the drain region is used for configuration node contact zone, to pass through a node
It connects to storage.
Currently, when forming node contact, the forming region of node contact is usually directly defined using photoetching process,
That is, directly defining size and the position for being formed by node contact using photoetching process.However, being formed using the above method
When node contact, due to the limitation of the alignment precision of photoetching process, so that the problem of inevitably generation position deviates, makes
The position of the forming region of the node contact defined generates deviation, this, which will further result in, is subsequently formed by node contact
It is unable to fully contact and lead to the problem of larger contact resistance between node contact area.Especially, with device size
Constantly reduction and the limitation of lithographic process window, the problem of making to be unable to fully contact between node contact and node contact area
It will be more serious.
In addition, after preparing the node contact, it is also necessary to which the arrangement mode of corresponding node contact forms a storage
Capacitor is on the node contact.That is, the arrangement mode of capacitor is corresponding with the arrangement mode of node contact, for example, working as
Multiple node contacts are arranged on its joint face with capacitor with the square array of rule, then are subsequently formed by capacitor
Corresponding regular square array arrangement.However, with the continuous reduction of dimensions of semiconductor devices, regular square array
Arrangement mode has been unable to reach the arrangement closeness of enough capacitors, to be unfavorable for the reduction of memory-size, and by
In the reduction of capacitor sizes, the capacitance of capacitor can also be impacted accordingly.Therefore, how capacitor arrangement is improved
Dense degree, and the capacitance of increase capacitor are particularly important.
Invention content
The purpose of the present invention is to provide a kind of forming methods of memory, to solve utilizing in existing forming method
When photoetching process directly defines node contact window, the problem of easy ting produce position deviation, while also advantageously improving capacitor
Arrangement dense degree.
In order to solve the above technical problems, the present invention provides a kind of forming method of memory, including：
One substrate is provided, multiple active areas is formed in the substrate, has one to be used to form defined in the active area
The first area in bit line contact area and multiple second areas for being used to form node contact area, multiple second areas are distributed in
The both sides of the first area；
Form a wordline mask over the substrate, be formed in the wordline mask it is multiple extend in a first direction open
Mouthful, and a plurality of word line conductor is formed in the substrate of the correspondence opening；
It is directed at the word line conductor and forms one first shielding wire over the substrate, opened described in the first shielding wire filling
Mouth is to cover the word line conductor, and the top surface of first shielding wire is not higher than the top surface of the wordline mask, uses
It is located at the first isolation barrier in the wordline mask in composition one；
Form a thickening layer over the substrate, the thickening layer covers first isolation barrier and the wordline is covered
Film, the thickening layer and the wordline mask are used to constitute the formation substrate of one second isolation barrier；
It is formed in the formation substrate of multiple bit line trenches over the substrate, the bit line trenches run through the formation
The thickening layer of substrate and the wordline mask, and the bit line trenches along second direction extend and with it is corresponding described in have
Source region intersects, so that the bitline contact area of institute in the corresponding active area corresponds in the bit line trenches, and is formed more
In the bit line trenches, bitline contact area of institute is connected to institute's bit line conductors, the top of institute's bit line conductors for bit line conductors
Surface is less than the top surface of the bit line trenches；
It is directed at institute's bit line conductors and forms one second shielding wire over the substrate, the second shielding wire filling institute rheme
Line trenches bit line conductors to cover, second shielding wire are provided commonly for constituting one positioned at the shape with institute's bit line conductors
At second isolation barrier in substrate, and the top surface of second shielding wire is higher than the top table of the wordline mask
Face makes second shielding wire extend in the part that the bit line trenches correspond to the thickening layer, so that second isolation
The top surface of barrier is higher than the top surface of first isolation barrier；
With second isolation barrier for secondary mask, the thickening layer for forming substrate and the word are removed successively
Line mask, to expose first isolation barrier and the node contact area, first isolation barrier and described successively
Two isolation barriers intersect on the surface of the substrate to define multiple node contact windows, each node contact area jointly
It is accordingly exposed in a node contact window；
A node contact is filled in the node contact window, and using first isolation barrier relative to described second
The lower top surface difference in height of isolation barrier makes the node contact extend over to the top surface of first isolation barrier.
Optionally, before forming the word line conductor, further include：
Form a bit line contact over the substrate, institute's bitline contact is embedded in a separation layer being located on the substrate
In, and be electrically connected with bitline contact area of institute, bitline contact area of institute is connected to the bit line by institute's bitline contact and leads
Body.
Optionally, bitline contact area of institute and the bit line is completely covered in the projection of the bit line trenches over the substrate
Contact, and in said first direction, the greatest width dimension of bitline contact area of institute and institute's bitline contact is respectively less than institute
The greatest width dimension of rheme line trenches, so that the greatest width dimension of bit line contact area and institute's bitline contact is respectively less than described
The greatest width dimension of second isolation barrier；It is being that substrate and described is formed described in mask etching using second isolation barrier
It is located at the part below second isolation barrier when separation layer is to expose the node contact area, in the separation layer to be protected
It stays.
Optionally, the bit line trenches include close to the undercut of institute's bitline contact and far from institute's bitline contact
Top channel, second isolation barrier include close to the bottom isolation part of institute's bitline contact and far from the bit line accordingly
The top isolation part of contact, and in said first direction, the broad-ruler of the top isolation part of second isolation barrier
The very little greatest width dimension more than institute's bitline contact and bitline contact area of institute；
In said first direction, described in being less than when the width dimensions of the bottom isolation part of second isolation barrier
It is being described in mask etching using second isolation barrier when width dimensions of the top isolation part of the second isolation barrier
When forming substrate and the separation layer to expose the node contact area, institute is located in the formation substrate and the separation layer
It states the part below the isolation part of top to be retained, institute of the retained formation substrate in correspondence second isolation barrier
The position for stating bottom isolation part extends to the surface of the retained separation layer；
In said first direction, described in being equal to when the width dimensions of the bottom isolation part of second isolation barrier
It is being described in mask etching using second isolation barrier when width dimensions of the top isolation part of the second isolation barrier
When forming substrate and the separation layer to expose the node contact area, it is located under the bottom isolation part in the separation layer
The part of side is retained.
Optionally, the forming step of institute's bitline contact includes：
Form a separation layer over the substrate, the separation layer covers the active area；
A bit line contacting window is formed in the separation layer, bitline contact area of institute is exposed in the bit line contacting window；
And
Alignment filling institute's bitline contact is in the bit line contacting window, institute's bitline contact and bitline contact area of institute electricity
Property connection.
Optionally, first shielding wire alignedly covers the word line conductor, and forming method includes：
It is substrate described in mask etching using the wordline mask, the wordline groove of the opening is corresponded in institute to form one
It states in substrate；
Word line conductor is formed in the wordline groove, and the surface of the word line conductor is not higher than the wordline groove
Top surface；And
It forms first shielding wire in said opening and extends in the wordline groove, led with covering the wordline
Body.
Optionally, the forming method of first shielding wire includes：
Form one first spacer material layer over the substrate, first spacer material layer is filled the opening and covered
The wordline mask；And
It is that polish stop layer executes chemical mechanical milling tech using the wordline mask, removes first isolated material
It is located at the part at the top of the wordline mask in layer, remaining first spacer material layer is made to be only filled in said opening,
To constitute first shielding wire.
Optionally, the forming step of second shielding wire includes：
Form one second spacer material layer over the substrate, second spacer material layer fills the bit line trenches simultaneously
Cover the thickening layer；And
It is that polish stop layer executes chemical mechanical milling tech using the thickening layer, partly removes the second isolation material
It is located at the part at the top of the thickening layer in the bed of material, remaining second spacer material layer is made to be only filled in the bit line trenches
In, to constitute second shielding wire of the top surface higher than the top surface of first shielding wire.
Optionally, after forming the bit line trenches, further include：
A spacer insulator layer is formed on the side wall of the bit line trenches, wherein the spacer insulator layer, the bit line are led
Body and second shielding wire collectively form second isolation barrier.
Optionally, the forming step of the node contact includes：
Have relative to the higher top surface of the first isolation barrier, alignment filling one using second isolation barrier
In gap of the conductive layer between adjacent second isolation barrier, the conductive layer is filled the node contact window and is covered
First isolation barrier, so that the conductive layer is extended continuously along the second direction；And
Multiple separation openings are formed in the conductive layer with etching mode, and the separation opening is located at described first and is isolated
Part above barrier exposes first isolation barrier, makes adjacent institute corresponding in the adjacent node contact window
It is mutually separated to state conductive layer, to constitute multiple node contacts, and separation opening has non-corresponding in described first
Isolation barrier and with the local be overlapped part of the node contact window so that the top surface of the node contact is along described second
Direction extends the top for being offset to first isolation barrier.
Optionally, separation opening structure in wave shape extends and locally overlaps in first isolation barrier, and
The waveform configuration for separating opening is corresponded to respectively at the position of each second isolation barrier both sides towards the second party
To wave crest and away from the trough of the second direction, so as to be connect positioned at the nodes of each second isolation barrier both sides
Tactile top surface extends the top for being offset to first isolation barrier respectively along the second direction toward opposite direction.
Another object of the present invention is to provide a kind of memory, including：
One substrate is formed with multiple active areas in the substrate, be formed in the active area bit line contact area and
Multiple node contact areas, multiple node contact areas are distributed in the both sides in bitline contact area of institute；
A plurality of word line conductor forms in the substrate and extends along a first direction；
A plurality of first shielding wire forms over the substrate and alignedly covers the word line conductor, for constituting one the
One isolation barrier, and the surface of first isolation barrier is higher than the surface of the substrate；
Multiple bit lines conductor forms and extends over the substrate and along second direction, institute's bit line conductors with it is corresponding
Active area intersects, so that the bitline contact area of institute in the corresponding active area is connected on institute's bit line conductors；
A plurality of second shielding wire forms over the substrate and alignedly covers institute's bit line conductors, institute's bit line conductors
It is provided commonly for constituting one second isolation barrier, first isolation barrier and second isolation barrier with second shielding wire
Intersect on the surface of the substrate to define multiple node contact windows jointly, each node contact area corresponds to an institute
Node contact window is stated, and makes the top surface of second isolation barrier higher than described using the thickness value of second shielding wire
The top surface of first isolation barrier；
Multiple node contacts are filled in the node contact window, and using first isolation barrier relative to described
The lower top surface difference in height of second isolation barrier makes the node contact extend over upper to first isolation barrier
Side.
Optionally, the memory further includes a bit line contact, is formed in bitline contact area of institute over the substrate,
Bitline contact area of institute is connected to institute's bit line conductors by institute's bitline contact.
Optionally, bitline contact area of institute and described is completely covered in the projection of second isolation barrier over the substrate
Bit line contact, and in said first direction, the greatest width dimension of bitline contact area of institute and institute's bitline contact is small
In the greatest width dimension of second isolation barrier.
Optionally, the memory further includes a support separation layer, is formed over the substrate and is connect positioned at the bit line
Tactile periphery；Second isolation barrier includes close to the bottom isolation part of institute's bitline contact and far from institute's bitline contact
Top isolation part, and the width dimensions of the top isolation part of second isolation barrier are more than institute's bitline contact and institute
The greatest width dimension in bitline contact area；
In said first direction, described in being less than when the width dimensions of the bottom isolation part of second isolation barrier
When the width dimensions of the top isolation part of the second isolation barrier, the support separation layer alignment setting is in second isolation
The lower section of the top isolation part of barrier, and extend from the position of the bottom isolation part of correspondence second isolation barrier
To the surface of the substrate；
In said first direction, described in being equal to when the width dimensions of the bottom isolation part of second isolation barrier
When the width dimensions of the top isolation part of the second isolation barrier, the support separation layer alignment setting is in second isolation
The lower section of the bottom isolation part of barrier.
Optionally, the memory further includes a spacer insulator layer, the side wall of covering institute bit line conductors, and the interval
Insulating layer, institute's bit line conductors and second shielding wire collectively form second isolation barrier.
Optionally, there is first isolation by an exposure between the adjacent node contact in this second direction
Barrier separation opening it is mutually separated, and separations opening with non-corresponding in first isolation barrier and with the section
The part that point contact window is locally overlapped so that the top surface of the node contact be offset to along second direction extension it is described
The top of first isolation barrier.
Optionally, separation opening structure in wave shape extends and locally overlaps in first isolation barrier, and
The waveform configuration for separating opening respectively corresponds at the position of each second isolation barrier both sides towards described second
The wave crest in direction and trough away from the second direction, so that the node positioned at each second isolation barrier both sides
The top surface of contact extends the top for being offset to first isolation barrier respectively along the second direction toward opposite direction.
Based on above-described memory, the present invention also provides a kind of semiconductor devices, including：
One substrate is formed with multiple first contact zones in the substrate；
A plurality of first isolation barrier is made of a plurality of the first shielding wire formed over the substrate, and extends first party
To extension；
A plurality of second isolation barrier forms over the substrate and extends along second direction, first isolation barrier
Intersect to define multiple contact holes jointly on the surface of the substrate with second isolation barrier, each described first connects
Touch area correspond to a contact hole, and second isolation barrier include one second shielding wire, with using described second every
Offline thickness value makes the top surface of second isolation barrier higher than the top surface of first isolation barrier；
Multiple conductive contacts are filled in the contact hole and are electrically connected with first contact zone, and described in utilization
First isolation barrier relative to the lower top surface difference in height of second isolation barrier, make the conductive contact extend over to
The top of first isolation barrier.
Optionally, multiple second contact zones are also formed on the substrate, second isolation barrier includes a conductor layer,
Second shielding wire covers the conductor layer, and in this second direction, multiple second contact zones are connected to phase
In the conductor layer for second isolation barrier answered.
Optionally, second contact zone is completely covered in the projection of second isolation barrier over the substrate, and
In said first direction, the greatest width dimension of second contact zone is less than the maximum width ruler of second isolation barrier
It is very little.
Optionally, second isolation barrier includes close to the bottom isolation part of second contact zone and far from described the
The top isolation part of two contact zones, and the width dimensions of the top isolation part of second isolation barrier are more than described the
The greatest width dimension of two contact zones；
In said first direction, described in being less than when the width dimensions of the bottom isolation part of second isolation barrier
When the width dimensions of the top isolation part of the second isolation barrier, in the top isolation part of second isolation barrier
Lower section, which is also aligned, is provided with a support separation layer, and the support separation layer corresponds to the bottom isolation of second isolation barrier
The position in portion extends on the surface of the substrate.
In the forming method of memory provided by the invention, word line conductor and then secondary is being formed using wordline mask
It is formed self-aligned the first isolation barrier using wordline mask, and increases the formation base of the second isolation barrier by a thickening layer
The thickness at bottom, the top surface to make to be formed on the second isolation barrier in substrate are higher than the top table of the first isolation barrier
Face.Thus, be on the one hand conducive to defining node contact window using the first isolation barrier and the intersection of the second isolation barrier
Avoid the problem that the offset deviation brought when for example executing photoetching process；On the other hand, due to the top surface of the second isolation barrier
Higher than the top surface of the first isolation barrier, so as on the basis of the node contact of the second isolation barrier both sides is mutually isolated,
Using the lower top surface of the first isolation barrier, allow node contact extended on the extending direction of the second isolation barrier to
Thus the top of first isolation barrier is conducive to adjustment and is formed by multiple node contacts on its joint face with capacitor
Arrangement mode, so as to advanced optimize the dense degree of capacitor arrangement.
Description of the drawings
Fig. 1 is a kind of flow diagram of the forming method of memory in the present invention.
Fig. 2 a are vertical view of the forming method of the memory in the embodiment of the present invention one when it executes step S110.
Fig. 2 b are the forming method of the memory in the embodiment of the present invention one shown in Fig. 2 a when it executes step S110
Along the sectional view of AA ', BB ' and the directions CC.
Fig. 3 a are vertical view of the forming method of the memory in the embodiment of the present invention one when it prepares bit line contact.
Fig. 3 b are the forming method of the memory in the embodiment of the present invention one shown in Fig. 3 a when it prepares bit line contact
Along the diagrammatic cross-section of AA ', BB ' and the directions CC '.
Fig. 4 a are vertical view of the forming method of the memory in the embodiment of the present invention one when it executes step S120.
Fig. 4 b and Fig. 4 c are the forming method of the memory in the embodiment of the present invention one shown in Fig. 4 a in its execution step
Along the sectional view of AA ', BB ' and the directions CC during S120.
Fig. 5 a are vertical view of the forming method of the memory in the embodiment of the present invention one when it executes step S130.
Fig. 5 b are the forming method of the memory in the embodiment of the present invention one shown in Fig. 5 a in its execution step S130 mistake
Along the sectional view of AA ', BB ' and the directions CC in journey.
Fig. 6 a are vertical view of the forming method of the memory in the embodiment of the present invention one when it executes step S140.
Fig. 6 b are the forming method of the memory in the embodiment of the present invention one shown in Fig. 6 a in its execution step S140 mistake
Along the sectional view of AA ', BB ' and the directions CC in journey.
Fig. 7 a are vertical view of the forming method of the memory in the embodiment of the present invention one when it executes step S150.
Fig. 7 b and Fig. 7 c are the forming method of the memory in the embodiment of the present invention one shown in Fig. 7 a in its execution step
Along the sectional view of AA ', BB ' and the directions CC during S150.
Fig. 8 a are vertical view of the forming method of the memory in the embodiment of the present invention one when it executes step S160.
Fig. 8 b are the forming method of the memory in the embodiment of the present invention one shown in Fig. 8 a when it executes step S160
Along the sectional view of AA ', BB ' and the directions CC.
Fig. 9 a are vertical view of the forming method of the memory in the embodiment of the present invention one when it executes step S170.
Fig. 9 b are the forming method of the memory in the embodiment of the present invention one shown in Fig. 9 a when it executes step S170
Along the sectional view of AA ', BB ' and the directions CC.
Figure 10 a~Figure 11 a are the forming method of the memory in the embodiment of the present invention one when it executes step S180
Vertical view.
Figure 10 b and Figure 11 b are respectively the formation side of the memory in the embodiment of the present invention one shown in Figure 10 a and Figure 11 a
Method is when it executes step S180 along the sectional view of AA ', BB ' and the directions CC.
Figure 12 a are the vertical view of the memory in the embodiment of the present invention two.
Figure 12 b are sectional view of the memory in the embodiment of the present invention two shown in Figure 12 a along AA ', BB ' and the directions CC.
Wherein, reference numeral is as follows：
X-direction-second direction；Y-direction-first direction；
The extending direction of Z-direction-active area；
100- substrates；110- active areas；
111- bit line contacts area；112- node contacts area；
112a- node contact windows；120- isolation structures；
130- separation layers；140- bit line contacts；
150- supports separation layer；210- wordline masks；
210a- is open；220- word line conductors；
220a- wordline grooves；The first isolation barriers of 300-；
The first shielding wires of 310-；400- forms substrate；
410- thickening layers；The second isolation barriers of 500-；
500a- grooves；510a- bit line trenches；
510- bit line conductors；520- spacer insulator layers；
The second shielding wires of 530-；600- node contacts；
601- conductive layers；600a- separates opening.
Specific implementation mode
As stated in the background art, at present when preparing node contact, typically node contact is defined using photoetching process
Window is limited with being further formed node contact by the precision of photoetching process, then inevitably makes to be formed by node
There are deviation of the alignment between contact and node contact area, and then generate larger contact resistance.In addition, with semiconductor devices ruler
The capacitance of very little continuous reduction, the dense degree and capacitor that how to ensure the capacitor arrangement in memory also becomes one
A urgent problem.
For this purpose, the present invention provides a kind of forming methods of memory.Fig. 1 is a kind of formation of memory in the present invention
The flow diagram of method, as shown in Figure 1, the forming method includes：
Step S110, provides a substrate, is formed with multiple active areas in the substrate, has one defined in the active area
It is used to form the first area in bit line contact area and multiple second areas for being used to form node contact area, multiple secondth areas
Domain is distributed in the both sides of the first area；
Step S120 forms a wordline mask over the substrate, is formed in the wordline mask multiple along first party
To the opening of extension, and a plurality of word line conductor is formed in the substrate of the correspondence opening；
Step S130 is directed at the word line conductor and forms one first shielding wire over the substrate, first shielding wire
The opening is filled to cover the word line conductor, the top surface of first shielding wire is not higher than the top table of the wordline mask
Face, for constituting first isolation barrier being located in the wordline mask；
Step S140 forms a thickening layer over the substrate, and the thickening layer covers first isolation barrier and institute
Wordline mask is stated, the thickening layer and the wordline mask are used to constitute the formation substrate of one second isolation barrier；
Step S150 is formed in the formation substrate of multiple bit line trenches over the substrate, and the bit line trenches pass through
Wear it is described formed substrate the thickening layer and the wordline mask, and the bit line trenches along second direction extend and with phase
The active area intersection answered, so that the bitline contact area of institute in the corresponding active area is corresponded in the bit line trenches
In, and multiple bit lines conductor is formed in the bit line trenches, bitline contact area of institute is connected to institute's bit line conductors, institute's rheme
The top surface of line conductor is less than the top surface of the bit line trenches；
Step S160, alignment institute bit line conductors form one second shielding wire over the substrate, second shielding wire
Filling the bit line trenches, bit line conductors, second shielding wire are provided commonly for composition one with institute's bit line conductors to cover
Second isolation barrier in the formation substrate, and the top surface of second shielding wire is covered higher than the wordline
The top surface of film makes second shielding wire extend in the part that the bit line trenches correspond to the thickening layer, so that described
The top surface of second isolation barrier is higher than the top surface of first isolation barrier；
Step S170 removes the described of formation substrate and thickens successively with second isolation barrier for secondary mask
Layer and the wordline mask, to expose first isolation barrier and the node contact area, first isolated screen successively
Barrier and second isolation barrier intersect on the surface of the substrate to define multiple node contact windows jointly, each described
Node contact area is accordingly exposed in a node contact window；
Step S180, one node contact of filling utilize first isolation barrier opposite in the node contact window
In the lower top surface difference in height of second isolation barrier, the node contact is made to extend over to first isolation barrier
Top surface.
In the forming method of memory provided by the invention, the wordline mask autoregistration landform for defining word line conductor is being utilized
At the first shielding wire to constitute the first isolation barrier after, by formed thickening layer, make the top surface for being formed by bit line trenches
The top surface of the first isolation barrier can be higher than, so as to further be formed self-aligned the second shielding wire in institute using thickening layer
In rheme line trenches, and ensure that the top surface for the second isolation barrier being made of bit line conductors and the second shielding wire is higher than first
The top surface of isolation barrier.Thus, on the one hand using the first isolation barrier and the intersection of the second isolation barrier to define
Node contact window, without additionally executing one of photoetching process again；On the other hand since the top surface of the first isolation barrier is low
In the top surface of the second isolation barrier, extended over to the top table of the first isolation barrier to enable to be formed by node contact
Face, that is, can be to be formed by node on the basis of guaranteeing to form node contact one-to-one with node contact area
The top of contact provides a wider space, and then multiple node contacts can be changed in the arrangement side of itself and the joint face of capacitor
Formula improves the arrangement flexibility for being subsequently formed by capacitor, in favor of improving the dense degree of capacitor arrangement.
Below in conjunction with the drawings and specific embodiments to it is proposed by the present invention go out memory and forming method thereof, semiconductor devices
It is described in further detail.According to following explanation and claims, advantages and features of the invention will become apparent from.It should be noted
That attached drawing is all made of very simplified form and uses non-accurate ratio, only to it is convenient, lucidly aid in illustrating this hair
The purpose of bright embodiment.
Embodiment one
Fig. 2 a are vertical view of the forming method of the memory in the embodiment of the present invention one when it executes step S110, figure
2b be the memory in the embodiment of the present invention one shown in Fig. 2 a forming method when it executes step S110 along AA ', BB ' and
The sectional view in the directions CC.
In step s 110, with reference to shown in figure 2a and Fig. 2 b, a substrate 100 is provided, is formed in the substrate 100 more
A active area 110 has a first area for being used to form bit line contact area 111 defined in the active area 110 and multiple is used for
The second area in node contact area 112 is formed, multiple second areas are distributed in the both sides of the first area.
In the present embodiment, the active area 110 is tilted relative to first direction (Y-direction) to be extended, multiple firstth areas
Domain extends in the both sides on the extending direction of the active area 110 and positioned at the second area.Wherein, the first area
Area is more than or equal to more than or equal to the area of the area and second area that are subsequently formed by the first contact zone subsequently to be formed
The second contact zone area.In subsequent technique, it is formed by bit line contact area 111 and is connected to one by a bit line contact
Bit line conductors, the node contact area 112 are connected to storage by a node contact.
Shown in Fig. 2 a, the active area 11 extends along the Z direction.Specifically, the extension side of the active area
It can be 50 °~70 °, for example, 60 ° to the acute angle of (Z-direction) between first direction.Further, the present embodiment
In, multiple active areas 110 are arranged in multirow, and active area 110, which tilts, to be extended, therefore can be made in same a line active area 110
Adjacent active area 110 has in the projection perpendicular to line direction to partially overlap, thus, can be conducive to improve active area battle array
The dense degree of row.
In conjunction with shown in Fig. 2 a and Fig. 2 b, multiple isolation structures 120, the isolation structure are also formed in the substrate 100
120 are located at the periphery of active area 110, for adjacent active area 110 to be isolated.It will also be appreciated that passing through to be formed
The isolation structure 120 defines the active area 110 in turn.Wherein, the isolation structure 120 can be trench isolations knot
Structure.
Further, the active area 110 is used to form storage unit, and the storage unit is, for example, memory transistor.
In subsequent manufacturing process, ion doping technique can be executed to the substrate of the first area and second area, with shape respectively
At ion doped region, the ion doped region of corresponding second area may make up the source region of the memory transistor, and then may make up and deposit
The bit line contact area 111 of reservoir；The ion doped region of corresponding first area may make up the drain region of the memory transistor, Jin Erke
Constitute the node contact area 112 of memory.Wherein, the ion doping technique can execute before forming word line conductor,
It can be executed after forming word line conductor.
It should be noted that in the attached drawing of the present embodiment, what the node contact area 112 and bit line contact area 111 were indicated
Position is the substrate close to the surface of node contact and bit line contact, i.e., what node contact area 112 indicated is that it connects with node
What tactile 500 contact surface and bit line contact area 111 indicated is the contact surface for it between bit line contact.However it should recognize
Know, in other embodiments, it is understood that it is that form doped region in the substrate be node contact area and bit line contact area,
At this point it is possible to will indicate that the reference numeral in node contact area and bit line contact area is shown in the position of the doped region in substrate.
In the present embodiment, before preparing word line conductor, bit line contact area 111 is first formed in the substrate of active area 110
With node contact area 112.As shown in Figure 2 b, can be by executing ion doping technique, while being formed in the substrate of second area
Bit line contact area 111, and node contact area 112 is formed in the substrate of first area.Certainly, in other embodiments, exist
In subsequent step after formation word line conductor, when exposing the substrate of second area, you can execute doping process to be formed
Bit line contact area 111, and when exposing the substrate of first area, you can doping process is executed to form node contact area
112。
In addition, further including forming a bit line conductors, and Shi Suo bitline contacts area 111 is connected to institute in subsequent technique
Bit line conductors, wherein bitline contact area 111 of institute can be connected to institute's bit line conductors by a bit line contact.Further,
Institute's bitline contact can be formed before forming word line conductor, can also be formed after forming word line conductor, or even also may be used
To prepare institute's bitline contact while preparing bit line conductors.
In the present embodiment, institute's bitline contact is preferentially formed before forming word line conductor.Fig. 3 a are the embodiment of the present invention
Vertical view of the forming method of memory when it prepares bit line contact in one, Fig. 3 b are the embodiment of the present invention one shown in Fig. 3 a
The forming method of middle memory is when it prepares bit line contact along the diagrammatic cross-section of AA ', BB ' and the directions CC '.With specific reference to
Shown in attached drawing 3a and attached drawing 3b, the forming method of institute's bitline contact includes：
Step 1 forms a separation layer 210 on the substrate 100, and the separation layer 210 covers described active 110；
Step 2 forms a bit line contacting window in the separation layer 210, and bitline contact area 111 of institute is exposed to described
In bit line contacting window；
Step 3, alignment filling institute bitline contact 220 is in the bit line contacting window, institute's bitline contact 220 and institute
Bitline contact area 111 is electrically connected.
It should be noted that being only to show schematically a kind of circular bit line contact in Fig. 3 a, however, in actual storage
In the preparation process of device, institute's bitline contact can be other arbitrary shapes, such as can be round, oval, rectangle or water chestnut
Shape etc..
Fig. 4 a are vertical view of the forming method of the memory in the embodiment of the present invention one when it executes step S120, figure
4b and Fig. 4 c are the forming method of the memory in the embodiment of the present invention one shown in Fig. 4 a during it executes step S120
Along the sectional view of AA ', BB ' and the directions CC.
In the step s 120, with specific reference to shown in Fig. 4 a- Fig. 4 c, a wordline mask 210 is formed on the substrate 100,
It is formed with multiple opening 210a extended along first direction (Y-direction) in the wordline mask 210, and forms a plurality of word line conductor
220 in the substrate 100 of the correspondence opening 210a.
Wherein, the wordline mask 210 is used to define the figure of word line conductor 220.Specifically, the word line conductor
220 be buried word line, i.e., the surface of the word line conductor 220 is not higher than the surface of the substrate 100.Correspondingly, the wordline
The forming method of conductor 220 includes：
First step forms wordline mask 210 on the substrate 100, the word shown in Fig. 4 a and Fig. 4 b
Multiple opening 210a are formed on line mask 210 to expose the substrate 100 of corresponding word line conductor；In the present embodiment, need
The word line conductor 220 of formation extends for (Y-direction) along a first direction, and therefore, the opening 210a is accordingly also along first
Direction (Y-direction) extends；
Second step is substrate 100 described in mask etching with the wordline mask 210, with shape shown in Fig. 4 b
At a wordline groove 220a in the substrate 100, the i.e. corresponding opening 210a of the wordline groove 220a；
Third step fills wordline material, with shape shown in Fig. 4 a and Fig. 4 c in the wordline groove 220a
At the word line conductor 220 extended along the first direction (Y-direction)；Specifically, the wordline material include a gate dielectric layer and
One grid conducting layer, the gate dielectric layer are formed in side wall and the bottom of the wordline groove 220a, the grid conducting layer shape
At on the gate dielectric layer and filling the wordline groove 220a；Wherein, the gate dielectric layer is, for example, oxide layer, nitration case
Or nitrogen oxidation layer etc., the grid conducting layer is such as can be polysilicon layer or metal layer；
Four steps then exists to ensure that the surface for being formed by word line conductor 220 is not higher than the surface of the substrate 100
After deposition has wordline material, can also technique further be etched back to wordline material execution, wordline is formed by with control
The height of conductor 220, such as the top surface of the word line conductor being ultimately formed 220 can further be made to be less than the wordline groove
The top surface of 220a, at this point, the top surface of the word line conductor 220 is less than the top surface of the substrate 100.
Since the surface of the word line conductor 220 is not higher than the top surface of the wordline groove 220a, to subsequent
In technique, can directly utilize wordline mask 210 opening 210a and wordline groove 220a, autoregistration on word line conductor 220
The first shielding wire is formed, and can ensure that the word line conductor 220 can be completely covered by being formed by the first shielding wire, avoid wordline
The side wall of conductor 220 is exposed.
Continue shown in Fig. 4 a, to be formed by word line conductor 220 and with active area 110 intersect, so as to make on active area 110
The gate structure of memory transistor is connected on corresponding word line conductor 220.In the present embodiment, the gate structure of memory transistor
It is formed simultaneously with the word line conductor, that is, the wordline material in active area 110 constitutes the grid knot of memory transistor simultaneously
Structure and word line conductor.Further, the gate structure is formed in bitline contact area 111 of institute and the node contact area 112
Between, and be to be arranged successively along the first direction in the multiple node contact areas 112 for being distributed in 220 both sides of the word line conductor
Cloth.
In forming method provided by the invention, still retain the wordline mask 210 after forming word line conductor 220,
So as to be formed self-aligned the first shielding wire using the opening 210a of the wordline mask 210.As described above, described in formation
After word line conductor 220, then multiple node contact areas 112 can be made to be distributed on the both sides of the word line conductor 220, in profit
After the first shielding wire being formed self-aligned with the wordline mask 210, you can make word line conductor 220 using first shielding wire
The node contact area 112 of both sides is mutually isolated.
Fig. 5 a are vertical view of the forming method of the memory in the embodiment of the present invention one when it executes step S130, figure
5b be the memory in the embodiment of the present invention one shown in Fig. 5 a forming method during it executes step S130 along AA ',
The sectional view of BB ' and the directions CC.
In step s 130, with specific reference to shown in Fig. 5 a and Fig. 5 b, be aligned the word line conductor 220 formed one first isolation
For line 310 on the substrate 100, first shielding wire 310 fills the opening 210a to cover the word line conductor 220,
The top surface of first shielding wire 310 is not higher than the top surface of the wordline mask 210, is located at the wordline for constituting one
The first isolation barrier 300 in mask 210.At this point, first isolation barrier keeps the node contact area 112 of 300 both sides corresponding
It is mutually isolated.
As shown in figure 5 a and 5b, first shielding wire 310 is filled opening 210a and is extended in wordline groove 220a,
To cover the word line conductor 220, so as to preferably be electrically isolated to word line conductor 220.Also, first isolation
Line 310 fills the opening 210a, that is, the surface of first shielding wire 310 is higher than the surface of substrate 100, and corresponding edge
First direction (Y-direction) extension.
In the present embodiment, the first shielding wire that alignment covers the word line conductor 220 is formed in combination with flatening process
310, forming method is, for example,：First, the first spacer material layer of deposition is on the substrate 100, first isolated material
Layer fills the wordline groove 220a and opening 210a, and covers the wordline mask 210；Then, flat chemical industry is utilized
Skill removes the part for being located at 210 top of the wordline mask in first spacer material layer, makes remaining first isolation
Material layer is only filled in the opening 210a, to constitute first shielding wire 310.Wherein, described first is partly being removed
When spacer material layer, chemical mechanical milling tech is executed as polish stop layer using the wordline mask 210；Alternatively,
It is that etching stop layer execution is etched back to technique that the wordline mask 210, which can be utilized,.Specifically, material can be isolated according to described first
The material of the bed of material and the wordline mask 210 selects corresponding removing method, for example, when the material of first spacer material layer
For silica, the wordline mask 210 close to the material of top section be silicon nitride when, then using chemical mechanical milling tech
Part removes first spacer material layer；When the material of first spacer material layer is silicon nitride, the wordline mask 210
When material close to top section is silica, then the available process portion that is etched back to removes first spacer material layer.
It is understood that the first shielding wire 310 formed using flatening process, top surface and the wordline mask
210 top surface, which is flushed or approached, to be flushed (for example, the difference in height of the two is less than 10% of wordline mask height).Correspondingly, the
The top surface of one isolation barrier 300 is flushed or is approached with the top surface of the wordline mask 210 and flushes.
Fig. 6 a are vertical view of the forming method of the memory in the embodiment of the present invention one when it executes step S140, figure
6b be the memory in the embodiment of the present invention one shown in Fig. 6 a forming method during it executes step S140 along AA ',
The sectional view of BB ' and the directions CC.
In step S140, shown in Fig. 6 a and Fig. 6 b, a thickening layer 410 is formed on the substrate 100, institute
It states thickening layer 410 and covers first isolation barrier 300 and the wordline mask 210, the thickening layer 410 and the wordline are covered
Film 210 is used to constitute the formation substrate 400 of one second isolation barrier.
It is formed in the wordline mask 210 and the thickening layer 410 that is, being subsequently formed by the second isolation barrier.By
In the formation substrate 400 for being formed with the thickening layer 410, top surface is higher than the top surface of the first isolation barrier 300, indirectly certainly
Determine subsequently to be formed by the height of the second isolation barrier, so as to be formed by the top surface of the second isolation barrier higher than described the
The top surface of one isolation barrier 300.
Further, the material identical with the wordline mask 210 that can be used of the thickening layer 410 is formed, such as can
It is all made of silica composition, certainly, in other embodiments, the material different from the wordline mask 210 can also be used and formed.
As long as by forming thickening layer 410, the second isolation barrier being made of the thickening layer 410 and wordline mask 210 can be made
The height for forming substrate 400 increases, further to make the top surface for being formed by the second isolation barrier be higher than the first isolation barrier
300 top surface.
Fig. 7 a are vertical view of the forming method of the memory in the embodiment of the present invention one when it executes step S150, figure
7b and Fig. 7 c are the forming method of the memory in the embodiment of the present invention one shown in Fig. 7 a during it executes step S150
Along the sectional view of AA ', BB ' and the directions CC.
In step S150, shown in Fig. 7 a~Fig. 7 c, multiple bit line trenches 510a are formed in the substrate 100
On the formation substrate 400 in, the bit line trenches 510a through it is described formed substrate 400 the thickening layer 410 and institute
State wordline mask 210, and the bit line trenches 510a extend along second direction (X-direction) and with the corresponding active area
110 intersections, so that the bitline contact area 111 of institute in the corresponding active area 110 corresponds in the bit line trenches 510a,
And multiple bit lines conductor 510 is formed in the bit line trenches 510a, bitline contact area 111 of institute is connected to institute's bit line conductors
510, the top surface of institute's bit line conductors 510 is less than the top surface of the bit line trenches 510a.
Wherein, the bit line trenches 510a is not only for forming bit line conductors 510；Meanwhile in subsequent technique, may be used also
The second shielding wire of a covering institute bit line conductors 510 is formed self-aligned using the bit line trenches 510a, in institute's rheme
The second isolation barrier is formed in line trenches 510a.Specifically, by adjusting the height of bit line conductors 510, so as to be formed by
The top surface of bit line conductors 510 is less than the top surface of the bit line trenches 510a, so as to conducive to the bit line trenches reserved
Second shielding wire for corresponding to bit line conductors 510 is formed to 510a autoregistrations at the top of bit line conductors 510, alignment covering is in place
Second shielding wire of 510 top of line conductor can be used for electrically isolating bit line conductors 510.
Emphasis is with reference to figure 7b and combines shown in Fig. 7 a, and projections of the bit line trenches 510a on the substrate 100 is complete
It covers bitline contact area 111 of institute and institute's bitline contact 140, Ji Suo bitline contacts area 111 and institute's bitline contact 140 is complete
It is complete corresponding in the bit line trenches 510a.And on the first direction (Y-direction), bitline contact area 111 of institute and institute
The greatest width dimension of bitline contact 140 is respectively less than the greatest width dimension of the bit line trenches 510a.Specifically, rear
In continuous technique, institute's bitline contact can be completely covered by being formed by the second isolation barrier using the bit line trenches 510a
140 and bit line contact area 111, and the greatest width dimension of bit line contact 112 and institute's bitline contact 140 is made to be respectively less than described
The greatest width dimension of two isolation barriers, to when being that mask etching forms substrate 400 using the second isolation barrier, it can be ensured that
Film layer in the projected area of the second isolation barrier is retained, and then avoidable bit line contact 140 and bit line contact area 111 are sudden and violent
Expose.For example, in the present embodiment, it is formed with separation layer 130 on the substrate 100, is utilizing second isolation barrier 500
When for mask etching separation layer 130 to expose the node contact area 112, in the separation layer 130 be located at described second every
The part of 500 lower section of off screen barrier is retained).Specifically, the greatest width dimension due to bit line trenches 210a is more than bit line contact
140 and bit line contact area 111 greatest width dimension, so as to make to be located at the part of the periphery of bit line contact 140 in separation layer 130
It can be retained, and then avoid bit line contact area 111 and the side wall of bit line contact 140 from being exposed using the separation layer 130
Go out.Especially, defined using the first isolation barrier 300 and the second isolation barrier it is multiple corresponding with node contact area 112
Node contact in, since part separation layer 130 is retained, it is ensured that in a first direction (that is, first isolation barrier 300
Extending direction) arrangement adjacent node contact and bit line contact 140 between electrically isolate.
Further, the bit line trenches 210a includes close to the undercut of bit line contact 140 and far from bit line contact
140 top channel, wherein on the first direction (Y-direction), the broad-ruler of the top channel of the bit line trenches 210a
The very little width dimensions more than bit line contact 140.In the present embodiment, the width dimensions of the undercut of the bit line trenches 210a are small
In the width dimensions of its top channel, so that structure wide at the top and narrow at the bottom is presented in the bit line trenches 210a.Certainly, in other implementations
In example, the bit line trenches 210a can also be it is whole have an identical width dimensions, i.e. the bottom ditch of the bit line trenches 210
Slot is identical with the width dimensions of top channel.
Shown in Fig. 7 a and Fig. 7 b, directly the bit line trenches can be formed using photoetching process and etch process
510a.The bit line trenches 510a and 110 space intersection of corresponding active area, so that the institute in corresponding active area 110
Bitline contact 140 can be exposed by the bit line trenches 510a, and then bit line contact 140 is made to can be connected to bit line conductors
510, to realize the electric connection between bit line contact area 111 and institute's bit line conductors 510.In addition, with reference to shown in figure 7b, it is described
In bit line trenches 510a, active area 110 described in non-corresponding and in the part of the corresponding isolation structure 120, be formed in substrate 100
On separation layer 130 be exposed, therefore, be filled in bit line conductors 510 in the bit line trenches 510a not corresponding described
The part of bit line contact 140 is isolated by the separation layer 130 with substrate 100.
Shown in Fig. 7 a and Fig. 7 c, institute's bit line conductors 510 are filled in the bit line trenches 510a, and with institute
Bitline contact 140 is electrically connected, correspondingly, being formed by bit line conductors 510 staggeredly passes through first isolation barrier 300.
Wherein, it is distributed in multiple node contact areas 112 of the same side of the word line conductor 220, two adjacent sections
Point contact area 112 is located at the both sides of institute's bit line conductors 510.Specifically, the word line conductor 220 is in the substrate
Projection and institute's bit line conductors 510 on 100 are intersected, with the multiple chessboard lattices defined, described in the chessboard lattice correspondence
Node contact area 112.
In the present embodiment, the width dimensions of the top channel of the bit line trenches 510a are more than the width dimensions of undercut
And structure wide at the top and narrow at the bottom is presented.Wherein, when the undercut of the bit line trenches 510a has enough height, then described
Bit line conductors 510 are only filled in the undercut, be formed by this time bit line conductors 510 at various locations on broad-ruler
It is very little consistent；When the height of the undercut of the bit line trenches 510a is relatively low, be formed by bit line conductors 510 extend to it is described
In the top channel of bit line trenches 510a, and then structure wide at the top and narrow at the bottom is also showed accordingly.
Further include forming spacer insulator layer before forming bit line conductors 510 shown in Fig. 7 a and Fig. 7 c
520 on the side wall of the bit line trenches 510a, make subsequently to be formed by node contact and position using the spacer insulator layer 520
Line conductor 510 electrically isolates.Wherein, the spacer insulator layer 520 in combination with depositing operation and is etched back to technique and is formed, specific to wrap
It includes：First, one insulation material layer of deposition is on the substrate 100, and the insulation material layer covers the wordline mask 210 and the
The top of one isolation barrier 300, and cover the bottom and side wall of the bit line trenches 510a；Then, it using technique is etched back to, goes
Except the insulation material layer positioned at 300 top of wordline mask 210 and the first isolation barrier, and removal are located at the bottoms bit line trenches 510a
The insulation material layer in portion, to ensure, bitline contact 140 can be exposed, and retained and be located on bit line trenches 510a side walls
Insulation material layer, to constitute the spacer insulator layer 520.
Fig. 8 a are vertical view of the forming method of the memory in the embodiment of the present invention one when it executes step S160, figure
8b be the memory in the embodiment of the present invention one shown in Fig. 8 a forming method when it executes step S160 along AA ', BB ' and
The sectional view in the directions CC.
In step S160, shown in Fig. 8 a and Fig. 8 b, alignment institute bit line conductors 510 form one second isolation
Line 530 on the substrate 100, second shielding wire 530 fill the bit line trenches 510a to cover bit line conductors
510, and the top surface of second shielding wire 530 is higher than the top surface of the wordline mask 210, so that second isolation
Line 530 extends in the part that the bit line trenches 510a corresponds to the thickening layer 410, second shielding wire 530 with it is described
Bit line conductors 510 are provided commonly for constituting second isolation barrier 500 in the formation substrate 400.
Wherein, the second isolation barrier 500, pattern and the bit line trenches are formed by using the bit line trenches 510a
The pattern of 510a is corresponding, that is, second isolation barrier 500 extends along second direction (X-direction) and includes leaning on accordingly
The bottom isolation part of nearly institute bitline contact 140 and the top isolation part far from institute's bitline contact 140, and then it is rendered as width
Under narrow structure, also, on the first direction (Y-direction), the width of the top isolation part of second isolation barrier 500
Size is more than the width dimensions of bit line contact 140 and bit line contact area 111.
As described above, constituted chessboard point is intersected in the projection of the word line conductor 220 and bit line conductors 510 on substrate
Lattice corresponding node contact zone, correspondingly, first isolation barrier 300 and second isolation barrier 500 intersection, it can common boundary
Make multiple node contact windows for being corresponding with the node contact area 112.
With reference to shown in figure 8a and Fig. 8 b, spacer insulator layer 520 is also formed on the side wall of bit line trenches 510a, therefore,
In the present embodiment, the spacer insulator layer 520, bit line conductors 510 and 530 common combination of the second shielding wire are described to constitute
Second isolation barrier 500.Wherein, second shielding wire 530 can be used an insulating materials and be formed, and in combination with flatening process
The second shielding wire 530 is formed self-aligned in the bit line trenches 510a.Specific steps include：
First, one second spacer material layer of deposition is on the substrate 100, the second spacer material layer filler duct
Slot 510a, and cover the thickening layer 410 for forming substrate 400；Wherein, second spacer material layer can be used and institute
It states the identical material of the first spacer material layer to be formed, for example, second spacer material layer and first spacer material layer can
It is all made of silicon nitride composition；
Then, in conjunction with shown in Fig. 8 a and Fig. 8 b, it is located at position in second spacer material layer using flatening process removal
Part in 410 top of the thickening layer, makes remaining second spacer material layer be only filled in the bit line trenches 510a, with
Constitute second shielding wire 530.Further, second isolated material is removed using chemical mechanical milling tech part
Layer, in the process, the thickening layer 410 can be used as polish stop layer, and process of lapping is enable automatically to stop at thickening layer
410 top position, at this point, the top surface of remaining second spacer material layer is flushed with the top surface of the thickening layer 410, from
And the top surface for being formed by the second shielding wire 530 is made to be flushed with the top surface of thickening layer 410, it is ensured that by the second shielding wire 530
The top surface of the second isolation barrier 500 constituted is higher than the top surface of first isolation barrier 300.
Certainly, in other embodiments, also using process portion removal second spacer material layer is etched back to, at this time
It is etching stop layer using the thickening layer 410, makes to be etched back to technique to be automatically stopped at the top of thickening layer 410.
Fig. 9 a are vertical view of the forming method of the memory in the embodiment of the present invention one when it executes step S170, figure
9b be the memory in the embodiment of the present invention one shown in Fig. 9 a forming method when it executes step S170 along AA ', BB ' and
The sectional view in the directions CC.
In step S170, shown in Fig. 9 a and Fig. 9 b, with second isolation barrier 500 for secondary mask,
The thickening layer for forming substrate and the wordline mask are removed successively, to expose first isolation barrier successively
300 and the node contact area 112, first isolation barrier 300 and second isolation barrier 500 are in the substrate 100
Surface intersect to define multiple node contact window 112a jointly, each node contact area 112 is accordingly exposed to one
In a node contact window 112a.
It is adjacent to make since the top surface of the second isolation barrier 500 is higher than the top surface of first isolation barrier 300
Two the second isolation barriers 500 between gap can constitute the groove 500a for including multiple node contact window 112a,
That is, the top of multiple contact hole 112a in same groove 500a is interconnected.It is understood that the node contact
Sidewall Heights of the window 112a on the extending direction of the first isolation barrier 300 (in Y-direction) is higher than the node contact window 112a
Sidewall Height on the extending direction of the second isolation barrier 500 (in X-direction).Thus, you can make subsequently to be directed at filling
Conductive layer in the groove 500a can be extended continuously along the second isolation barrier 500.
In the present embodiment, it is also formed with the separation layer 130 on the substrate 100, therefore, is removing the thickening layer
During the wordline mask, the separation layer 130 exposed is further also removed, so that the node contact area
112 expose.
In addition, in the present embodiment, second isolation barrier 500 is presented including bottom isolation part and top isolation part
Therefore narrow structure under width is being that mask etching forms substrate and separation layer 130 with exposure with second isolation barrier 500
It is described to form in substrate and the separation layer 130 portion being located at below the top isolation part when going out the node contact area 112
It point is retained, position of the retained formation substrate in the bottom isolation part of correspondence second isolation barrier 500
Set the surface for extending to the retained separation layer 130.In the present embodiment, with specific reference to cuing open on the directions CC ' in Fig. 9 b
Face schematic diagram, the part wordline mask 210 formed in substrate are retained.
It should be noted that in other embodiments, in a first direction, when the bottom of second isolation barrier every
Width dimensions from the top isolation part that the width dimensions in portion are equal to second isolation barrier, and it is all higher than the bit line
It is being to be formed described in mask etching using second isolation barrier when greatest width dimension in contact and bitline contact area of institute
When substrate and the separation layer are to expose the node contact area, it is located at below the bottom isolation part in the separation layer
Part is retained.
Figure 10 a~11a are forming method the bowing when it executes step S180 of the memory in the embodiment of the present invention one
View, Figure 10 b and Figure 11 b are respectively that the forming method of the memory in the embodiment of the present invention one shown in Figure 10 a and Figure 11 a exists
Along the sectional view of AA ', BB ' and the directions CC when its execution step S180.
In step S180, shown in Figure 10 a~Figure 10 b and Figure 11 a~Figure 11 b, a node contact 600 is filled
In the node contact window 112a, and it is relatively low relative to second isolation barrier 500 using first isolation barrier 300
Top surface difference in height, so that the node contact 600 is extended over to the top surface of first isolation barrier 300.
That is, due to the lower top surface of the first isolation barrier, it is real using the space above the first isolation barrier
It is now formed by the spatially extended of 600 top of node contact, so as to adjust node contact 600 according to the arrangement mode of capacitor
Arrangement mode on its joint face with capacitor.
Specifically, the forming method of the node contact 600 includes：
First step, emphasis have using second isolation barrier 500 relative to institute with reference to shown in figure 10a and Figure 10 b
300 higher top surface of the first isolation barrier is stated, alignment one conductive layer 601 of filling is in adjacent second isolation barrier 500
Between gap in, the conductive layer 601 fills the node contact window 112a and covers first isolation barrier 300, with
The conductive layer 601 is set to be extended continuously along the second direction (X-direction)；
As noted previously, as 500 top surface of the second isolation barrier is higher than the top surface of first isolation barrier 300, it can
Multiple groove 500a are constituted, so as to utilize groove 500a (the higher top surface of the second isolation barrier 500) alignedly to fill out
Conductive layer 601 is filled in the groove 500a (gap between two adjacent the second isolation barriers 500)；Wherein, available
Chemical mechanical milling tech, and be polish stop layer with second isolation barrier 500, so that conductive layer 601 is alignedly filled in
In the groove 500a；
Second step, emphasis form multiple separations with reference to shown in figure 11a and Figure 11 b, with etching mode and are open 600a in institute
It states in conductive layer 601, the part that 600a is located above first isolation barrier 300 that is open that separates exposes described first
Isolation barrier 300 keeps the adjacent conductive layer 601 corresponding in the adjacent node contact window 112a mutually separated,
To constitute multiple node contacts 600, and separation opening 600a has non-corresponding in first isolation barrier 300
And with the local be overlapped parts the node contact window 112a so that the top surface of the node contact 600 is along described second
Direction extends the top for being offset to first isolation barrier 300；
That is, by etching 601 to the first isolation barrier 300 of conductive layer, to make in adjacent contact hole 112a
Conductive layer 601 is mutually separated, and 600 are contacted with configuration node.It is understood that node adjacent in same groove 500a connects
Adjacent node contact 600 is avoided to be electrically connected using the first isolation barrier 300 and separation opening 600a between touching 600.
In preferred scheme, the bottom for separating opening 600 further extends in first isolation barrier 300, that is, etches institute
It states after conductive layer 601 exposes first isolation barrier 300, then etches first isolation barrier 300 partly to go
Except first isolation barrier 300 and etching stopping are in first isolation barrier 300, with formed extend to described first every
Separation opening 600a in off screen barrier 300.
Optionally, it continues to refer to figure 1 shown in 1a, separation opening 600a structures in wave shape extend and locally overlap in institute
It states in the first isolation barrier 300, and the waveform configuration for separating opening 600 is in each 500 liang of second isolation barrier
The position of side corresponds to the wave crest towards the second direction and the trough away from the second direction respectively, so as to be located at each institute
The top surface of the node contact 600 of 500 both sides of the second isolation barrier is stated respectively along the second direction toward opposite direction
Extend the top for being offset to first isolation barrier 300 (that is, close to second isolation barrier 500 and positioned at described second
The top surface of the node contact 600 of 500 both sides of isolation barrier extends respectively along the second direction toward opposite direction inclined
Move to the top of first isolation barrier 300).Wherein, towards the second direction indicate be to be directed toward in a second direction
Its positive direction (positive direction of X-direction), what it is away from second direction expression is to be directed toward its negative direction (side X in a second direction
To negative direction)；Alternatively, it is also understood that towards the second direction indicate be to be directed toward its losing side in a second direction
To (negative direction of X-direction), what is indicated away from the second direction is to be directed toward its positive direction in a second direction (X-direction is just
Direction), that is, being intended to indicate that along two phase negative sides in second direction towards second direction and away from second direction herein
To.
That is, the node contact 600 positioned at 500 both sides of the second isolation barrier shows on its joint face with capacitor
For along the interlaced extension of the extending direction of bit line conductors.Thus, in subsequent technique, it need to be in the node contact
When forming capacitor on 600, you can it is also corresponding interlaced in the X direction to make to be formed by capacitor, and then institute can be improved
The electrode surface area of the capacitor of formation, and also advantageously improve the dense degree of capacitor arrangement.
In the present embodiment, the separation opening 600a is corrugated waveform configuration, and then separation opening 600a exists
Along the X direction toward opposite direction alternating bending in each groove.Certainly, in other embodiments, the separation opening 600a
It can also be rectangular waveform configuration.
Further, in the waveform configuration for separating opening 600a, two phases on wave crest and trough
Mutually the maximum amplitude value between close side wall is less than the width value of second isolation barrier, in etching conductive layer 601
Allow to expose the second isolation barrier, and then can ensure that can be by the first isolation barrier 300 between adjacent node contact 600
Opening 600a is mutually separated with separating.And the big wave amplitude between two side walls being located remotely from each other on wave crest and trough
Value can further be more than the width value of second isolation barrier, that is, ensure that adjacent node contact 600 can realize mutually
On the basis of separation, the width dimensions for separating opening 600a can be further increased, make separation opening 600a in the width direction
It is extended in contact hole 112a from the first isolation barrier 300, so advantageously reduces the preparation difficulty for separating opening 600a, and
Make to be formed by 600 part of node contact and covers first isolation barrier 300.Wherein, close to each other on wave crest and trough
Maximum amplitude value between side wall is expressed as the inner edge vertical range of wave amplitude of vibration；The side wall being located remotely from each other on wave crest and trough it
Between maximum amplitude value, be expressed as the outer rim vertical range of wave amplitude of vibration.
Embodiment two
Another object of the present invention is to provide a kind of memory, the memory utilizes a plurality of first isolation barrier and more
The second isolation barrier of item, which defines, utilizes one in the node contact window for being corresponding with node contact area and second isolation barrier
Second shielding wire makes the top surface of the second isolation barrier be higher than the top surface of the first isolation barrier, so as to be formed along second
The node contact that the extending direction of isolation barrier extends.
Figure 12 a are the vertical view of the memory in the embodiment of the present invention two, and Figure 12 b are that the present invention shown in Figure 12 a is implemented
The sectional view of memory in example two along AA ', BB ' and the directions CC.In conjunction with shown in Figure 12 a and Figure 12 b, the memory includes：
One substrate 100 is formed with multiple active areas 110 in the substrate 100, one is formed in the active area 110
Bit line contact area 111 and multiple node contact areas 112, multiple node contact areas 112 are distributed in bitline contact area 111 of institute
Both sides；In addition, being also formed with multiple isolation structures 120 in the substrate 100, the isolation structure 120 is located at active area
110 periphery, for adjacent active area 110 to be isolated；
A plurality of word line conductor 220, is formed in the substrate 100 and (Y-direction) extends along a first direction, to be isolated
Bitline contact area 111 of institute and the node contact area 112；
A plurality of first shielding wire 310 is formed on the substrate 100 and alignedly covers the word line conductor 220, is used for
One first isolation barrier 300 is constituted, and the surface of first isolation barrier 300 is higher than the surface of the substrate 100；
Multiple bit lines conductor 510 is formed on the substrate 100 and extends along second direction (X-direction), the bit line
Conductor 510 intersects with corresponding active area 110, so that bitline contact area 111 of the institute connection in the corresponding active area 110
To institute's bit line conductors 510；
A plurality of second shielding wire 530 is formed on the substrate 100 and alignedly covers institute's bit line conductors 510, described
Bit line conductors 510 and second shielding wire 530 are provided commonly for constituting one second isolation barrier 500, first isolation barrier
300 and second isolation barrier 500 intersect to define multiple node contact windows jointly on the surface of the substrate 100
112a, each node contact area 112 corresponds to a node contact window 112a, and utilizes second shielding wire
530 thickness difference relative to first shielding wire 310 on the substrate 100 makes the top of second isolation barrier 500
Surface is higher than the top surface of first isolation barrier 300；That is, since second shielding wire 510 has certain thickness, from
And the top surface of second shielding wire 510 is made to be more than the top of first shielding wire 310 relative to the height of the substrate 100
Height of the surface relative to the substrate 100；
Multiple node contacts 600 are filled in the node contact window 112a, and utilize first isolation barrier 300
Relative to second isolation barrier, 500 lower top surface difference in height, the node contact 600 is made to extend over to described
It the top of one isolation barrier 300 and does not extend over to the top of second isolation barrier 510, so as to make to be located at described the
The node contact 600 of two isolation barriers, 510 both sides can be mutually isolated by second isolation barrier 510.
It continues to refer to figure 1 shown in 2b, bitline contact area 111 of institute is connected to the bit line by a bit line contact 140 and leads
Body 510.That is, institute's bitline contact 140 is formed in bitline contact area 111 of institute, and the both ends of institute's bitline contact 140 point
It Lian Jie not bitline contact area 111 of institute and institute's bit line conductors 510.
Further, institute's bitline contact is completely covered in projection of second isolation barrier 500 on the substrate 100
Area 111 and institute's bitline contact 140, and on the first direction (in Y-direction), bitline contact area 111 of institute and described
The greatest width dimension of bit line contact 140 is respectively less than the greatest width dimension of second isolation barrier 500.Due to the second isolation
Bit line contact area 111 and bit line contact 140 can be completely covered in the projection of barrier 500, so as to utilize second isolated screen
Barrier 500 simultaneously combines a support separation layer 150, and bitline contact area 111 of institute and bit line contact 140 is avoided to be exposed to node contact window
In 112a.Specifically, the support separation layer 150 is located at the periphery of institute's bitline contact 140.
In the present embodiment, second isolation barrier 500 includes close to the bottom isolation part of institute bitline contact 140 and remote
Top isolation part from institute's bitline contact, and the width dimensions of the top isolation part of second isolation barrier 500
More than the greatest width dimension of institute's bitline contact 140 and bitline contact area 111 of institute.In the first direction (in Y-direction)
On, when the width dimensions of the bottom isolation part of second isolation barrier 500 are less than the institute of second isolation barrier 500
When stating the width dimensions of top isolation part, the alignment of support separation layer 150 is arranged described in second isolation barrier 500
The lower section of top isolation part, and extend to from the position of the bottom isolation part of correspondence second isolation barrier 500 described
On the surface of substrate 100.And in said first direction, when the bottom isolation part of second isolation barrier 500
When width dimensions are equal to the width dimensions of the top isolation part of second isolation barrier 500, the support separation layer 150
Alignment is arranged in the lower section of the bottom isolation part of second isolation barrier 500.
It continues to refer to figure 1 shown in 2b, the memory still further comprises a spacer insulator layer 520, the spacer insulator
Layer 520 covers the side wall of institute's bit line conductors 510, and the spacer insulator layer 520, institute's bit line conductors 510 and described second
Shielding wire 530 collectively forms second isolation barrier 500.
Shown in Figure 12 a and Figure 12 b, in multiple node contacts 600, in second direction (X-direction)
There is the separation opening 600a of first isolation barrier mutually separated by an exposure between the adjacent node contact 600,
And separation opening 600a have non-corresponding in first isolation barrier 300 and with the parts the node contact window 112a
The part of overlapping, so that the top surface of the node contact 600 is offset to first isolation along second direction extension
The top of barrier 300.In the present embodiment, the arrangement of second isolation barrier 500 is the arranged in parallel of rectilinear form, and institute
The width for stating the second isolation barrier 500 is more than the width for separating the 600a that is open.
Wherein, the separation opening 600a can be extended with structure in wave shape and locally be overlapped in first isolation barrier
On 300, and it is described separate opening 600a waveform configuration each second isolation barrier, 500 both sides position respectively
The corresponding wave crest towards the second direction and the trough away from the second direction, so as to be located at each second isolated screen
The top surface for hindering the node contact 600 of 500 both sides is offset to institute respectively along the second direction toward opposite direction extension
State the top of the first isolation barrier.
Embodiment three
Based on above-described memory and forming method thereof, the present invention also provides a kind of semiconductor devices.Described half
Conductor device includes：
One substrate is formed with multiple first contact zones in the substrate；
A plurality of first isolation barrier is made of a plurality of the first shielding wire formed over the substrate, and extends first party
To extension；
A plurality of second isolation barrier forms over the substrate and extends along second direction, first isolation barrier
Intersect to define multiple contact holes jointly on the surface of the substrate with second isolation barrier, each described first connects
Touch area correspond to a contact hole, and second isolation barrier include one second shielding wire, with using described second every
The top surface of second isolation barrier is set to be higher than relative to the thickness difference of first shielding wire over the substrate offline
The top surface of first isolation barrier；
Multiple conductive contacts are filled in the contact hole and are electrically connected with first contact zone, and described in utilization
First isolation barrier relative to the lower top surface difference in height of second isolation barrier, make the conductive contact extend over to
It the top of first isolation barrier and does not extend over to the top of second isolation barrier.
That is, the second isolation barrier having compared with top surface is realized by second shielding wire, thus in a first direction,
The electric connection between adjacent conductive contact is realized using second isolation barrier.Simultaneously as the first isolation barrier
Top surface be less than the top surface of the second isolation barrier, it can be ensured that the second isolation barrier under the buffer action of conductive contact,
Using the space above the first isolation barrier, realizes the extension of conductive contact in a second direction, thus can be adjusted multiple
The arrangement mode of the conductive contact on its top surface.
According to different semiconductor devices, it can also be formed further with one second contact zone in the substrate, described
Two isolation barriers include a conductor layer, and second shielding wire covers the conductor layer, and in this second direction, multiple
Second contact zone is connected in the conductor layer of corresponding second isolation barrier.That is, second shielding wire is not
It is only used for electrically isolating adjacent conductive contact, while can also be used to draw the second contact zone.
Preferably, second contact zone is completely covered in the projection of second isolation barrier over the substrate, and
In said first direction, the greatest width dimension of second contact zone is less than the maximum width ruler of second isolation barrier
It is very little.Be exposed in the contact hole in this way, can avoid second contact zone, it is ensured that the second contact zone and conductive contact it
Between electrically isolate.
Specifically, second isolation barrier includes close to the bottom isolation part of second contact zone and far from described the
The top isolation part of two contact zones, and the width dimensions of the top isolation part of second isolation barrier are more than described the
The greatest width dimension of two contact zones.In said first direction, when the bottom isolation part of second isolation barrier
When width dimensions are less than the width dimensions of the top isolation part of second isolation barrier, in second isolation barrier
The lower section of the top isolation part, which is also aligned, is provided with a support separation layer, and the support separation layer corresponds to second isolated screen
The position of the bottom isolation part of barrier extends on the surface of the substrate.At this point, even if the bottom of second isolation barrier
The size of portion isolation part be less than the second contact zone size, due to there are support separation layer, so as to using it is described support every
Absciss layer avoids the electric connection between the second contact zone and conductive contact.
In conclusion in the forming method of memory provided by the invention, using the wordline mask for defining word line conductor,
The first shielding wire is formed self-aligned to constitute the first isolation barrier, and by forming a thickening layer, makes the second isolation barrier
It forms substrate and has larger thickness, and then the top surface for ensuring to be formed on the second isolation barrier in substrate is higher than first
The top surface of isolation barrier.Thus, on the one hand, define and be corresponding with using the first isolation barrier and the second isolation barrier
The node contact window in node contact area, compared with traditional utilization photoetching process directly defines node contact window, institute of the present invention
The method of offer can not only omit one of photoetching process, and can avoid leading to institute circle by the precision limitation of photoetching process
The node contact window made has the problem of larger displacement deviation；On the other hand the sky above the first isolation barrier can also be utilized
Between, make the top of node contact that can extend on the extending direction of the second isolation barrier, to adjust node contact in itself and capacitance
Arrangement mode on the joint face of device.
Each embodiment is described by the way of progressive in this specification, the highlights of each of the examples are with other
The difference of embodiment, just to refer each other for identical similar portion between each embodiment.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (23)
1. a kind of forming method of memory, which is characterized in that including：
One substrate is provided, multiple active areas is formed in the substrate, has one to be used to form bit line defined in the active area
The first area of contact zone and multiple second areas for being used to form node contact area, multiple second areas are distributed in described
The both sides of first area；
It forms a wordline mask over the substrate, multiple openings extended in a first direction is formed in the wordline mask,
And a plurality of word line conductor is formed in the substrate of the correspondence opening；
Be directed at the word line conductor and form one first shielding wire over the substrate, the first shielding wire filling opening with
The word line conductor is covered, and the top surface of first shielding wire is not higher than the top surface of the wordline mask, is used for structure
The first isolation barrier being located at one in the wordline mask；
Form a thickening layer over the substrate, the thickening layer covers first isolation barrier and the wordline mask, institute
It states thickening layer and the wordline mask is used to constitute the formation substrate of one second isolation barrier；
It is formed in the formation substrate of multiple bit line trenches over the substrate, the bit line trenches run through the formation substrate
The thickening layer and the wordline mask, and the bit line trenches along second direction extend and with the corresponding active area
Intersection so that the bitline contact area of institute in the corresponding active area corresponds in the bit line trenches, and forms a plurality of position
For line conductor in the bit line trenches, bitline contact area of institute is connected to institute's bit line conductors, the top surface of institute's bit line conductors
Less than the top surface of the bit line trenches；
It is directed at institute's bit line conductors and forms one second shielding wire over the substrate, second shielding wire fills the bit line ditch
Slot bit line conductors to cover, second shielding wire are provided commonly for constituting one positioned at the formation base with institute's bit line conductors
Second isolation barrier in bottom, and the top surface of second shielding wire is higher than the top surface of the wordline mask, makes
Second shielding wire extends in the part that the bit line trenches correspond to the thickening layer, so that second isolation barrier
Top surface is higher than the top surface of first isolation barrier；
With second isolation barrier for secondary mask, the thickening layer for forming substrate is removed successively and the wordline is covered
Film, to expose first isolation barrier and the node contact area successively, first isolation barrier and described second every
Off screen barrier intersects on the surface of the substrate to define multiple node contact windows jointly, and each node contact area corresponds to
Ground is exposed in a node contact window；And
A node contact is filled in the node contact window, and using first isolation barrier relative to second isolation
The lower top surface difference in height of barrier makes the node contact extend over to the top surface of first isolation barrier.
2. the forming method of memory as described in claim 1, which is characterized in that before forming the word line conductor, also
Including：
Form a bit line contact over the substrate, institute's bitline contact is embedded in the separation layer that one is located on the substrate simultaneously
It is electrically connected with bitline contact area of institute, bitline contact area of institute is connected to institute's bit line conductors by institute's bitline contact.
3. the forming method of memory as claimed in claim 2, which is characterized in that the bit line trenches are over the substrate
Bitline contact area of institute and institute's bitline contact is completely covered in projection, and in said first direction, bitline contact area of institute
The greatest width dimension of the bit line trenches is respectively less than with the greatest width dimension of institute bitline contact, so that institute's bitline contact
The greatest width dimension of area and institute's bitline contact is respectively less than the greatest width dimension of second isolation barrier；Described in utilization
Second isolation barrier is when forming substrate and the separation layer described in mask etching to expose the node contact area, it is described every
It is located at the part below second isolation barrier in absciss layer to be retained.
4. the forming method of memory as claimed in claim 3, which is characterized in that the bit line trenches include close to institute's rheme
The undercut of line contact and the top channel far from institute's bitline contact, second isolation barrier include close to institute accordingly
The top isolation part of the bottom isolation part of bitline contact and separate institute bitline contact, and in said first direction, it is described
The width dimensions of the top isolation part of second isolation barrier are more than the width of institute's bitline contact and bitline contact area of institute
Size；
In said first direction, when the width dimensions of the bottom isolation part of second isolation barrier are less than described second
It is being to be formed described in mask etching using second isolation barrier when width dimensions of the top isolation part of isolation barrier
When substrate and the separation layer are to expose the node contact area, the top is located in the formation substrate and the separation layer
Part below portion isolation part is retained, and the retained formation substrate is at the bottom of correspondence second isolation barrier
The position of portion isolation part extends to the surface of the retained separation layer；And
In said first direction, when the width dimensions of the bottom isolation part of second isolation barrier are equal to described second
It is being to be formed described in mask etching using second isolation barrier when width dimensions of the top isolation part of isolation barrier
When substrate and the separation layer are to expose the node contact area, it is located at below the bottom isolation part in the separation layer
Part is retained.
5. the forming method of memory as claimed in claim 2, which is characterized in that the forming step packet of institute's bitline contact
It includes：
Form a separation layer over the substrate, the separation layer covers the active area；
A bit line contacting window is formed in the separation layer, bitline contact area of institute is exposed in the bit line contacting window；And
In the bit line contacting window, institute's bitline contact electrically connects alignment filling institute's bitline contact with bitline contact area of institute
It connects.
6. the forming method of memory as described in claim 1, which is characterized in that first shielding wire alignedly covers institute
Word line conductor is stated, forming method includes：
It is substrate described in mask etching using the wordline mask, the wordline groove of the opening is corresponded in the lining to form one
In bottom；
Word line conductor is formed in the wordline groove, and the top surface of the word line conductor is not higher than the top of the wordline groove
Surface；And
It forms first shielding wire in said opening and extends in the wordline groove, to cover the word line conductor.
7. the forming method of memory as described in claim 1, which is characterized in that the forming method packet of first shielding wire
It includes：
Form one first spacer material layer over the substrate, the first spacer material layer filling is described to be open and cover described
Wordline mask；And
It is that polish stop layer executes chemical mechanical milling tech using the wordline mask, removes in first spacer material layer
Part at the top of the wordline mask makes remaining first spacer material layer be only filled in said opening, with structure
At first shielding wire.
8. the forming method of memory as described in claim 1, which is characterized in that the forming step packet of second shielding wire
It includes：
Form one second spacer material layer over the substrate, second spacer material layer is filled the bit line trenches and covered
The thickening layer；And
It is that polish stop layer executes chemical mechanical milling tech using the thickening layer, partly removes second spacer material layer
In be located at the thickening layer at the top of part, so that remaining second spacer material layer is only filled in the bit line trenches,
To constitute second shielding wire of the top surface higher than the top surface of first shielding wire.
9. the forming method of memory as described in claim 1, which is characterized in that after forming the bit line trenches and
It is formed before institute's bit line conductors, further includes：
A spacer insulator layer is formed on the side wall of the bit line trenches, wherein the spacer insulator layer, institute's bit line conductors and
Second shielding wire collectively forms second isolation barrier.
10. the forming method of memory as claimed in any one of claims 1 to 9 wherein, which is characterized in that the node contact
Forming step includes：
Have relative to the higher top surface of the first isolation barrier using second isolation barrier, alignment filling one is conductive
In gap of the layer between adjacent second isolation barrier, the conductive layer is filled described in the node contact window and covering
First isolation barrier, so that the conductive layer is extended continuously along the second direction；And
Multiple separation openings are formed in the conductive layer with etching mode, and the separation opening is located at first isolation barrier
The part of top exposes first isolation barrier, makes in the adjacent node contact window corresponding adjacent described lead
Electric layer is mutually separated, and to constitute multiple node contacts, and separation opening has non-corresponding in first isolation
Barrier and with the local be overlapped concave portion of the node contact window so that the top surface of the node contact is along described second
Direction extends the top for being offset to first isolation barrier.
11. the forming method of memory as claimed in claim 10, which is characterized in that separation opening structure in wave shape is prolonged
It stretches and locally overlaps in first isolation barrier, and the waveform configuration for separating opening is in each second isolation
The position of barrier both sides corresponds to the wave crest towards the second direction and the trough away from the second direction respectively, so as to be located at
The top surface of the node contact of each second isolation barrier both sides is respectively along the second direction toward opposite direction
Extend the top for being offset to first isolation barrier.
12. a kind of memory, which is characterized in that including：
One substrate is formed with multiple active areas in the substrate, be formed in each active area a bit line contact area and
Multiple node contact areas, the node contact area are distributed in the both sides in bitline contact area of institute；
A plurality of word line conductor forms and extends in the substrate and along a first direction, to be isolated bitline contact area and
The node contact area；
A plurality of first shielding wire forms over the substrate and alignedly covers the word line conductor, for constitute one first every
Off screen hinders, and the surface of first isolation barrier is higher than the surface of the substrate；
Multiple bit lines conductor forms and extends over the substrate and along second direction, institute's bit line conductors with it is corresponding active
Area intersects, so that the bitline contact area of institute in the corresponding active area is connected on institute's bit line conductors；
A plurality of second shielding wire forms over the substrate and alignedly covers institute's bit line conductors, institute's bit line conductors and institute
It states the second shielding wire to be provided commonly for constituting one second isolation barrier, first isolation barrier and second isolation barrier are in institute
It states and intersects on the surface of substrate to define multiple node contact windows jointly, each node contact area corresponds to a section
Point contact window, and make institute relative to the thickness difference of first shielding wire over the substrate using second shielding wire
The top surface for stating the second isolation barrier is higher than the top surface of first isolation barrier；And
Multiple node contacts are filled in the node contact window, and using first isolation barrier relative to described second
The lower top surface difference in height of isolation barrier makes the node contact extend over to the top of first isolation barrier and not
It extends over to the top of second isolation barrier.
13. memory as claimed in claim 12, which is characterized in that further include：
One bit line contact is formed in bitline contact area of institute over the substrate, and bitline contact area of institute passes through the bit line
It connects to institute's bit line conductors.
14. memory as claimed in claim 13, which is characterized in that the projection of second isolation barrier over the substrate
Bitline contact area of institute and institute's bitline contact is completely covered, and in said first direction, bitline contact area of institute and institute
The greatest width dimension of bitline contact is respectively less than the greatest width dimension of second isolation barrier.
15. memory as claimed in claim 13, which is characterized in that the memory further includes a support separation layer, is formed
Over the substrate and positioned at the periphery of institute's bitline contact；Second isolation barrier includes close to the bottom of institute's bitline contact
The top isolation part of portion isolation part and separate institute bitline contact, and the top isolation part of second isolation barrier
Width dimensions are more than the greatest width dimension of institute's bitline contact and bitline contact area of institute；
In said first direction, when the width dimensions of the bottom isolation part of second isolation barrier are less than described second
When the width dimensions of the top isolation part of isolation barrier, the support separation layer alignment is arranged in second isolation barrier
The top isolation part lower section, and extend to institute from the position of the bottom isolation part of correspondence second isolation barrier
It states on the surface of substrate；And
In said first direction, when the width dimensions of the bottom isolation part of second isolation barrier are equal to described second
When the width dimensions of the top isolation part of isolation barrier, the support separation layer alignment is arranged in second isolation barrier
The bottom isolation part lower section.
16. memory as claimed in claim 12, which is characterized in that further include：
One spacer insulator layer, the side wall of covering institute bit line conductors, and the spacer insulator layer, institute's bit line conductors and described the
Two shielding wires collectively form second isolation barrier.
17. the memory as described in claim 12~16 any one, which is characterized in that adjacent in this second direction
There is the separation of first isolation barrier to be open by an exposure between the node contact mutually separated, and described separates
Mouthful have non-corresponding in first isolation barrier and with the local be overlapped concave portion of the node contact window so that the section
The top surface of point contact extends the top for being offset to first isolation barrier along the second direction.
18. memory as claimed in claim 17, which is characterized in that separation opening structure in wave shape extends and locally weighs
Repeatedly in first isolation barrier, and the waveform configuration for separating opening is in each second isolation barrier both sides
Position respectively corresponds to the wave crest towards the second direction and the trough away from the second direction, so that positioned at each described
The top surface of the node contact of second isolation barrier both sides, which extends respectively along the second direction toward opposite direction, to be deviated
To the top of first isolation barrier.
19. memory as claimed in claim 18, which is characterized in that the arrangement of second isolation barrier is rectilinear form
Arranged in parallel, the width of second isolation barrier is more than the width for separating opening.
20. a kind of semiconductor devices, which is characterized in that including：
One substrate is formed with multiple first contact zones in the substrate；
A plurality of first isolation barrier is made of a plurality of the first shielding wire formed over the substrate, and extends first direction and prolong
It stretches；
A plurality of second isolation barrier forms over the substrate and extends along second direction, first isolation barrier and institute
The second isolation barrier is stated to intersect on the surface of the substrate to define multiple contact holes, each first contact zone jointly
A corresponding contact hole, and second isolation barrier includes one second shielding wire, to utilize second shielding wire
Make the top surface of second isolation barrier higher than described relative to the thickness difference of first shielding wire over the substrate
The top surface of first isolation barrier；And
Multiple conductive contacts are filled in the contact hole and are electrically connected with first contact zone, and utilize described first
Isolation barrier makes the conductive contact extend over to described relative to the lower top surface difference in height of second isolation barrier
It the top of first isolation barrier and does not extend over to the top of second isolation barrier.
21. semiconductor devices as claimed in claim 20, which is characterized in that be also formed with multiple second contacts on the substrate
Area, second isolation barrier include a conductor layer, and second shielding wire covers the conductor layer, and in the second party
Upwards, multiple second contact zones are connected in the conductor layer of corresponding second isolation barrier.
22. semiconductor devices as claimed in claim 21, which is characterized in that second isolation barrier is over the substrate
Second contact zone is completely covered in projection, and in said first direction, the greatest width dimension of second contact zone
Less than the greatest width dimension of second isolation barrier.
23. semiconductor devices as claimed in claim 21, which is characterized in that second isolation barrier includes close to described the
The top isolation part of the bottom isolation part of two contact zones and separate second contact zone, and the institute of second isolation barrier
The width dimensions for stating top isolation part are more than the greatest width dimension of second contact zone；In said first direction, work as institute
The width dimensions for stating the bottom isolation part of the second isolation barrier are less than the top isolation part of second isolation barrier
Width dimensions when, the lower section of the top isolation part of second isolation barrier be also aligned be provided with a support isolation
The position of layer, the bottom isolation part that the support separation layer corresponds to second isolation barrier extends to the table of the substrate
On face.
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| US11856758B2 (en) | 2020-09-24 | 2023-12-26 | Changxin Memory Technologies, Inc. | Method for manufacturing memory and same |
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| CN108962894B (en) * | 2018-06-22 | 2024-01-16 | 长鑫存储技术有限公司 | Method for forming contact by filling groove |
| CN111223860B (en) * | 2018-11-27 | 2024-05-21 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN114005791B (en) * | 2020-07-28 | 2024-05-17 | 长鑫存储技术有限公司 | Memory device and method of forming the same |
| CN114068544A (en) * | 2020-08-04 | 2022-02-18 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
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| US11974427B2 (en) | 2020-09-09 | 2024-04-30 | Changxin Memory Technologies, Inc. | Manufacturing method of a memory and a memory |
| US11985815B2 (en) | 2020-09-24 | 2024-05-14 | Changxin Memory Technologies, Inc. | Method for manufacturing memory and same |
| CN113078056B (en) * | 2021-03-30 | 2022-06-24 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure |
| CN114628504A (en) * | 2022-04-29 | 2022-06-14 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
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