CN107611112A - A kind of fan-out package device - Google Patents
A kind of fan-out package device Download PDFInfo
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- CN107611112A CN107611112A CN201710740416.0A CN201710740416A CN107611112A CN 107611112 A CN107611112 A CN 107611112A CN 201710740416 A CN201710740416 A CN 201710740416A CN 107611112 A CN107611112 A CN 107611112A
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- rewiring
- glass base
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- 239000000758 substrate Substances 0.000 claims abstract description 107
- 239000011521 glass Substances 0.000 claims description 122
- 238000004806 packaging method and process Methods 0.000 claims description 58
- 238000000034 method Methods 0.000 claims description 56
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 238000002161 passivation Methods 0.000 claims description 23
- 229910000679 solder Inorganic materials 0.000 claims description 17
- 230000000903 blocking effect Effects 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 6
- 238000005476 soldering Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 26
- 239000000463 material Substances 0.000 description 13
- 238000000206 photolithography Methods 0.000 description 13
- 239000002313 adhesive film Substances 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 230000003014 reinforcing effect Effects 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 239000003292 glue Substances 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 239000005022 packaging material Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a kind of fan-out package device, the device includes：Package substrate, the package substrate includes glass-base, pad and the first wiring layer again, and the pad is arranged at the glass-base side, described first again wiring layer be arranged at the opposite side of the glass-base, wherein, the pad and the described first wiring layer electrical connection again；Chip, the chip electrically connect with the pad of the package substrate.By the above-mentioned means, embodiment provided by the present invention can prevent chip from shifting, while the line width of wiring layer and line-spacing can be made again narrower.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a fan-out type packaging device.
Background
As the size of the chip is smaller and smaller along with the development of semiconductor technology, the density of I/O (input/output) pins on the surface of the chip is higher and higher, and fan-out type packaging has come to be used, which fans out the high density of I/O pins of the chip into low density of packaging pins.
At present, the existing fan-out packaging method includes the following procedures: providing a carrier plate, attaching a layer of double-sided adhesive film on the carrier plate, attaching the front side of the chip on the adhesive film, carrying out plastic packaging on the chip, stripping the adhesive film and the carrier plate, and forming a rewiring layer, ball planting and cutting on the front side of the chip.
The inventor of the invention finds that the adhesive film is adopted in the fan-out type packaging method, the temperature changes during the plastic packaging of the chip cause the adhesive film to stretch, and the plastic packaging material, the chip and the carrier plate have different Coefficients of Thermal Expansion (CTE) and warp during the plastic packaging, so that the chip generates offset during the plastic packaging. The offset of the chip causes difficulty in subsequent processes such as photolithography alignment; in addition, the rewiring layer of the fan-out package device is limited in narrow line width/pitch.
Disclosure of Invention
The invention mainly solves the technical problem of providing a fan-out type packaging device which can prevent a chip from deviating and can make the line width and the line distance of a rewiring layer narrower.
In order to solve the technical problems, the invention adopts a technical scheme that: providing a fan-out packaged device, the device comprising: the packaging substrate comprises a glass base layer, a pad and a first rewiring layer, wherein the pad is arranged on one side of the glass base layer, the first rewiring layer is arranged on the other side of the glass base layer, and the pad is electrically connected with the first rewiring layer; a chip electrically connected with the pad of the package substrate.
The invention has the beneficial effects that: different from the situation of the prior art, the packaging substrate in the fan-out type packaging device adopted by the invention comprises a glass base layer, a bonding pad and a first rewiring layer, wherein the bonding pad and the first rewiring layer are respectively positioned at two sides of the glass base layer, the bonding pad is electrically connected with the first rewiring layer, and a chip is electrically connected with the bonding pad; on one hand, the packaging substrate comprises a bonding pad, and the chip is electrically connected with the bonding pad of the packaging substrate, so that the conditions that the temperature change of the chip during plastic packaging causes the expansion of a glue film, the warping occurs due to the difference of thermal expansion Coefficients (CTE) of a plastic packaging material, the chip and a carrier plate during plastic packaging, and the like, which are caused by the adoption of a glue film packaging method, and the chip is deviated during plastic packaging are avoided; on the other hand, the packaging substrate comprises a glass substrate, and the glass substrate is an insulator, so that the preparation process of the fan-out type packaging device can be simplified; on the other hand, the welding pads of the packaging substrate and the first rewiring layer are positioned on two opposite sides of the glass substrate, and technical support is provided for subsequently providing a fan-out type packaging structure with a welding ball structure on two sides; in another aspect, the sector packaging method provided by the invention is to fabricate the chip by first fabricating the rewiring layer and then forming the rewiring layer, and the method is narrower in linewidth and linedistance of the rewiring layer than the method of fabricating the chip and then performing rewiring on the chip.
Drawings
FIG. 1 is a schematic flow chart diagram illustrating a fan-out packaging method according to an embodiment of the present invention;
FIG. 2 is a top view of one embodiment of a wafer in the field of semiconductor packaging;
FIG. 3 is a schematic structural diagram of one embodiment of forming a via hole in a glass substrate;
FIG. 4 is a flow chart illustrating a fan-out packaging method according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of an embodiment of a packaged device corresponding to S201-S206 in FIG. 4;
FIG. 6 is a schematic structural diagram of one embodiment of a packaged device corresponding to S207-S215 in FIG. 4;
fig. 7 is a schematic structural diagram of another embodiment of a packaged device corresponding to S207 in fig. 4;
fig. 8 is a schematic structural diagram of another embodiment of a packaged device corresponding to S215 in fig. 4;
FIG. 9 is a flow chart illustrating another embodiment of a fan-out packaging method of the present invention;
FIG. 10 is a schematic structural diagram of an embodiment of a packaged device corresponding to S301-S309 of FIG. 9;
fig. 11 is a schematic structural diagram of another embodiment of a packaged device corresponding to S307 in fig. 9;
FIG. 12 is a schematic structural diagram of another embodiment of a packaged device corresponding to S310-S316 in FIG. 9;
fig. 13 is a schematic structural diagram of another embodiment of a packaged device corresponding to S316 in fig. 9;
FIG. 14 is a flow chart illustrating another embodiment of a fan-out packaging method of the present invention;
FIG. 15 is a schematic structural diagram of an embodiment of a packaged device corresponding to S407-S420 in FIG. 14;
fig. 16 is a schematic structural diagram of another embodiment of a packaged device corresponding to S412 in fig. 14;
fig. 17 is a schematic structural diagram of another embodiment of a packaged device corresponding to S420 in fig. 14;
FIG. 18 is a schematic structural diagram of another embodiment of a fan-out packaging method according to the present invention;
FIG. 19 is a schematic diagram illustrating a structure of an embodiment of a packaged device corresponding to S507-S517 in FIG. 18;
FIG. 20 is a schematic structural diagram of one embodiment of a fan-out packaged device of the present invention;
FIG. 21 is a schematic structural diagram of another embodiment of a fan-out packaged device in accordance with the present invention;
FIG. 22 is a schematic structural diagram of another embodiment of a fan-out packaged device in accordance with the present invention;
FIG. 23 is a schematic structural diagram of yet another embodiment of a fan-out packaged device in accordance with the present invention;
FIG. 24 is a schematic structural diagram of yet another embodiment of a fan-out packaged device in accordance with the present invention.
Detailed Description
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a fan-out packaging method according to an embodiment of the present invention, the method including:
s101: and providing a packaging substrate, wherein the packaging substrate comprises a glass base layer, a bonding pad and a first rewiring layer, the bonding pad is arranged on one side of the glass base layer, the first rewiring layer is arranged on the other side of the glass base layer, and the bonding pad is electrically connected with the first rewiring layer.
In one application scenario, the glass substrate may be directly provided with the bonding pads, as shown in fig. 2, and fig. 2 is a top view of an embodiment of a wafer in the field of semiconductor packaging. The wafer 10 includes a base layer 120 and a pad 100, the base layer 120 has a front surface and a back surface, the pad 100 is formed on the front surface of the base layer 120, and correspondingly, a first redistribution layer is formed on the back surface of the base layer 120; in this embodiment, the base layer 120 is made of glass, and the glass has an insulating property, so that a subsequent process for manufacturing the fan-out package device can be simplified, for example, a step of forming an insulating layer (or a mask layer) on the glass base layer in contact with the glass base layer can be omitted.
Specifically, the step S101 includes: providing a glass substrate provided with bonding pads, i.e. providing a wafer 10 as in fig. 2; a first redistribution layer and a second redistribution layer are respectively formed on two opposite sides of the glass substrate, the second redistribution layer is formed on the pad and electrically connected with the pad, that is, the second redistribution layer is formed on the pad 100 on the front side of the substrate 120 as shown in fig. 2, and the first redistribution layer is formed on the back side of the substrate 120.
Since the glass base layer itself has insulation, for the purpose of electrically connecting the pad with the first redistribution layer, in one embodiment, the glass base layer is provided so that the side thereof having the pad is positioned below before the first redistribution layer is formed; and forming a through hole at a position of the glass substrate opposite to the pad. Referring to fig. 3, in an application scenario, as shown in fig. 3a, a surface of the glass base layer 20 having the bonding pad 22 faces downward, a through hole 24 is formed at a position corresponding to the bonding pad 22 on a side of the glass base layer 20 opposite to the bonding pad 22 by using a laser or a photolithography method, and a cross section of the formed through hole 24 is rectangular; in another application scenario, as shown in fig. 3b, the surface of the glass substrate 26 having the bonding pad 28 faces downward, a through hole 21 is formed at a position corresponding to the bonding pad 28 on a side of the glass substrate 26 opposite to the bonding pad 28 by etching, and a cross section of the through hole 21 is formed to be arc-shaped. Generally, when the thickness of the glass substrate is thicker, for example > 100um, the through holes can be formed directly by laser or photolithography; when the glass substrate is thin, for example < 100um, the through hole can be formed by etching, for example, dry etching or wet etching; of course, when the glass substrate is thicker, the side of the glass substrate opposite to the bonding pad may be ground to reduce the thickness, and then the through hole is formed by etching, laser, or photolithography. In other embodiments, other ways of forming vias or other ways of electrically connecting pads with the first redistribution layer may be used.
S102: the chip is electrically connected to the bonding pad of the package substrate.
Specifically, when a second redistribution layer is formed on the pad on the front side of the glass substrate, the step S102 is specifically: electrically connecting the chip with the second rewiring layer and electrically connecting the chip with the bonding pad through the second rewiring layer; in an application scene, the chip is provided with the metal salient points, the chip is electrically connected with the second rewiring layer in a mode of reflow soldering of the metal salient points and the second rewiring layer, and the mode can avoid the situation that the position of the chip deviates due to the fact that a glue film is heated and softened in the subsequent chip plastic package process.
The above-described packaging method will be described in further detail below in terms of several specific embodiments.
In a first embodiment, please refer to fig. 4, fig. 4 is a flow chart illustrating a fan-out packaging method according to an embodiment of the present invention; the method comprises the following steps:
s201: providing a glass substrate provided with a bonding pad; specifically, referring to fig. 5a, in an application scenario, the package substrate includes a glass substrate 30 directly provided with a pad 32;
s202: forming a first passivation layer on one side of the glass base layer, which is provided with the bonding pad, and arranging a first opening at the position, corresponding to the bonding pad, of the first passivation layer; specifically, referring to fig. 5b, in one embodiment, a first passivation layer 34 is first coated on the surface of the glass substrate 30, and then a first opening 340 is formed at a position of the first passivation layer 34 corresponding to the pad 32 by exposure, development or other means, so that the pad 32 is exposed; in another embodiment, a dielectric layer (not shown) may be further formed on a surface of the first passivation layer 34 opposite to the glass substrate 30, and an opening (not shown) is also formed on the dielectric layer corresponding to the pad 34 to expose the pad 32.
S203: forming a first seed layer on the surface of the first passivation layer opposite to the glass substrate; specifically, referring to fig. 5c, in one embodiment, the material of the first seed layer 36 is one or a mixture of titanium, aluminum, copper, gold, and silver, and the process of forming the first seed layer 36 is a sputtering process or a physical vapor deposition process.
S204: forming a first mask layer on the surface of the first seed layer, which is opposite to the glass substrate, and arranging a second opening at the position, corresponding to the bonding pad, of the first mask layer; specifically, referring to fig. 5d, the material of the first mask layer 38 is one or more of photoresist, silicon oxide, silicon nitride, and amorphous carbon, in the embodiment, the material of the first mask layer 38 is photoresist, a second opening 380 penetrating through the first mask layer 38 is formed in the first mask layer 38 by using a photolithography process, and the second opening 380 is located above the pad 32.
S205: forming a second rewiring layer in the second opening; specifically, referring to fig. 5e, in one embodiment, an electroplating process is used to form a second redistribution layer 31 in the second opening 380, and the material of the second redistribution layer 31 is copper or other suitable metal. In this embodiment, the height of the second redistribution layer 31 is lower than the depth of the second opening 380, and in other embodiments, the height of the second redistribution layer 31 may be the same as the depth of the second opening 380.
S206: removing the first seed layer except the first mask layer and the second rewiring layer; specifically, referring to fig. 5f, in one embodiment, the first mask layer 38 is removed by photolithography to expose a portion of the first seed layer 36; then, removing part of the exposed first seed layer 36 by using a wet etching process or a dry etching process, and only remaining the first seed layer 36 positioned below the second rewiring layer 31; the pad 32, the first seed layer 36, and the second redistribution layer 31 are electrically connected.
S207: electrically connecting the chip with a bonding pad of a package substrate; specifically, in an application scenario, as shown in fig. 6a, a metal bump 400 is disposed on a surface of a chip 40, and the metal bump 400 of the chip 40 is reflow-soldered to the second redistribution layer 31, so that the chip 40 is electrically connected to the second redistribution layer 31 and is electrically connected to a pad 32 through the second redistribution layer 31; in another application scenario, step S207 further includes: forming a passivation layer 50 on the second redistribution layer 31, and providing an opening 500 on the passivation layer 50 (as shown in fig. 7 a), providing a metal bump 520 on the surface of the chip 52, and performing reflow soldering on the metal bump 520 of the chip 52 and the second redistribution layer 31 through the opening 500, so that the chip 52 is electrically connected to the second redistribution layer 31 and the pad 32 through the second redistribution layer 31 (as shown in fig. 7 b); in the above two embodiments, the chip 40 or 52 is flip-chip mounted, and in other embodiments, the chip 40 or 52 may also be face-mounted, which is not limited in the present invention.
S208: plastically packaging the chip and one side of the glass substrate on which the second rewiring layer is formed; in particular, see fig. 6 b; in one embodiment, the surface of the glass substrate 30 having the bonding pads 32 is filled with liquid or powder resin, so that the chip 40 and the second redistribution layer 31 are all covered in the resin material, and the molding layer 42 is formed after curing.
S209: arranging the glass substrate in a state that one side of the glass substrate, which is provided with the bonding pad, is positioned below the bonding pad, and forming a through hole at the position of the glass substrate, which is back to the bonding pad; specifically, referring to fig. 6c, the manner of forming the through hole 44 is mentioned in the above embodiment, and is not described herein again, in this embodiment, the through hole 44 may be formed by laser or photolithography, and the cross section of the through hole 44 is rectangular.
S210: forming a third sub-layer on one side of the glass base layer, which is opposite to the bonding pad, wherein the third sub-layer is directly contacted with the glass base layer; specifically, referring to fig. 6d, in one embodiment, the material of the third sub-layer 46 is one or a mixture of titanium, aluminum, copper, gold, and silver, and the process of forming the third sub-layer 46 is a sputtering process or a physical vapor deposition process.
S211, forming a third mask layer on the surface of the third seed layer opposite to the glass substrate, and forming a sixth opening on the third mask layer; specifically, referring to fig. 6e, the material of the third mask layer 48 is one or more of photoresist, silicon oxide, silicon nitride, and amorphous carbon, in this embodiment, the material of the third mask layer 48 is photoresist, and a sixth opening 480 penetrating through the third mask layer 48 is formed in the third mask layer 48 by using a photolithography process.
S212: forming a first rewiring layer in the sixth opening; specifically, referring to fig. 6f, in one embodiment, a first redistribution layer 41 is formed in the sixth opening 480 by an electroplating process, and the material of the first redistribution layer 41 is copper or other metal. In fig. 6f, the first redistribution layer 41 fills the sixth opening 480, and in other embodiments, the first redistribution layer 41 may also be filled with a layer in the sixth opening 480, and the thickness thereof may be designed according to practical situations, which is not limited by the present invention.
S213: removing the third mask layer and a third sublayer except the first rewiring layer; specifically, please refer to fig. 6g, the process is similar to step S206 and is not repeated here.
S214: arranging a first blocking layer on the surface, opposite to the glass base layer, of the first rewiring layer, and forming a seventh opening on the first blocking layer; specifically, referring to fig. 6h, the material of the first barrier layer 43 has an insulating property, and in one embodiment, the seventh opening 430 is formed on the first barrier layer 43 by photolithography or other etching methods.
S215: arranging a solder ball; in an application scenario, referring to fig. 6i, a solder ball may be directly disposed in the seventh opening 430, for example, a ball mounting machine is used to mount the solder ball 45 in the seventh opening 430, and the solder ball 45 is made of tin or tin alloy. Wherein the solder balls 45 and the first redistribution layer 41 are electrically connected; in another application scenario, referring to fig. 8, ball mounting may be performed in a manner of forming an under-ball metal layer on the first redistribution layer 41; specifically, a fourth sub-layer 60 is formed on the surface of the first barrier layer 43 opposite to the glass substrate 30 (as shown in fig. 8 a), and the fourth sub-layer 60 may be formed by sputtering a titanium layer and then sputtering a copper layer on the titanium layer; forming a fourth masking layer 62 on the surface of the fourth sub-layer opposite to the glass substrate 30, and forming an eighth opening 620 (shown in fig. 8 b) on the fourth masking layer 62 corresponding to the seventh opening 430; forming an under-ball metal layer 64 in the eighth opening 620 (as shown in fig. 8 c), where the material of the under-ball metal layer 64 may be copper, and may be formed by electroplating; removing the fourth mask layer 62 and the corresponding fourth sub-layer 60 under the fourth mask layer 62 (as shown in fig. 8 d); forming solder balls 66 on the positions corresponding to the under-ball metal layers 64, dropping the solder balls 66 to the positions corresponding to the under-ball metal layers 64 by a ball-mounting machine, and reflowing (as shown in fig. 8 e); the solder balls 66, the ubm layer 64, the fourth sub-layer 60, and the first redistribution layer 41 are electrically connected.
In a second embodiment, please refer to fig. 9, fig. 9 is a schematic flow chart of another fan-out packaging method according to another embodiment of the present invention, the method is mainly different from the first embodiment in that providing a package substrate includes: the reinforcing plate is attached to one side of the base layer, which is back to the bonding pad, and the specific flow is as follows:
s301: providing a glass base layer provided with a bonding pad, and attaching a reinforcing plate to one side of the glass base layer, which is back to the bonding pad; specifically, referring to fig. 10a, the glass substrate 70 with a thickness less than or equal to a predetermined thickness may be selected at the beginning according to actual requirements, for example, when the predetermined thickness is 100um, the glass substrate 70 with a thickness of 50, 60, 80um, etc. may be directly selected; in order to prevent the strength of the glass substrate 70 from being insufficient in the subsequent manufacturing process, in this embodiment, a reinforcing plate 74 is attached to a side of the glass substrate 70 opposite to the pad 72, the reinforcing plate 74 may be made of glass, metal, silicon wafer, or the like, and the reinforcing plate 74 and the glass substrate 70 may be attached and fixed by a double-sided adhesive film.
S302-S308 are the same as S202-S208 in the above embodiments, and are not repeated herein, and the schematic structural diagrams thereof can be seen in FIGS. 10b-10 h; the package structure corresponding to step S307 can also be referred to fig. 11.
S309: removing the reinforcing plate; specifically, as shown in fig. 10i, in one embodiment, the reinforcing plate 74 and the glass substrate 70 are adhered by a double-sided adhesive film, which can be directly peeled off, so as to remove the reinforcing plate 74.
S310: arranging the glass substrate in a state that one side of the glass substrate, which is provided with the bonding pad, is positioned below the bonding pad, and forming a through hole at the position of the glass substrate, which is back to the bonding pad; specifically, referring to fig. 12a, since the glass substrate has a relatively thin thickness in this embodiment, a through hole may be formed by etching, and a cross section of the through hole is arc-shaped, but in other embodiments, a laser or photolithography method may also be used, which is not limited in this disclosure.
S311-S316 are the same as S210-S215 in the above embodiment, and their corresponding structures can be seen in fig. 12b-12g, wherein the manner of disposing solder balls in step S316 can also be seen in fig. 13.
In a third embodiment, please refer to fig. 14, fig. 14 is a schematic flow chart of another fan-out packaging method according to another embodiment of the present invention, the method mainly differs from the first embodiment in that a side of the glass substrate having the bonding pads can perform multiple wiring, that is, at least one redistribution layer is formed on a side of the second redistribution layer opposite to the glass substrate, in this embodiment, the side of the glass substrate having the bonding pads includes two wiring layers, and the specific flow is as follows:
S401-S406 are the same as S201-S206 in the above embodiments, and are not described herein, and their structures can be seen in FIGS. 5a-5 f.
S407: forming a first dielectric layer on the surface of the second rewiring layer opposite to the glass substrate, and arranging a third opening on the first dielectric layer; specifically, referring to fig. 15a, in one embodiment, the first dielectric layer 80 is made of a photoresist, and after a layer of photoresist is coated on the surface of the second redistribution layer 31, a third opening 800 is formed in the first dielectric layer 80 by using a photolithography process.
S408: forming a second seed layer on the surface of the first dielectric layer opposite to the glass substrate; specifically, referring to fig. 15b, in one embodiment, a second seed layer 82 may be formed on a surface of the first dielectric layer 80 opposite to the glass substrate 30 by a sputtering process, and the material of the second seed layer 82 is copper, titanium, or other metal.
S409: forming a second mask layer on the surface of the second seed layer, which is opposite to the glass substrate, and arranging a fourth opening on the second mask layer; specifically, referring to fig. 15c, in one embodiment, the second mask layer 84 is made of a photoresist, and a photolithography process is used to form the fourth opening 840.
S410: forming a third rewiring layer in the fourth opening; specifically, referring to fig. 15d, an electroplating process may be used to form a third redistribution layer 86 in the fourth opening 840, where the material of the third redistribution layer 86 may be a metal such as copper; in fig. 15d, the third redistribution layer 86 fills the entire fourth opening 840, in other embodiments, the third redistribution layer 86 may only be laid in the fourth opening 840 by one layer, and the thickness may be set according to actual conditions.
S411: removing the second mask layer and the second seed layer except the third rewiring layer; specifically, please refer to fig. 15 e; the second redistribution layer 31, the second seed layer 82, and the third redistribution layer 86 are electrically connected.
S412: electrically connecting the chip with a bonding pad of a package substrate; specifically, the step is similar to step S207 in the foregoing embodiment, the metal bump 880 is disposed on the surface of the chip 88, the metal bump 880 of the chip 88 and the third redistribution layer 86 may be reflow-soldered, so that the chip 88 is electrically connected to the third redistribution layer 86 and is electrically connected to the pad 32 through the third redistribution layer 86 (as shown in fig. 15 f), or the passivation layer is disposed on the third redistribution layer 86 (as shown in fig. 16), a second passivation layer is formed on the third redistribution layer, a fifth opening (not shown) is disposed on the second passivation layer, a metal bump is disposed on the surface of the chip, and the metal bump of the chip and the third redistribution layer through the fifth opening are reflow-soldered, so that the chip and the third redistribution layer are electrically connected, and are electrically connected to the pad through the third redistribution layer.
S413-S420 are the same as S208-S215 in the above embodiments, and are not described herein, and the structure thereof can be seen in FIGS. 15g-15 n; the structure of step S420 can also be seen in fig. 17.
In a fourth embodiment, please refer to fig. 18, fig. 18 is a schematic flow chart of a fan-out package method according to another embodiment of the present invention, which is mainly different from the first embodiment in that after the rewiring is completed on both sides of the glass substrate, the package substrate is formed first, and then the package substrate is electrically connected to the chip, and the specific flow is as follows:
S501-S506 are the same as S201-S206 in the above embodiments, and are not described herein, and the structure thereof can be seen in FIGS. 5a-5 f.
S507-S511 are the same as S209-S213 in the above embodiments, and are not repeated herein, and the structure thereof can be seen in fig. 19a-19e, wherein, in order to avoid the glass substrate from being broken during the formation of the through hole in step S507, the step may further include before the formation of the through hole: and providing a substrate, and attaching the substrate to one side of the glass base layer with the bonding pad.
S512: providing a carrier plate, and connecting one side of the glass substrate, on which the first rewiring layer is formed, with the carrier plate; specifically, referring to fig. 19f, the carrier may be made of glass, metal, or the like, and the carrier and one side of the first redistribution layer may be connected by a double-sided adhesive film.
S513: arranging the glass substrate in a state that one side with the bonding pad is positioned above, and electrically connecting the chip with the bonding pad of the packaging substrate; specifically, this step is the same as step S207 in the above embodiment, and may adopt a manner of flip-chip mounting the chip on the second redistribution layer (as shown in fig. 19 g), or may adopt a manner of disposing a passivation layer on the second redistribution layer, which is not described herein again.
S514: the side of the chip and the glass substrate on which the second rewiring layer is formed is subjected to plastic packaging, specifically, the step is the same as step S208 in the above embodiment, as shown in fig. 19 h.
S515: removing the carrier plate; specifically, as shown in fig. 19i, when the carrier board and the first redistribution layer are connected by adhesive film, the carrier board may be removed by peeling off the adhesive film.
S516: arranging a first blocking layer on the surface, opposite to the glass base layer, of the first rewiring layer, and forming a seventh opening on the first blocking layer; specifically, this step is the same as step S214 in the above embodiment, as shown in fig. 19 j.
S517: disposing solder balls on the first redistribution layer; specifically, this step is the same as step S215 in the above-described embodiment, as shown in fig. 19k or fig. 8.
The above illustration shows only four specific embodiments, and it is within the scope of the present invention to provide a fan-out packaging method involving a glass substrate having rewiring on the side opposite to the bond pads.
Referring to fig. 20, fig. 20 is a schematic structural diagram of a fan-out package device according to an embodiment of the present invention, the device including: the package substrate 90 includes a glass base layer 900, a pad 902, and a first redistribution layer 904, wherein the pad 902 is disposed on one side of the glass base layer 900, the first redistribution layer 904 is disposed on the other side of the glass base layer 900, the pad 902 is electrically connected to the first redistribution layer 904, and the chip 92 is electrically connected to the pad 902 of the package substrate 90.
In one application scenario, the glass substrate 900 may be directly provided with the pad 902; in another application scenario, due to poor conductivity of the glass base layer 900, in order to electrically connect the pad 902 and the first redistribution layer 904 on opposite sides of the glass base layer 900, a through hole 906 is disposed on a side of the glass base layer 900 opposite to the pad 902, and the position of the through hole 906 corresponds to the position of the pad 902, so that the first redistribution layer 904 is electrically connected to the pad 902 through the through hole 906. In this embodiment, the through-hole 906 is formed by laser or photolithography, and the cross-section of the through-hole 906 is rectangular.
In another application scenario, with continued reference to fig. 20, the package substrate 90 further includes a second redistribution layer 908, and the second redistribution layer 908 is disposed on the pad 902 and electrically connected to the pad 902.
The structure of the fan-out package device provided by the present invention will be further described with respect to several specific embodiments.
Continuing to refer to fig. 20, in one embodiment, the side of the glass substrate 900 facing away from the pad 902 includes, in addition to the first redistribution layer 904: a third sub-layer 901, wherein the third sub-layer 901 is in direct contact with the glass substrate 900; the first redistribution layer 904, the third sublayer 901 and the pad 902 are electrically connected; a first blocking layer 903 disposed on a side of the first redistribution layer 904 opposite to the glass substrate 900, and a seventh opening (not shown) is formed on the first blocking layer 903; solder balls 905 are disposed in the seventh opening (not labeled) and electrically connected to the first redistribution layer 904. The side of the glass base layer 900 on which the pads 902 are provided includes, in addition to the second re-wiring layer 908, the device further including: a first passivation layer 907 disposed between the pad 902 side of the glass substrate 900 and the second redistribution layer 908, and a first opening (not labeled) is disposed at a position of the first passivation layer 907 corresponding to the pad 902; a first seed layer 909 disposed between the first passivation layer 907 and the second rewiring layer 908; the pad 902, the first seed layer 909, and the second rewiring layer 908 are electrically connected. A metal bump 920 is arranged on the chip 92, and the chip 92 is in reflow soldering with the second re-wiring layer 908 through the metal bump 920; and the plastic sealing layer 911, wherein the plastic sealing layer 911 covers the chip 92 and one side of the glass base layer 900, which is provided with the bonding pad 902.
Referring to fig. 21, fig. 21 is a schematic structural diagram of another embodiment of a fan-out package device according to the present invention; in this embodiment, the difference between the packaged device and the packaged device in fig. 20 is that the through hole is formed in the glass substrate by etching, and the cross section of the through hole is arc-shaped.
Referring to fig. 22, fig. 22 is a schematic structural diagram of another embodiment of a fan-out package device according to the present invention; in this embodiment, the difference between the packaged device and the packaged device in fig. 20 is that solder balls are disposed on a side of the glass substrate opposite to the pads, and an under-ball metal layer is disposed in this embodiment. Specifically, the packaged device includes, in addition to the structure in fig. 20 described above, further: a fourth sub-layer 1002 covering the seventh opening (not labeled) of the first barrier layer 1000 and disposed on a side of the first barrier layer 1000 opposite to the glass substrate 1004; the ubm layer 1006 is disposed on a side of the fourth sub-layer 1002 opposite to the glass substrate 1004; the solder balls 1008 are arranged on one side of the under-ball metal layer 1006 opposite to the glass substrate 1004; the solder balls 1008, the ubm layer 1006, the fourth sub-layer 1002, and the first redistribution layer 1001 are electrically connected.
Referring to fig. 23, fig. 23 is a schematic structural diagram of a fan-out package device according to yet another embodiment of the present invention; in this embodiment, the packaged device is different from the packaged device in fig. 20 above in that a plurality of rewiring processes may be performed on the side of the glass substrate on which the pads are disposed, for example, twice wiring processes are performed on the side of the glass substrate on which the pads are disposed, that is, the side of the second rewiring layer 1102 opposite to the glass substrate 1100 further includes a third rewiring layer 1104. Specifically, the structure of the packaged device that is the same as that in fig. 20 is not described herein again, and the packaged device in this embodiment further includes: a first dielectric layer 1106 disposed between the second redistribution layer 1102 and the third redistribution layer 1104, wherein a third opening (not shown) is disposed on the first dielectric layer 1106; a second seed layer 1108 disposed between the first dielectric layer 1106 and the third redistribution layer 1104; wherein the second redistribution layer 1102, the second seed layer 1108, and the third redistribution layer 1104 are electrically connected; the surface of the chip 112 is provided with a metal bump 1120, and the chip 112 is reflow-soldered to the third redistribution layer 1104 through the metal bump 1120.
Referring to fig. 24, fig. 24 is a schematic structural diagram of a fan-out package device according to still another embodiment of the present invention; in the present embodiment, the packaged device is different from the packaged device in fig. 23 above in the manner in which the chip is electrically connected to the third rewiring layer. Specifically, as shown in fig. 24, the packaged device further includes: the second passivation layer 1200 is disposed on a side of the third redistribution layer 1202 opposite to the glass substrate 1204, the second passivation layer 1200 is provided with a fifth opening, the surface of the chip 122 is provided with a metal bump 1220, and the metal bump 1220 of the chip 122 is reflow-welded to the third redistribution layer 1202 through the fifth opening.
In other embodiments, the package device may also have other structures, and the present invention is not limited thereto. In summary, different from the situation of the prior art, the package substrate in the fan-out package method adopted by the present invention includes a glass base layer, a pad and a first redistribution layer, where the pad and the first redistribution layer are respectively located at two sides of the glass base layer, the pad is electrically connected to the first redistribution layer, and the chip is electrically connected to the pad; on one hand, the packaging substrate comprises a bonding pad, and the chip is electrically connected with the bonding pad of the packaging substrate, so that the conditions that the temperature change of the chip during plastic packaging causes the expansion of a glue film, the warping occurs due to the difference of thermal expansion Coefficients (CTE) of a plastic packaging material, the chip and a carrier plate during plastic packaging, and the like, which are caused by the adoption of a glue film packaging method, and the chip is deviated during plastic packaging are avoided; on the other hand, the packaging substrate comprises a glass substrate, and the glass substrate is an insulator, so that the preparation process of the fan-out type packaging device can be simplified; on the other hand, the welding pads of the packaging substrate and the first rewiring layer are positioned on two opposite sides of the glass substrate, and technical support is provided for subsequently providing a fan-out type packaging structure with a welding ball structure on two sides; in another aspect, the sector packaging method provided by the invention is to fabricate the chip by first fabricating the rewiring layer and then forming the rewiring layer, and the method is narrower in linewidth and linedistance of the rewiring layer than the method of fabricating the chip and then performing rewiring on the chip.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A fan-out packaged device, the device comprising:
the packaging substrate comprises a glass base layer, a pad and a first rewiring layer, wherein the pad is arranged on one side of the glass base layer, the first rewiring layer is arranged on the other side of the glass base layer, and the pad is electrically connected with the first rewiring layer;
a chip electrically connected with the pad of the package substrate.
2. The device of claim 1,
the packaging substrate further comprises a second re-wiring layer, and the second re-wiring layer is arranged on the bonding pad and electrically connected with the bonding pad.
3. The device of claim 1,
and a through hole is formed in one side of the glass base layer, which is opposite to the bonding pad, and the position of the through hole corresponds to that of the bonding pad, so that the first rewiring layer is electrically connected with the bonding pad through the through hole.
4. The device of claim 3,
the through hole is formed by a laser or etching or photoetching method;
the cross section of the through hole formed by the laser method is rectangular, the cross section of the through hole formed by the etching method is arc-shaped, and the cross section of the through hole formed by the photoetching method is rectangular.
5. The device of claim 1, wherein a side of the pad of the glass substrate includes, in addition to a second re-routing layer, the device further comprising:
the first passivation layer is arranged between one side of the bonding pad of the glass base layer and the second rewiring layer, and a first opening is formed in the position, corresponding to the bonding pad, of the first passivation layer;
a first seed layer disposed between the first passivation layer and the second re-wiring layer;
wherein the bonding pad, the first seed layer, and the second re-wiring layer are electrically connected.
6. The device of claim 5, wherein a side of the pad of the glass base layer includes a third re-routing layer in addition to a second re-routing layer on a side of the second re-routing layer opposite the glass base layer, the device further comprising:
a first dielectric layer disposed between the second redistribution layer and the third redistribution layer, and having a third opening formed thereon;
a second seed layer disposed between the first dielectric layer and the third re-wiring layer;
wherein the second re-wiring layer, the second seed layer, and the third re-wiring layer are electrically connected.
7. The device of claim 6,
the surface of the chip is provided with a metal bump, and the chip is in reflow soldering with the third rewiring layer through the metal bump; or,
the device further comprises a second passivation layer, wherein the second passivation layer is arranged on one side, back to the glass base layer, of the third rewiring layer, a fifth opening is formed in the second passivation layer, a metal bump is arranged on the surface of the chip, and the metal bump of the chip is in reflow soldering with the third rewiring layer through the fifth opening.
8. The device of claim 1, further comprising:
and the plastic packaging layer covers the chip and one side of the glass base layer, which is provided with the bonding pad.
9. The device of claim 1, wherein a side of the glass base layer facing away from the pad comprises a first rewiring layer, the device further comprising:
the third sublayer is arranged between one side, back to the bonding pad, of the glass base layer and the first rewiring layer;
wherein the first redistribution layer, the third sublayer, and the pad are electrically connected.
10. The device of claim 9, further comprising:
the first blocking layer is arranged on one side, back to the glass base layer, of the first rewiring layer, and a seventh opening is formed in the first blocking layer; the solder balls are arranged in the seventh openings and are electrically connected with the first rewiring layer; or,
the first blocking layer is arranged on one side, back to the glass base layer, of the first rewiring layer, and a seventh opening is formed in the first blocking layer; a fourth sub-layer covering the seventh opening and disposed on a side of the first barrier layer opposite to the glass substrate; the under-ball metal layer is arranged on one side, back to the glass base layer, of the fourth sub-layer; the solder balls are arranged on one side, back to the glass substrate, of the metal layer below the balls; wherein the solder balls, the UBM layer, the fourth sub-layer, and the first redistribution layer are electrically connected.
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| CN201710740416.0A CN107611112A (en) | 2017-08-24 | 2017-08-24 | A kind of fan-out package device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109671700A (en) * | 2018-12-26 | 2019-04-23 | 华进半导体封装先导技术研发中心有限公司 | A kind of fan-out-type chip-packaging structure and its manufacturing method |
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Application publication date: 20180119 |