[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

CN107591334B - 用于放置在具有高k介电栅极的半导体主动区内的栅极接触的方法及设备 - Google Patents

用于放置在具有高k介电栅极的半导体主动区内的栅极接触的方法及设备 Download PDF

Info

Publication number
CN107591334B
CN107591334B CN201710545803.9A CN201710545803A CN107591334B CN 107591334 B CN107591334 B CN 107591334B CN 201710545803 A CN201710545803 A CN 201710545803A CN 107591334 B CN107591334 B CN 107591334B
Authority
CN
China
Prior art keywords
gate
trench
layer
disposed
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710545803.9A
Other languages
English (en)
Other versions
CN107591334A (zh
Inventor
恩德·拉伯特
谢瑞龙
张洵渊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries US Inc
Original Assignee
GlobalFoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GlobalFoundries Inc filed Critical GlobalFoundries Inc
Publication of CN107591334A publication Critical patent/CN107591334A/zh
Application granted granted Critical
Publication of CN107591334B publication Critical patent/CN107591334B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832—Multiple layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明涉及用于放置在具有高K介电栅极的半导体主动区内的栅极接触的方法及设备，其中，一种方法提供在Rx区中具有FinFET的结构，该FinFET包括沟道、源极/漏极(S/D)区及栅极，该栅极包括栅极金属。在具有高k介电性衬垫与核心的栅极上方形成覆盖体。该栅极的各侧上布置沟槽硅化物(TS)。使该TS凹陷至高于该栅极的层阶且低于该覆盖体的层阶的层阶。在该结构上方布置氧化物层。在该Rx区里的氧化物层内图型化CB沟槽，以在该CB沟槽的中间部分处使核心与衬垫曝露。相对于衬垫而选择性蚀刻核心，以将CB沟槽延展至栅极金属处的底端。金属化CB沟槽以形成CB接触部。

Description

用于放置在具有高K介电栅极的半导体主动区内的栅极接触 的方法及设备
技术领域
本发明是关于半导体装置及其制作方法。更具体地说，本发明是关于一种在半导体结构的主动区内置放栅极接触部的方法及设备。
背景技术
先前技术半导体技术(例如：40纳米(nm)、14nm及更先进的技术节点)目前在栅极结构的一部分上布置有大部分栅极(CB)接触部，该部分位于任何主动(Rx)区外侧及隔离区上方，诸如浅沟槽隔离(STI)区、深沟槽隔离区或类似者上方。目的在于防止电气短路至源极/漏极(CA)接触部或下层沟槽硅化物(TS)层的高风险。
CB接触部短路至TS层的可能性特别会造成问题。原因在于，TS层纵向跨布整个Rx区延展，为的是要确保即使在最坏情况的错准条件下，与鳍片阵列中的FinFET的源极/漏极(S/D)有适当的电接触。因此，即使CA接触部可位于Rx区的局部化区域中离CB接触部够远处以防短路，但TS层无法如此。
在先前技术10nm技术及更先进的技术中，栅极电极金属上方的自对准接触(SAC)氮化物覆盖体用于防止CA接触部与栅极金属之间出现短路。SAC覆盖体是由单一材料所组成，典型为氮化硅(SiN)，其大体上与上方布置有SAC覆盖体的栅极间隔物具有相同或类似的材料组成。于栅极间隔物与SAC覆盖体之间，栅极金属与TS区完全隔离。在有此类覆盖体的情况下，有可能在栅极金属的层阶下面做出深TS凹口，以企图避免短路至潜在布置于Rx区中的CB接触部。
不过，还是有问题，关于TS层可凹陷到多深而不会不可接受地使穿过TS层的电阻增加，这方面仍有所限制。因此，即是有了此一深TS层凹口，布置于栅极上方的CB接触部仍与凹陷的TS变得太过接近而无法可靠制造。
在Rx区外侧置放CB接触部不利于扩缩，对于10nm技术节点及更先进节点尤其如此。另外，布置于隔离区上方的CB接触部有另外的设计要求，对于比例缩小又造成更多问题。举例而言，隔离区上方的CB接触部必须总是位于两个Rx区之间，必须在CB接触部与鳍片与TS区之间具有最小间隔，诸如此类等等。
因此，需要有一种能够在半导体结构的Rx区内置放CB接触部的方法及设备。此外，此类方法及设备需要具备能可靠制造性。
发明内容
本发明通过提供一种在半导体结构的Rx区内置放CB接触部的方法与设备，提供优于先前技术的优点与替代方案。此外，该方法与设备不仅改良半导体结构的尺寸调整能力，而且还具备可轻易制造性。
一种根据本发明的一或多项态样在半导体结构的Rx区中置放CB接触部的方法，包括：提供在Rx区中布置有FinFET的结构。该FinFET包括布置于一对源极/漏极(S/D)区之间的沟道、及布置于该沟道上方的栅极(CB)。该栅极包括布置于栅极间隔物之间的栅极金属。该栅极上方形成覆盖体，该覆盖体具有围绕内核布置的高k介电性外衬垫。在该S/D区上方该栅极的相对侧上形成沟槽硅化物(TS)层。使该TS层凹陷至高于该栅极的层阶且低于该覆盖体的层阶的层阶。在该结构上方布置氧化物层。在氧化物层内图型化CB沟槽，以在该CB沟槽的中间部分处使核心曝露。CB沟槽位于Rx区内。相对于该衬垫而选择性蚀刻该核心，以使该CB沟槽进一步延展至沟槽底端，并且使该栅极金属曝露。金属化该CB沟槽以形成电连接至该栅极金属的CB接触部。
在本发明的另一态样中，一种半导体结构，包括布置于Rx区中的FinFET。该FinFET包括布置于一对源极/漏极(S/D)区之间的沟道、及布置于该沟道上方的栅极。该栅极包括布置于栅极间隔物之间的栅极金属。布置于该栅极上方的覆盖体，其包括围绕内核布置的高k介电性外衬垫。该覆盖体与核心自该栅极向上延展至实质相同第一覆盖体层阶。在该S/D区上方该栅极的相对侧上布置沟槽硅化物(TS)层。该TS层具有高于该栅极的层阶且低于该覆盖体层阶的层阶。在该结构上方布置氧化物层。在氧化物层内及Rx区上方布置CB沟槽。该CB沟槽向下延展至实质位于该覆盖体层阶处的沟槽中间部分，并且自该中间部分进一步延展至沟槽底端。该沟槽底端包括该栅极金属。CB接触部布置于该CB沟槽内并且电连接至该栅极金属。
附图说明
搭配附图经由以下详细说明将会更完全理解本发明，其中：
图1A根据本发明，是半导体结构在中间制造阶段的简化俯视平面图；
图1B根据本发明，是图1A沿着线条1B-1B取看的简化截面图；
图2根据本发明，是图1B有栅极凹陷之后的截面图；
图3根据本发明，是图2具有保护层及布置于其上的衬垫层的截面图；
图4根据本发明，是图3有保护层及衬垫层受各向异性蚀刻而使栅极的栅极金属曝露的截面图；
图5根据本发明，是图4有覆盖体形成于其上的截面图；
图6根据本发明，是图5有TS层布置于其上的截面图；
图7根据本发明，是图6有TS层凹陷的截面图；
图8根据本发明，是图7有氧化物层布置于其上的截面图；
图9A根据本发明，是图8展示结构100的特征的俯视平面图，该特征下铺于氧化物层(以假想线边界表示)，其中氧化物层中布置一对CA沟槽，而虚线周界表示氧化物层中尚待形成CB沟槽的目标位置。
图9B根据本发明，是图9A沿着线条9B-9B取看的简化截面图；
图9C根据本发明，是图9A沿着线条9C-9C取看的简化截面图；
图10A根据本发明，是图9B具有布置于其上的有机平坦化层(OPL)、及布置于该OPL内的CB沟槽的截面图；
图10B根据本发明，是图9C具有OPL布置于其上的截面图；
图11A根据本发明，是图10A具有蚀刻于氧化物层内的CB沟槽的截面图；
图11B根据本发明，是图10B的截面图；
图12A根据本发明，是图11A具有向下蚀刻至栅极的栅极金属的CB沟槽的截面图；
图12B根据本发明，是图11B的截面图；
图13A根据本发明，是图12A具有经金属化用以形成CB接触部的CB沟槽的截面图；以及
图13B根据本发明，是图12B具有经金属化用以形成CA接触部的CA沟槽的截面图。
具体实施方式
现将说明某些例示性具体实施例以便整体理解本文所揭示方法、系统及装置其结构、功能、制造及使用的原理。附图中绘示这些具体实施例的一或多项实施例。本领域技术人员将会理解本文中具体所述、及附图中所示的方法、系统及装置为非限制性例示性具体实施例，而且本发明的范畴仅由权利要求书来界定。搭配一项例示性具体实施例所示或所述的特征可与其它具体实施例的特征组合。此类修改及变动用意是要包括于本发明的范畴内。
图1A至13B根据本发明，绘示用于在半导体结构的主动(Rx)区内置放栅极(CB)接触部的一种方法与设备的各项例示性具体实施例。
请参阅图1A及1B，介绍根据本发明的半导体结构100在中间制造阶段沿着线条1B-1B取看的简化俯视平面图及简化截面图的例示性具体实施例。在程序流程的这个阶段，半导体结构100包括具有鳍片104的衬底102，该鳍片自衬底102起向上垂直延展，并且跨布该衬底水平延展，用以界定衬底102的主动(Rx)区106。鳍片104布置于跨布衬底102的Rx区106延展的平行鳍片阵列中(看图1A最清楚)。鳍片104在虚设栅极108终止，其位在Rx区106的边缘处跨布鳍片104的远端而侧向延展。虚设栅极108用于诱使源极/漏极(S/D)区110在鳍片104位于虚设栅极108与相邻主动栅极112之间的部分上对称磊晶生长。
所示虽然仅一个主动栅极112，但栅极112仍可以是沿着主动区106内的鳍片104布置的多个主动栅极112(例如：从数个到数千个及更大数量)。栅极112大体上垂直于Rx区106内的鳍片104延展，并且亦可实质延展到隔离区114内。另外，所示虽然仅两个S/D区110，典型仍有S/D区110磊晶生长到介于Rx区106内许多栅极112的各者之间、及介于Rx区106的边界处的主动栅极112与虚设栅极108之间的鳍片104内。
与Rx区106毗连旳是隔离区114，诸如浅沟槽隔离(STI)区、深沟槽隔离区或类似者，其用于使Rx区106与半导体结构100上各种其它主动区(图未示)分开。隔离区114典型为由非晶介电材料所组成，诸如可流动氧化物(FOX)或类似者。
鳍式场效应晶体管(FinFET)116布置于Rx区106的鳍片104内。FinFET 116包括一对S/D区110及布置于其之间的沟道118。栅极112布置于沟道118上方，并且可操作成用以控制穿过沟道118及介于S/D区110之间的电气连续性。栅极112包括布置于一对栅极间隔物122之间的栅极金属(或栅极金属堆叠)120。要注意的是，虚设栅极108具有如主动栅极112般确切的结构，差别在于虚设栅极未布置于主动沟道118上方并且部分延展到隔离区114内没有主动装置处。
栅极间隔物122是由介电材料所组成，诸如SiN、SiBCN或类似者。对于本特定例示性具体实施例，栅极间隔物122是SiBCN。
栅极金属120典型为栅极金属堆叠，其大体上包括三个主要结构群组(图未示)。那三个主要结构为：栅极介电层(典型为高k介电材料)、功函数金属结构(典型为TiN、TaN、TiCAl、其它金属氮化物或类似材料)及栅极电极金属(典型为Al、W、Cu或类似金属)。栅极介电层用于使功函数金属结构及栅极电极与衬底电气绝缘。功函数金属结构大体上是金属氮化物，其提供适当FinFET操作所需要的功函数，但电阻率典型比栅极电极大10到100倍。栅极电极是具有很低电阻率的金属。
布置于S/D区110上方且介于栅极112与虚设栅极108之间的是层间介电质(ILD)124，其典型为由诸如SiO2的氧化物所组成。ILD 124自鳍片104向上延展至鳍片104顶端上面的第一层阶(即高度)126。该第一层阶在程序流程的这个阶段，实质等于栅极112及ILD124的高度。
请参阅图2，栅极108、112接着向下凹陷至第二层阶或栅极层阶128。第二栅极层阶128是经完全处理的结构100中的鳍片104上面的栅极108、112的最后层阶(高度)。可使栅极间隔物122及栅极金属120在两个不同的各向异性蚀刻程序中凹陷，诸如反应性离子蚀刻(RIE)程序或类似者。
请参阅图3，在结构100上方布置衬垫层130。大体上，可透过诸如原子层沉积(ALD)程序或类似程序，在ILD 124及栅极108、112的曝露表面上方保形涂布衬垫层。该衬垫层大体上是一种高k介电质，具有第一材料组成，诸如二氧化铪(HfO2)、氮化物硅酸铪(HfSiON)或类似者。对于本特定例示性具体实施例，衬垫层是HfO2。衬垫层大体上非常薄，而且典型为在3nm至6nm厚的范围内。
由于衬垫层如此的薄，所以接着在衬垫层130上方布置保护层131以在后续蚀刻程序期间保护衬垫层。保护层可以是氮化物，诸如氮化硅(SiN)或类似者。保护层可透过诸如ALD或类似程序来涂敷。对于本特定例示性具体实施例，衬垫层是SiN。
请参阅图4，接着举例如通过RIE或类似者来各向异性蚀刻高k介电性衬垫层130及相关联的保护层131。该各向异性蚀刻程序使栅极金属120在栅极108、112的顶端处曝露。保护层131防止衬垫层130在此程序期间遭受破坏或腐蚀。衬垫层130的其余部分形成用于覆盖体132的外衬垫134(看图5最清楚)，其将完全在后续步骤中形成。
请参阅图5，接着通过诸如化学气相沉积(CVD)、物理气相沉积(PVD)、ALD或类似手段在衬垫层130上方布置核心层。该核心层大体上亦为一种介电质，具有与衬垫层130的第一材料组成不同的第二材料组成。核心层典型为由氮化物所组成，诸如SiN、SiBCN或类似者。
对于本特定例示性具体实施例，核心层是SiN，其是与保护层131相同的材料。如此，在这项具体实施例中，沉积核心层之前，不需要先移除保护层。
接着，将核心层与衬垫层130向下平坦化(诸如通过化学机械平坦化(CMP)来达成)，以使ILD 124的顶端表面曝露，并且完成在栅极108、112上方形成覆盖体132。覆盖体132包括围绕内核136布置的高k介电性外衬垫134。如前述，外衬垫134是自衬垫层130经平坦化之后留下的部分所形成。内核136是自核心层经平坦化之后留下的部分所形成。
请参阅图6，TS沟槽(图未示)是通过众所周知的程序，诸如通过各向异性干蚀刻程序，将ILD层124从结构100的Rx区106中的栅极108、112之间移除所形成。举例而言，可利用TS掩模通过习知的光刻程序，接着进行电浆干蚀刻，来图型化TS沟槽。电浆蚀刻本质上属于自对准，其中此蚀刻程序仅移除氧化物ILD层124，并且对氮化物栅极盖体132及间隔物122具有选择性。接着，在TS沟槽内形成TS层138。
TS层138取代ILD层124布置于栅极108、112的相对侧上及S/D区110上方。TS层138可通过TS金属化程序来布置。TS金属化程序可包括在S/D区110上方形成底端硅化物层，接着沉积顶端传导金属层。底端硅化物层可由Ni、Ti、NiPt硅化物或类似者所组成。传导金属层可由TiN、TaN及诸如W、Co或Ru的主体传导材料所组成。
将TS层138的任何过量填充向下平坦化至第一层阶126，其现为鳍片104的顶端表面上面的覆盖体132的顶端的层阶(或高度)(核心136及/或高k衬垫134)。TS层138跨布整个Rx区106纵向延展，以便确保即使是在最坏情况的错准条件下，仍与鳍片104的阵列中的S/D区110有适当电接触。
请参阅图7，接着使TS层138凹陷至高于栅极108、112的层阶128且低于核心136的层阶126的第三层阶140。此凹陷可通过TS层138的定时各向异性蚀刻来达成，诸如通过反应性离子蚀刻(RIE)或类似者来达成。
要注意的重点是，相较于在Rx区中形成CB接触部的先前技术方法，TS层138的此种凹陷属于浅式。在那些先前技术方法中，TS层妥适地凹陷至低于栅极108、112的层阶128。在本具体实施例中，TS层138的凹陷范围典型为15nm至30nm，其典型为原始TS层高度的约百分之25至50。然而，在Rx区中形成CB接触部的先前技术方法是使TS层凹陷到尽可能合理的程度，不会过度增加TS层的整体电阻。因此，先前技术方法使TS层妥适凹陷至低于TS层原始高度的百分之50，且低于栅极108、112的层阶128。
请参阅图8，氧化物填充层(或氧化物层)142布置于结构100上方。氧化物填充层142将用于后续图型化CB沟槽(看图12A最清楚)及CA沟槽(看图9C最清楚)。
请参阅图9A、9B及9C，在氧化物填充层142内图型化一对CA沟槽144(看图9C最清楚)，用以在其底下曝露TS层138。在此程序流程的后面，可金属化CA沟槽以形成电连接至TS层138的一对CA接触部160(看图13B最清楚)。CA沟槽144可如通过RIE程序或类似者来各向异性蚀刻。截面图9B展示同样将对尚待形成CB沟槽146进行图型化并金属化以形成CB接触部162处的位置(看图13A最清楚)。
为求清楚，图9A的俯视平面图展示结构100下铺于氧化物层142的特征，其中氧化物层142是以假想线边界来表示。另外，俯视平面图9A中展示CB沟槽146的虚线周界，而且其表示将在后续程序步骤中布置于氧化物填充层142内的CB沟槽146的目标位置。
要注意的重点是，CA沟槽144与CB沟槽146必须顺着平行于栅极112的方向相隔充分距离148而置，用以实质防止CB接触部162与CA接触部160之间出现电气短路(看图13B最清楚)。距离148必须顾及因无法避免的制造变异所致的最坏情况错准允差，并且仍然能够防止出现此短路。距离148典型为在15nm至30nm或更大的范围内，端视Rx区的整体宽度而定。
请参阅图10A及10B，接着在结构100上方布置有机平坦化层(OPL)150。接着通过诸如RIE蚀刻或类似程序，将CB沟槽146图型化并蚀刻到OPL层150内。虽然本具体实施例的程序流程展示CA沟槽之后才形成CB沟槽146，但本领域技术人员仍将认知的是，该程序流程中可先形成CB沟槽。
请参阅图11A及11B，在氧化物层142内进一步图型化并蚀刻CB沟槽146，以在CB沟槽146的中间部分152处使覆盖体132的顶端表面曝露。此蚀刻程序再次地，可以是RIE程序。
中间部分152的目标是要着落于该覆盖体的内核136直接位在栅极金属120上面的至少一部分上。如后续步骤中将更详细论述者，这是因为将会自中间部分152起，进一步将CB沟槽146向下蚀刻至沟槽底端156(看图12A最清楚)以使栅极金属120曝露。
然而，由于光刻及其它制造允差的关系，CB沟槽146的中间部分152可着落于覆盖体132的其它部分上，包括核心136未直接安放于栅极金属120或栅极高k介电性衬垫134上方的部分。在最坏情况的制造允差下，中间部分152甚至可部分延展到氧化物填充层142内约覆盖体132的层阶126处，如这项特定具体实施例中所示。此外，使中间部分152在覆盖体132的顶端表面上着落，甚至可将顶端表面向下蚀刻到稍微低于覆盖体层阶126约二至五nm处。
要注意的是，覆盖体132向上延展至覆盖体层阶126，此为高于TS层138的层阶140的距离154，亦实质为中间部分152高于TS层138的距离。此距离154预定为中间部分152离任何TS层138的充分垂直距离，用以实质防止该中间部分上所布置的任何金属与Rx区106内的任何TS层之间出现电气短路。
距离154必须顾及因无法避免的制造变异所致的最坏情况错准及其它允差，并且仍然能够防止出现此短路。距离154典型为在10nm至30nm的范围内。
请参阅图12A及12B，接着在本具体实施例中，相对于衬垫134选择性各向异性蚀刻核心136，以使CB沟槽146进一步延展至沟槽底端156，并且使栅极金属120曝露。该各向异性蚀刻可通过RIE程序或类似者来完成。
高k介电性衬垫134的第一材料组成、核心136的第二材料组成与氧化物填充层142的第三材料组成之间的差异使第一核心材料在各向异性蚀刻程序(诸如RIE)中相对于衬垫及氧化物填充层的第二及第三材料非常具有选择性。因此，可将核心136向下蚀刻以使栅极金属120曝露而不会蚀刻高k介电性衬垫134或氧化物填充层142。
这很重要，因为在此实施例中，要防止布置于CB沟槽146的任何CB接触部162(看图13A最清楚)与TS层138之间出现短路，需要高k介电性衬垫134。即使衬垫134典型只有3nm至6nm厚，但其高k材料组成仍提供足以防止CB接触部162与TS层138之间出现短路的电气绝缘。另外，未遭受蚀刻的衬垫134作用在于使CB接触部162与栅极金属120自对准。
请参阅图13A及13B，OPL层150举例如通过湿蚀刻程序或类似者来剥除。接着，举例如通过CVD、PVD、无电式金属镀覆或类似者将CA沟槽144及CB沟槽146金属化，以形成位在CA沟槽144中的CA接触部160、及位在CB沟槽146中的CB接触部162。CB接触部162电连接至栅极金属120，而CA接触部160电连接至TS层138。
在本程序流程的最后阶段，完成的半导体结构100此时包括布置于Rx区106中的FinFET 116。FinFET 116包括布置于一对源极/漏极(S/D)区110之间的沟道118、及布置于沟道118上方的栅极112。栅极112包括布置于栅极间隔物122之间的栅极金属120。覆盖体132布置于栅极112上方。该覆盖体包括围绕覆盖体核心136布置的高k介电性外衬垫134。在S/D区110上方栅极112的相对侧上布置沟槽硅化物(TS)层138。TS层138具有高于栅极112的层阶128且低于覆盖体132的层阶126的层阶140。在结构100上方布置氧化物层142。氧化物层142内及Rx区106上方布置CB沟槽146。CB沟槽146向下延展至实质位于覆盖体132的层阶126处的沟槽中间部分152，并且自中间部分152进一步延展至沟槽底端156。该沟槽底端包括栅极金属120。CB接触部162布置于CB沟槽146内并且电连接至该栅极金属120。
另外，半导体结构100此时包括用于FinFET 116的该对源极/漏极(CA)接触部160，其亦布置于氧化物层142内。该CA接触部电连接至TS层138，其套叠FinFET 116的S/D区110。CA接触部160顺着平行于栅极112的方向位于离CB接触部162充分距离148处(看图9A最清楚)，用以实质防止CB接触部162与CA接触部160之间出现电气短路。
此外，半导体结构100的Rx区106更包括垂直于栅极112延展的多个鳍片104(看图1A最清楚)。多个FinFET 116布置于鳍片104中。各FinFET 116包括布置于一对S/D区110之间的沟道118，其中栅极112布置于各FinFET 116的沟道118上方，而TS层138布置于各FinFET116的S/D区110上方的栅极112的相对侧上。
有助益的是，CA接触部160与CB接触部162都布置于结构100的Rx区106内，并且离任何TS层138充分距离且彼此相离，用以实质防止出现电气短路。CA接触部160与CB接触部162的形式及间隔顾及因无法避免的制造变异所致的最坏情况错准及其它允差，用以防止出现此短路。因此，结构100可轻易制造，并且可比例缩小至10nm技术节点及更先进的技术节点。
虽然已参照特定具体实施例说明本发明，应了解的是，仍可在所述发明概念的精神与范畴内施作许多变更。因此，本发明的用意不在于限制所述具体实施例，而是要具有以下权利要求书内容所界定的完全范畴。

Claims (20)

1.一种制造半导体装置的方法，该方法包含：
提供在主动区中布置有FinFET的结构，该FinFET包括布置于一对源极/漏极区之间的沟道、及布置于该沟道上方的栅极，该栅极包括布置于栅极间隔物之间的栅极金属；
在该栅极上方形成覆盖体，该覆盖体具有围绕内核布置的高k介电性外衬垫；
在该源极/漏极区上方的该栅极的相对侧上形成沟槽硅化物层；
使该沟槽硅化物层凹陷至高于该栅极的层阶且低于该覆盖体的层阶的层阶；
在该结构上方布置氧化物层；
在该氧化物层内图型化栅极沟槽，以使该内核与高k介电性外衬垫在该栅极沟槽的中间部分处曝露，该栅极沟槽位于该主动区内；
相对于该高k介电性外衬垫选择性蚀刻该内核，以使该栅极沟槽进一步延展至沟槽底端，并且使该栅极金属曝露；以及
金属化该栅极沟槽以形成电连接至该栅极金属的栅极接触部。
2.根据权利要求1所述的方法，其中，该高k介电性外衬垫具有高k介电性的第一材料组成，并且该内核具有与该第一材料组成不同的第二材料组成。
3.根据权利要求2所述的方法，其中，该第一材料是HfO2。
4.根据权利要求2所述的方法，其中，该第二材料是SiN、SiBCN及SiCO的其中一者。
5.根据权利要求1所述的方法，其中，该栅极沟槽的该中间部分位于离任何沟槽硅化物层充分距离处，用以实质防止该主动区内该栅极接触部与该沟槽硅化物层之间出现电气短路。
6.根据权利要求1所述的方法，包含使该沟槽硅化物层凹陷至该内核的该层阶的25％至50％的范围内的层阶。
7.根据权利要求1所述的方法，包含使该沟槽硅化物层凹陷至该内核的该层阶下面15nm至30nm的范围内。
8.根据权利要求1所述的方法，包含在氧化物层内就该FinFET布置一对源极/漏极接触部，该源极/漏极接触部电连接至将该FinFET的该源极/漏极区套叠的该沟槽硅化物层，该源极/漏极接触部顺着平行于该栅极的方向位于离该栅极接触部充分距离处，用以实质防止该栅极接触部与该源极/漏极接触部之间出现电气短路。
9.根据权利要求8所述的方法，包含：
在该氧化物层内图型化一对源极/漏极沟槽，以使该沟槽硅化物层在该FinFET的该源极/漏极区上方曝露；以及
金属化该源极/漏极沟槽，以形成电连接至该沟槽硅化物层的该源极/漏极接触部。
10.根据权利要求1所述的方法，包含：
形成该覆盖体前先在该栅极之间布置介电层；
使该介电层的层阶下面的该栅极凹陷至该栅极层阶；
在该结构上方布置衬垫层，该衬垫层具有高k介电性的第一材料组成；
在该衬垫层上方布置核心层，该核心层具有与该第一材料组成不同的第二材料组成；
将该核心层与衬垫层向下研磨至该介电层的该层阶，以形成该覆盖体的该高k介电性外衬垫与该内核；
移除该介电层，以形成沟槽硅化物沟槽；以及
在该沟槽硅化物沟槽内形成该沟槽硅化物层。
11.一种半导体结构，包含：
FinFET，布置于主动区中，该FinFET包括布置于一对源极/漏极区之间的沟道、及布置于该沟道上方的栅极，该栅极包括布置于栅极间隔物之间的栅极金属；
覆盖体，包括围绕内核布置的高k介电性外衬垫，该覆盖体布置于该栅极上方，该高k介电性外衬垫与内核自该栅极向上延展至实质相同第一覆盖体层阶；
布置于该源极/漏极区上方该栅极的对置侧上的沟槽硅化物层，该沟槽硅化物层具有高于该栅极的层阶且低于该覆盖体层阶的层阶；
布置于该结构上方的氧化物层；
布置于该氧化物层内及该主动区上方的栅极沟槽，该栅极沟槽向下延展至实质位于该覆盖体层阶处的沟槽中间部分，并且自该中间部分进一步延展至沟槽底端，该沟槽底端包括该栅极金属；以及
布置于该栅极沟槽内并且电连接至该栅极金属的栅极接触部。
12.根据权利要求11所述的半导体结构，其中，该高k介电性外衬垫具有高k介电性的第一材料组成，并且该内核具有与该第一材料组成不同的第二材料组成。
13.根据权利要求12所述的半导体结构，其中，该第一材料是HfO2。
14.根据权利要求12所述的半导体结构，其中，该第二材料是SiN、SiBCN及SiCO的其中一者。
15.根据权利要求11所述的半导体结构，其中，该栅极沟槽的该中间部分位于离任何沟槽硅化物层充分距离处，用以实质防止该主动区内该栅极接触部与该沟槽硅化物层之间出现电气短路。
16.根据权利要求11所述的半导体结构，包含该沟槽硅化物层，所具层阶在该覆盖体层阶的25％至50％的范围内。
17.根据权利要求11所述的半导体结构，包含该沟槽硅化物层，所具层阶在该覆盖体层阶下面15nm至30nm的范围内。
18.根据权利要求11所述的半导体结构，包含供该FinFET布置于氧化物层内的一对源极/漏极接触部，该源极/漏极接触部电连接至将该FinFET的该源极/漏极区套叠的该沟槽硅化物层，该源极/漏极接触部顺着平行于该栅极的方向位于离该栅极接触部充分距离处，用以实质防止该栅极接触部与该源极/漏极接触部之间出现电气短路。
19.根据权利要求11所述的半导体结构，其中，该栅极沟槽自该栅极沟槽的该中间部分向下延展至该沟槽底端的区段具有面积与该内核的横向截面实质相等的截面。
20.根据权利要求11所述的半导体结构，更包含：
该主动区，包括垂直于该栅极而延展的多个鳍片；
多个FinFET，布置于该鳍片中，各FinFET包括布置于一对源极/漏极区之间的沟道，其中，该栅极布置于各FinFET的该沟道上方；以及
该沟槽硅化物层，布置于各FinFET的该源极/漏极区上方的该栅极的相对侧上。
CN201710545803.9A 2016-07-06 2017-07-06 用于放置在具有高k介电栅极的半导体主动区内的栅极接触的方法及设备 Active CN107591334B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/202,817 US9824921B1 (en) 2016-07-06 2016-07-06 Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate caps
US15/202,817 2016-07-06

Publications (2)

Publication Number Publication Date
CN107591334A CN107591334A (zh) 2018-01-16
CN107591334B true CN107591334B (zh) 2020-11-24

Family

ID=60303313

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710545803.9A Active CN107591334B (zh) 2016-07-06 2017-07-06 用于放置在具有高k介电栅极的半导体主动区内的栅极接触的方法及设备

Country Status (3)

Country Link
US (2) US9824921B1 (zh)
CN (1) CN107591334B (zh)
TW (1) TWI649836B (zh)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9941278B2 (en) 2016-07-06 2018-04-10 Globalfoundries Inc. Method and apparatus for placing a gate contact inside an active region of a semiconductor
US9824921B1 (en) 2016-07-06 2017-11-21 Globalfoundries Inc. Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate caps
US9929048B1 (en) * 2016-12-22 2018-03-27 Globalfoundries Inc. Middle of the line (MOL) contacts with two-dimensional self-alignment
US10056473B1 (en) 2017-04-07 2018-08-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10269636B2 (en) * 2017-05-26 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of fabricating the same
US10497612B2 (en) 2017-12-11 2019-12-03 Globalfoundries Inc. Methods of forming contact structures on integrated circuit products
US10510613B2 (en) 2018-01-23 2019-12-17 Globalfoundries Inc. Contact structures
US10475702B2 (en) * 2018-03-14 2019-11-12 Taiwan Semiconductor Manufacturing Co., Ltd. Conductive feature formation and structure using bottom-up filling deposition
US10573724B2 (en) * 2018-04-10 2020-02-25 International Business Machines Corporation Contact over active gate employing a stacked spacer
US10347541B1 (en) * 2018-04-25 2019-07-09 Globalfoundries Inc. Active gate contacts and method of fabrication thereof
US11139385B2 (en) * 2018-05-17 2021-10-05 International Business Machines Corporation Interface-less contacts to source/drain regions and gate electrode over active portion of device
US10665505B2 (en) 2018-05-22 2020-05-26 International Business Machines Corporation Self-aligned gate contact isolation
US10685872B2 (en) 2018-05-30 2020-06-16 International Business Machines Corporation Electrically isolated contacts in an active region of a semiconductor device
CN110571186B (zh) * 2018-06-05 2021-10-01 中芯国际集成电路制造(上海)有限公司 金属纳米线的制造方法与半导体器件及其制造方法
KR102529229B1 (ko) 2018-06-07 2023-05-04 삼성전자주식회사 반도체 소자
US10770388B2 (en) 2018-06-15 2020-09-08 International Business Machines Corporation Transistor with recessed cross couple for gate contact over active region integration
US10431495B1 (en) 2018-07-23 2019-10-01 International Business Machines Corporation Semiconductor device with local connection
US10438850B1 (en) 2018-07-23 2019-10-08 International Business Machines Corporation Semiconductor device with local connection
KR102516878B1 (ko) 2018-07-26 2023-03-31 삼성전자주식회사 집적회로 소자
US10529826B1 (en) 2018-08-13 2020-01-07 Globalfoundries Inc. Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devices
US10832963B2 (en) 2018-08-27 2020-11-10 International Business Machines Corporation Forming gate contact over active free of metal recess
KR102609372B1 (ko) 2018-08-31 2023-12-06 삼성전자주식회사 반도체 소자
US11139203B2 (en) * 2018-10-22 2021-10-05 Taiwan Semiconductor Manufacturing Co., Ltd. Using mask layers to facilitate the formation of self-aligned contacts and vias
US10832943B2 (en) 2019-04-02 2020-11-10 International Business Machines Corporation Gate contact over active region with self-aligned source/drain contact
US11205723B2 (en) 2019-06-27 2021-12-21 International Business Machines Corporation Selective source/drain recess for improved performance, isolation, and scaling
KR20220158340A (ko) * 2021-05-24 2022-12-01 삼성전자주식회사 게이트 구조체를 갖는 반도체 소자들 및 그 형성 방법
US20230163194A1 (en) 2021-11-22 2023-05-25 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy Hybrid Film for Self-Alignment Contact Formation

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1830090A (zh) * 2003-08-13 2006-09-06 国际商业机器公司 利用自对准后栅极控制前栅极绝缘体上硅mosfet的器件阈值
CN101711426A (zh) * 2007-03-14 2010-05-19 Nxp股份有限公司 具有两个独立栅极的鳍片场效应管以及制造它的方法
CN103378135A (zh) * 2012-04-13 2013-10-30 台湾积体电路制造股份有限公司 用于FinFET的装置
CN104517859A (zh) * 2013-10-02 2015-04-15 格罗方德半导体公司 利用替代栅极技术形成鳍式场效晶体管的方法和器件
CN105590865A (zh) * 2014-11-07 2016-05-18 格罗方德半导体公司 在finfet器件上形成替代栅极结构的方法及其得到的器件

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140097464A (ko) * 2011-12-20 2014-08-06 인텔 코오퍼레이션 ｎ-형 및 ｐ-형 ＭＯＳ 소스-드레인 콘택들을 위한 III-V 층들
US9287138B2 (en) * 2012-09-27 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET low resistivity contact formation method
US9000513B2 (en) * 2012-11-12 2015-04-07 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing a semiconductor device and semiconductor device with surrounding gate transistor
US9431296B2 (en) * 2014-06-26 2016-08-30 International Business Machines Corporation Structure and method to form liner silicide with improved contact resistance and reliablity
TWI620234B (zh) * 2014-07-08 2018-04-01 聯華電子股份有限公司 一種製作半導體元件的方法
KR102276642B1 (ko) 2014-07-28 2021-07-15 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US9362285B2 (en) * 2014-10-02 2016-06-07 International Business Machines Corporation Structure and method to increase contact area in unmerged EPI integration for CMOS FinFETs
US9502286B2 (en) * 2014-12-05 2016-11-22 Globalfoundries Inc. Methods of forming self-aligned contact structures on semiconductor devices and the resulting devices
US9577096B2 (en) * 2015-05-19 2017-02-21 International Business Machines Corporation Salicide formation on replacement metal gate finFet devices
US9780178B2 (en) * 2015-06-05 2017-10-03 Globalfoundries Inc. Methods of forming a gate contact above an active region of a semiconductor device
US9722043B2 (en) * 2015-06-15 2017-08-01 International Business Machines Corporation Self-aligned trench silicide process for preventing gate contact to silicide shorts
US9653356B2 (en) 2015-08-10 2017-05-16 Globalfoundries Inc. Methods of forming self-aligned device level contact structures
US9905671B2 (en) 2015-08-19 2018-02-27 International Business Machines Corporation Forming a gate contact in the active area
US9853151B2 (en) 2015-09-17 2017-12-26 International Business Machines Corporation Fully silicided linerless middle-of-line (MOL) contact
US9735242B2 (en) * 2015-10-20 2017-08-15 Globalfoundries Inc. Semiconductor device with a gate contact positioned above the active region
US9853110B2 (en) 2015-10-30 2017-12-26 Globalfoundries Inc. Method of forming a gate contact structure for a semiconductor device
US9496225B1 (en) * 2016-02-08 2016-11-15 International Business Machines Corporation Recessed metal liner contact with copper fill
US9761483B1 (en) 2016-03-07 2017-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices, FinFET devices and methods of forming the same
US9941278B2 (en) 2016-07-06 2018-04-10 Globalfoundries Inc. Method and apparatus for placing a gate contact inside an active region of a semiconductor
US9824921B1 (en) 2016-07-06 2017-11-21 Globalfoundries Inc. Method and apparatus for placing a gate contact inside a semiconductor active region having high-k dielectric gate caps

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1830090A (zh) * 2003-08-13 2006-09-06 国际商业机器公司 利用自对准后栅极控制前栅极绝缘体上硅mosfet的器件阈值
CN101711426A (zh) * 2007-03-14 2010-05-19 Nxp股份有限公司 具有两个独立栅极的鳍片场效应管以及制造它的方法
CN103378135A (zh) * 2012-04-13 2013-10-30 台湾积体电路制造股份有限公司 用于FinFET的装置
CN104517859A (zh) * 2013-10-02 2015-04-15 格罗方德半导体公司 利用替代栅极技术形成鳍式场效晶体管的方法和器件
CN105590865A (zh) * 2014-11-07 2016-05-18 格罗方德半导体公司 在finfet器件上形成替代栅极结构的方法及其得到的器件

Also Published As

Publication number Publication date
US10014215B2 (en) 2018-07-03
CN107591334A (zh) 2018-01-16
US20180012798A1 (en) 2018-01-11
TWI649836B (zh) 2019-02-01
TW201812996A (zh) 2018-04-01
US9824921B1 (en) 2017-11-21

Similar Documents

Publication Publication Date Title
CN107591334B (zh) 用于放置在具有高k介电栅极的半导体主动区内的栅极接触的方法及设备
CN107591333B (zh) 用于在半导体的主动区内放置栅极接触的方法及设备
CN109273428B (zh) 集成电路的预金属化电介质或层间电介质层中的接触结构
TWI523237B (zh) 具有源極－汲極側壁間隔物並降低高度的鰭式場效電晶體
US9331178B2 (en) Method for manufacturing non-planar field effect transistor having a semiconductor fin
US8753964B2 (en) FinFET structure having fully silicided fin
US11776857B2 (en) Semiconductor device
US10050114B2 (en) Semiconductor device and method of manufacturing the same
CN111863711B (zh) 半导体结构及其形成方法
US9711505B2 (en) Semiconductor devices having dummy gate structure for controlling channel stress
TW202008445A (zh) 半導體裝置的形成方法
TW202040824A (zh) 半導體裝置
US9741615B1 (en) Contacts for a fin-type field-effect transistor
US10916470B2 (en) Modified dielectric fill between the contacts of field-effect transistors
CN109300897B (zh) 半导体装置及其制造方法
US10008385B1 (en) Enlarged sacrificial gate caps for forming self-aligned contacts
US11621332B2 (en) Wraparound contact to a buried power rail
CN115995426A (zh) 用于形成互连结构的方法
CN109390287B (zh) 半导体元件结构及其制造方法
US20230197830A1 (en) Method for Forming a Stacked FET Device
US20240154006A1 (en) Method for forming a semiconductor device
EP4199058A1 (en) A method for forming a stacked fet device
CN114068396B (zh) 半导体结构及其形成方法
KR20240133617A (ko) 후면 게이트 컨택트, 후면 게이트 에칭 정지층, 및 이를 형성하는 방법
CN115249704A (zh) 半导体结构及其形成方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20210305

Address after: California, USA

Patentee after: Lattice chip (USA) integrated circuit technology Co.,Ltd.

Address before: Greater Cayman Islands, British Cayman Islands

Patentee before: GLOBALFOUNDRIES Inc.

TR01 Transfer of patent right