CN107565976A - New latch for parallel-serial conversion - Google Patents
New latch for parallel-serial conversion Download PDFInfo
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- CN107565976A CN107565976A CN201710685655.0A CN201710685655A CN107565976A CN 107565976 A CN107565976 A CN 107565976A CN 201710685655 A CN201710685655 A CN 201710685655A CN 107565976 A CN107565976 A CN 107565976A
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Abstract
The present invention relates to integrated circuit fields, to propose a kind of new circuit structure, it is possible to achieve the function of multiplexing and data storage, in the case where completing same parallel data and being converted into serial data, cost of the circuit on area can be reduced.The technical solution adopted by the present invention is that, for the new latch of parallel-serial conversion, by two resistance R1, R2, six PMOSs M1, M2, M3, M4, M5 and M6, three NMOS tubes M7, M8, M9 and a current source I composition, annexation are as follows：The speed of current source goes out ground connection, and input meets node A；NMOS tube M7 grid meets P0, and source electrode connects node A drain electrodes and connects node B, Substrate ground；NMOS tube M8 grid meets P1, and source electrode meets node A, and drain electrode connects node D, Substrate ground；NMOS tube M9 grid meets clock CLK.Present invention is mainly applied to IC design occasions that manufacture.
Description
Technical field
The present invention relates to the serial port circuit design of integrated circuit fields, more particularly to parallel-serial conversion.Concretely relate to be used for
The new latch of parallel-serial conversion.
Background technology
One traditional trigger only has the function of data storage, it is impossible to is done directly the multiplexing of data, can typically distinguish
The multiplexing of data is completed with the multiplexer of current mode logic (CML), depositing for data is completed with current mode logic (CML) latch
Storage.So traditional parallel-to-serial converter structure uses a part of the trigger as sequence circuit, it will uses more door
To realize the multiplexing of data, it will circuit area is had larger consumption.In serial port circuit, parallel-serial conversion is by low speed
Parallel data is converted into the serial data of high speed.Multiplexer (MUX) is the pith of parallel-to-serial converter, but big
A large amount of traditional flip-flops (FF) are applied in most parallel-to-serial converters to realize the multiple function of multichannel and data storage function, institute
The trigger used with traditional parallel-to-serial converter adds the cost of circuit area.
The content of the invention
For overcome the deficiencies in the prior art, the present invention is directed to propose a kind of new circuit structure, it is possible to achieve multiplexing
With the function of data storage, in the case where completing same parallel data and being converted into serial data, circuit can be reduced in area
On cost.The technical solution adopted by the present invention is, for the new latch of parallel-serial conversion, by two resistance R1, R2, and six
PMOS M1, M2, M3, M4, M5 and M6, three NMOS tubes M7, M8, M9 and a current source I composition, annexation are as follows：Electricity
The speed in stream source goes out ground connection, and input meets node A；NMOS tube M7 grid meets P0, and source electrode connects node A drain electrodes and meets node B, and substrate connects
Ground；NMOS tube M8 grid meets P1, and source electrode meets node A, and drain electrode connects node D, Substrate ground；NMOS tube M9 grid connects clock
CLK, source electrode meet node A, and drain electrode connects node C, Substrate ground；PMOS M1 grid meets IN0, and source electrode meets node F, and drain electrode connects section
Point B, substrate connect power supply；PMOS M2 grid meets IN0, and source electrode connects node, and drain electrode meets node B, and substrate connects power supply；PMOS M3
Grid meet IN1, source electrode meets node F, and drain electrode connects node, and substrate connects power supply；PMOS M4 grid meets IN1, and source electrode connects node
E, drain electrode meet node D, and substrate connects power supply；PMOS M5 grid connects PMOS M6 source electrode, and source electrode meets node F, and drain electrode connects section
Point C, substrate connect power supply；M6 grid connects PMOS M5 source electrode, and source electrode meets node E, and drain electrode meets node C, and substrate connects power supply；Electricity
Resistance R1 end 1 connects power supply, and end 2 meets node F；Resistance R2 end 1 connects power supply, and end 2 meets node E；Node E and F are as output；Three
Control signal CLK, P0, P1 are used to maintaining and selecting input signal, and CLK frequency is the duty of P0 and P1 twice of clock signal
Than being 20% for 50%, P0 and P1 dutycycle, input signal IN0 and IN1 are selected for respectively.
No matter selection signal P0 and P1 level height, now circuit is for storing when clock CLK is low level
The logic level IN0 and IN1 of input；When clock CLK is high level, if selection signal P0 be if high level P1 is low level
Circuit output IN0 data, if selection signal P1 be data that IN1 is exported if high level P0 is low level.
The features of the present invention and beneficial effect are：
The circuit structure of the proposition of the present invention, can be used for high speed parallel-serial conversion.Used respectively compared to conventional circuit structure
Multiplexer and latch realize that multidiameter delay data are converted to serial data all the way, and the present invention realizes that parallel-serial conversion can be at one
Clock cycle realizes the multiplexing and storage of data, so as to greatly save the number of transistors needed for circuit realiration so that chip
The cost of area reduces.
Brief description of the drawings：
Fig. 1 present invention proposes the circuit structure for integrating multiplexer and latch.
Timing diagram when Fig. 2 circuit structures proposed by the present invention are run.
4 to 1 parallel-to-serial converter that the circuit structure that Fig. 3 is proposed is realized.
Embodiment
The present invention combine traditional current-mode multiplexer and latch its while propose a kind of achievable data storage
The circuit structure of data-reusing is completed, a kind of circuit structure proposed by the present invention is as shown in figure.It is proposed by the present invention to realize number
According to the circuit structure of multiplexing and storage by two resistance R1, R2, six PMOSs M1, M2, M3, M4, M5 and M6, three NMOS tubes
M7, M8, M9 and a current source I composition.The annexation of each component is as follows：The speed of current source goes out ground connection, and input connects node
A；NMOS tube M7 grid meets P0, and source electrode connects node A drain electrodes and connects node B, Substrate ground；NMOS tube M8 grid connects P1, source electrode
Node A is met, drain electrode connects node D, Substrate ground；NMOS tube M9 grid meets CLK, and source electrode meets node A, and drain electrode connects node C, substrate
Ground connection；PMOS M1 grid meets IN0, and source electrode meets node F, and drain electrode meets node B, and substrate connects power supply；PMOS M2 grid connects
IN0, source electrode connect node, and drain electrode meets node B, and substrate connects power supply；PMOS M3 grid meets IN1, and source electrode meets node F, and drain electrode connects
Node, substrate connect power supply；PMOS M4 grid meets IN1, and source electrode meets node E, and drain electrode meets node D, and substrate connects power supply；PMOS
M5 grid connects PMOS M6 source electrode, and source electrode meets node F, and drain electrode meets node C, and substrate connects power supply；M6 grid connects PMOS
M5 source electrode, source electrode meet node E, and drain electrode meets node C, and substrate connects power supply；Resistance R1 end 1 connects power supply, and end 2 meets node F；Resistance
R2 end 1 connects power supply, and end 2 meets node E；Node E and F are as output.
The operation logic of circuit structure proposed by the present invention is as follows, is divided into transmission IN0, maintains IN0, transmit IN1, maintains
The steps of IN1 tetra-, the sequential that its function is realized is as shown in Figure 2.Three control signals CLK, P0, P1 are used to maintain and select input to believe
Number.CLK frequency is that the dutycycle that the dutycycle of P0 and P1 twice of clock signal is 50%, P0 and P1 is 20%, for dividing
Input signal IN0 and IN1 are not selected.
Specific function is embodied as：When clock CLK be it is low level when no matter selection signal P0 and P1 level height,
Now circuit is used for the logic level IN0 and IN1 for storing input；When clock CLK is high level, if selection signal P0 is height
Level P1 is low level then circuit output IN0 data, is to export IN1's if high level P0 is low level if selection signal P1
Data.To prevent that circuit from being simultaneously high level when the state of selection for selection signal.The state of function is completed from circuit
As can be seen that function of half of the clock cycle of circuit structure proposed as multiplexer, half of clock cycle is data storage work(
Energy.In a word, the circuit structure of proposition can substitute multiplexer and complete the function of latching.
To become apparent from the object, technical solutions and advantages of the present invention, implementation of the present invention is provided below in conjunction with example.
Traditional 4 to 1 parallel-serial conversion structure needs three latch (L), three 2 to 1 and go here and there and turn (M) and three triggers (FF).
Such as figure three is all, realizes 4 to 1 same parallel-serial conversion using the circuit structure of the present invention, it is thus only necessary to three latch (L)
With the circuit structure (ML) for being three propositions.Circuit structure proposed by the present invention, which is can be seen that, from the quantity using door is realizing 4
To 1 parallel-serial conversion when, it is instead of traditional 2 to 1 with ML and go here and there shifting circuit (M) and trigger (FF), realize multichannel and answer
With the function of being latched with data.There it can be seen that can when completing identical data-reusing using structure proposed by the present invention
To reduce the use number of gate circuit, reduce so that the area of circuit is spent.
Claims (2)
1. a kind of new latch for parallel-serial conversion, it is characterized in that, by two resistance R1, R2, six PMOS M1, M2,
M3, M4, M5 and M6, three NMOS tubes M7, M8, M9 and a current source I composition, annexation are as follows：The speed of current source goes out to connect
Ground, input meet node A；NMOS tube M7 grid meets P0, and source electrode connects node A drain electrodes and connects node B, Substrate ground；NMOS tube M8's
Grid meets P1, and source electrode meets node A, and drain electrode connects node D, Substrate ground；NMOS tube M9 grid meets clock CLK, and source electrode connects node
A, drain electrode connect node C, Substrate ground；PMOS M1 grid meets IN0, and source electrode meets node F, and drain electrode meets node B, and substrate connects electricity
Source；PMOS M2 grid meets IN0, and source electrode connects node, and drain electrode meets node B, and substrate connects power supply；PMOS M3 grid meets IN1,
Source electrode meets node F, and drain electrode connects node, and substrate connects power supply；PMOS M4 grid meets IN1, and source electrode meets node E, and drain electrode connects node
D, substrate connect power supply；PMOS M5 grid connects PMOS M6 source electrode, and source electrode meets node F, and drain electrode meets node C, and substrate connects electricity
Source；M6 grid connects PMOS M5 source electrode, and source electrode meets node E, and drain electrode meets node C, and substrate connects power supply；Resistance R1 end 1 connects
Power supply, end 2 meet node F；Resistance R2 end 1 connects power supply, and end 2 meets node E；Node E and F are as output；Three control signals
CLK, P0, P1 are used to maintaining and selecting input signal, and CLK frequency is that the dutycycle of P0 and P1 twice of clock signal is
50%, P0 and P1 dutycycle are 20%, and input signal IN0 and IN1 are selected for respectively.
2. it is used for the new latch of parallel-serial conversion as claimed in claim 1, it is characterized in that, when clock CLK is low level
When no matter selection signal P0 and P1 level height, now circuit be used for store input logic level IN0 and IN1；At that time
When clock CLK is high level, if the data that selection signal P0 is circuit output IN0 if high level P1 is low level, if selection
Signal P1 is that high level P0 is the data that low level then exports IN1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710685655.0A CN107565976A (en) | 2017-08-11 | 2017-08-11 | New latch for parallel-serial conversion |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710685655.0A CN107565976A (en) | 2017-08-11 | 2017-08-11 | New latch for parallel-serial conversion |
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| CN107565976A true CN107565976A (en) | 2018-01-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201710685655.0A Pending CN107565976A (en) | 2017-08-11 | 2017-08-11 | New latch for parallel-serial conversion |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111900991A (en) * | 2020-08-11 | 2020-11-06 | 中国科学院微电子研究所 | Dynamic reset double-edge switch driving circuit and method suitable for ultra-high-speed DAC |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7006021B1 (en) * | 2003-06-27 | 2006-02-28 | Cypress Semiconductor Corp. | Low power serializer circuit and method |
| CN103490748A (en) * | 2013-06-21 | 2014-01-01 | 北京大学深圳研究生院 | Latch circuit unit and data driving circuit for display device |
| CN104682967A (en) * | 2015-01-30 | 2015-06-03 | 陈普锋 | GaAs logical unit based on differential structure and serial-parallel conversion circuit thereof |
| US20150312060A1 (en) * | 2014-04-23 | 2015-10-29 | Lsi Corporation | Decision feedback equalization slicer with enhanced latch sensitivity |
-
2017
- 2017-08-11 CN CN201710685655.0A patent/CN107565976A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7006021B1 (en) * | 2003-06-27 | 2006-02-28 | Cypress Semiconductor Corp. | Low power serializer circuit and method |
| CN103490748A (en) * | 2013-06-21 | 2014-01-01 | 北京大学深圳研究生院 | Latch circuit unit and data driving circuit for display device |
| US20150312060A1 (en) * | 2014-04-23 | 2015-10-29 | Lsi Corporation | Decision feedback equalization slicer with enhanced latch sensitivity |
| CN104682967A (en) * | 2015-01-30 | 2015-06-03 | 陈普锋 | GaAs logical unit based on differential structure and serial-parallel conversion circuit thereof |
Non-Patent Citations (1)
| Title |
|---|
| TSAI,W.等: "A novel low gate-count serializer topology with Multiplexer-Flip-Flops", 《2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111900991A (en) * | 2020-08-11 | 2020-11-06 | 中国科学院微电子研究所 | Dynamic reset double-edge switch driving circuit and method suitable for ultra-high-speed DAC |
| CN111900991B (en) * | 2020-08-11 | 2022-11-29 | 中国科学院微电子研究所 | Dynamic reset double-edge switch driving circuit and method suitable for ultra-high-speed DAC |
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