CN107565803B - Surge current suppression circuit and suppression method for super-capacity input energy storage capacitor - Google Patents
Surge current suppression circuit and suppression method for super-capacity input energy storage capacitor Download PDFInfo
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- CN107565803B CN107565803B CN201710855621.1A CN201710855621A CN107565803B CN 107565803 B CN107565803 B CN 107565803B CN 201710855621 A CN201710855621 A CN 201710855621A CN 107565803 B CN107565803 B CN 107565803B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 51
- 238000004146 energy storage Methods 0.000 title claims abstract description 48
- 230000001629 suppression Effects 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 9
- 230000002265 prevention Effects 0.000 claims abstract description 15
- 238000012986 modification Methods 0.000 description 2
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Abstract
The invention discloses a surge current suppression circuit and a suppression method for an ultra-large capacity input energy storage capacitor, wherein the surge current suppression circuit comprises a delay control unit, a temperature compensation unit, a reverse discharge prevention unit, a resistor network unit and a switch unit; the input ends of the delay control unit, the temperature compensation unit and the reverse discharge prevention unit are connected with the power supply of the system; the output end of the reverse discharge prevention unit is connected with the input end of the high-capacity energy storage capacitor Cbig; the output end of the high-capacity energy storage capacitor Cbig is connected with the input ends of the resistor network unit and the switch unit; the output ends of the resistor network unit and the switch unit are connected with a system power supply loop; and the third end of the delay control unit and the third end of the temperature compensation unit are respectively connected with the switch unit. The invention realizes the surge current suppression of the ultra-large capacity input energy storage capacitor with a simple circuit structure, improves the safety and adaptability of the circuit, and provides a guarantee for the safety of an aviation airborne power supply system.
Description
Technical Field
The invention relates to the field of switching power supplies and components thereof, in particular to a surge current suppression circuit and a suppression method for an ultra-large-capacity input energy storage capacitor.
Background
The switching power supply and the components thereof are widely applied to the airborne electronic systems of civil and military aviation. In aviation applications, it is common to meet the requirements of on-board power supply characteristics (high and low voltage surges), for example, at 30 picofarads. The input energy storage capacitor with super large capacity can cause great adverse effect on a front-stage power supply system without strict treatment, for example, surge current exceeding kiloamperes is generated, and the front-stage power supply is damaged when serious. The prior art generally adopts NTC thermistors for suppression, and the performance of the NTC thermistors is greatly changed along with different environmental temperatures.
Disclosure of Invention
In order to solve the defects in the prior art, the invention provides a surge current suppression circuit and a suppression method for an ultra-large-capacity input energy storage capacitor, which can control an input current waveform when a switching power supply is started in an aeronautical airborne application, so that the surge current of the switching power supply is greatly reduced and has a controllable rising characteristic.
In order to achieve the above purpose, the technical scheme of the invention is as follows: the surge current suppression circuit for the ultra-large capacity input energy storage capacitor comprises a delay control unit, a temperature compensation unit, an anti-reverse discharge unit, a resistor network unit and a switch unit; the input ends of the delay control unit, the temperature compensation unit and the reverse discharge prevention unit are connected with the power supply of the system; the output end of the reverse discharge prevention unit is connected with the input end of the high-capacity energy storage capacitor Cbig; the output end of the high-capacity energy storage capacitor Cbig is connected with the input ends of the resistor network unit and the switch unit; the output ends of the resistor network unit and the switch unit are connected with a system power supply loop; and the third end of the delay control unit and the third end of the temperature compensation unit are respectively connected with the switch unit.
Further, the resistor network unit includes a thermistor Rntc and a resistor Rnom connected in parallel.
Further, the switching unit comprises a MOS tube K2 and a compensation resistor Rcomp which are connected in series, and a MOS tube K1 which is connected in parallel with the MOS tube K2 and the compensation resistor Rcomp which are connected in series; and the third end of the delay control unit is connected with the MOS tube K1, and the third end of the temperature compensation unit is connected with the MOS tube K2.
The suppression method of the surge current suppression circuit of the ultra-large capacity input energy storage capacitor comprises the following steps:
1) When the power supply of the system is started, the delay control unit starts to delay time; the reverse discharge prevention unit is positively conducted; the pressure difference of the large-capacity energy storage capacitor Cbig is increased from 0V; the resistor network unit and the high-capacity energy storage capacitor Cbig are connected in series to divide voltage to limit the current increasing rate; the temperature compensation unit detects the ambient temperature and outputs a switch control signal such as 3) after comparing with a compensation temperature section, and the loop current is suppressed to a preset range, so that the voltage controllable curve of the high-capacity energy storage capacitor Cbig is increased;
2) When the power supply of the system is stable, the time delay control unit finishes timing when the voltage of the large-capacity energy storage capacitor Cbig rises to a certain amplitude; the third end of the delay control unit outputs a switch control signal, the MOS tube K1 is conducted in a low-resistance mode, the resistor network unit is short-circuited, the steady-state power consumption of a loop is reduced, and the surge current suppression is finished;
3) When the output of the temperature compensation unit turns on a switching signal, the MOS tube K2 is conducted with low resistance, the resistor network unit is connected with the compensation resistor Rcomp in parallel and then connected with the high-capacity energy storage capacitor Cbig in series; when no output switch-on signal is output, the MOS tube K2 is closed, and the resistor network unit is connected with the high-capacity energy storage capacitor Cbig in series.
The beneficial effects of the invention are as follows: the surge current suppression circuit of the super-capacity input energy storage capacitor is suitable for a switching power supply and components thereof for configuring the high-capacity input energy storage capacitor in aviation onboard application, and can effectively control the input current waveform of the switching power supply when the super-capacity input energy storage capacitor is started, so that the current peak value and the rise time of the surge current suppression circuit are controllable, and the surge current is small. Under the action of the surge current suppression circuit of the super-capacity input energy storage capacitor, the input surge current waveform can be controlled, the starting-up surge current peak value is greatly reduced, and the temperature consistency is good.
In some applications, the on-board power supply of the aviation can be used under extremely severe temperature conditions (for example, low temperature-55 ℃), and in this state, if the impedance value of the resistance network playing a role in suppressing surge current changes greatly along with the temperature, the circuit cannot be started at extremely low temperature, and the on-board power supply system can be damaged due to the fact that the impedance is too small at higher temperature. In this case, therefore, the temperature compensation unit circuit must be able to compensate well for the impedance-temperature characteristics of the resistor network constituted by Rntc and Rnom. In this embodiment, the temperature compensation unit circuit can compensate the resistance network unit to the initial impedance variation of not more than 20% in a wide temperature range from-55 ℃ to 100 ℃, so that the same level of surge current suppression performance can be ensured under extremely severe temperature conditions.
Through the technical scheme, the surge current suppression of the ultra-large-capacity input energy storage capacitor is realized by adopting a simple circuit structure, the safety and the adaptability of the circuit are improved, and the safety of an aviation airborne power supply system is ensured.
Drawings
Fig. 1 is a schematic block diagram of an inrush current suppression circuit for implementing a very large capacity input storage capacitor of the present invention.
The device comprises a 1-time delay control unit, a 2-temperature compensation unit, a 3-reverse discharge prevention unit, a 4-resistance network unit and a 5-switch unit.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
On the contrary, the invention is intended to cover any alternatives, modifications, equivalents, and variations as may be included within the spirit and scope of the invention as defined by the appended claims. Further, in the following detailed description of the present invention, certain specific details are set forth in order to provide a better understanding of the present invention. The present invention will be fully understood by those skilled in the art without the details described herein.
The surge current suppression circuit for the super-capacity input energy storage capacitor is used for controlling the startup surge current after the super-capacity input energy storage capacitor is applied to the input end in the airborne application.
Referring to fig. 1, the surge current suppression circuit of the ultra-large capacity input energy storage capacitor comprises a delay control unit 1, a temperature compensation unit 2, an anti-reverse discharge unit 3, a resistor network unit 4 and a switch unit 5; the input ends of the delay control unit 1, the temperature compensation unit 2 and the reverse discharge prevention unit 3 are connected with the power supply of the system; the output end of the reverse discharge prevention unit 3 is connected with the input end of the high-capacity energy storage capacitor Cbig; the output end of the high-capacity energy storage capacitor Cbig is connected with the input ends of the resistor network unit 4 and the switch unit 5; the output ends of the resistor network unit 4 and the switch unit 5 are connected with a system power supply loop; the third end of the delay control unit 1 and the third end of the temperature compensation unit 2 are respectively connected to the switch unit 5.
The resistor network unit 4 includes a thermistor Rntc and a resistor Rnom connected in parallel.
The switch unit 5 comprises a MOS tube K2 and a compensation resistor Rcomp which are connected in series, and a MOS tube K1 which is connected in parallel with the MOS tube K2 and the compensation resistor Rcomp which are connected in series; the third end of the delay control unit 1 is connected with the MOS tube K1, and the third end of the temperature compensation unit 2 is connected with the MOS tube K2.
A control method of a surge current suppression circuit of an ultra-large capacity input energy storage capacitor comprises the following steps:
1) When the power supply of the system is started, the delay control unit 1 starts delay time; the reverse discharge prevention unit 3 is conducted in the forward direction; the pressure difference of the large-capacity energy storage capacitor Cbig is increased from 0V; the resistor network unit 4 and the high-capacity energy storage capacitor Cbig are connected in series to divide voltage to limit the current increasing rate; the temperature compensation unit 2 detects the ambient temperature and outputs a switch control signal such as 3) after comparing with a compensation temperature section, and the loop current is suppressed to a preset range, so that the voltage controllable curve of the high-capacity energy storage capacitor Cbig is increased;
2) When the power supply of the system is stable, the time delay control unit 1 finishes timing when the voltage of the large-capacity energy storage capacitor Cbig rises to a certain amplitude; the third end of the delay control unit 1 outputs a switch control signal, the MOS tube K1 is conducted in a low-resistance mode, the resistor network unit 4 is short-circuited, the steady-state power consumption of a loop is reduced, and the surge current suppression is finished;
3) When the output of the temperature compensation unit 2 turns on a switching signal, the MOS tube K2 is turned on with low resistance, the resistor network unit 4 is connected with the compensation resistor Rcomp in parallel and then connected with the high-capacity energy storage capacitor Cbig in series; when no output switch-on signal is output, the MOS tube K2 is closed, and the resistor network unit 4 is connected in series with the high-capacity energy storage capacitor Cbig.
The principle of the invention is that when the power supply voltage of the applied system is started, the initial voltage of the super-capacity energy storage capacitor Cbig is 0V, and the reverse discharge prevention unit 3 is positively conducted in the first step; secondly, the delay control unit 1 starts delay time, the control signal output of the MOS tube K1 is low, and the MOS tube K1 is not conducted; the third step, the temperature compensation unit 2 detects the ambient temperature, if in the temperature compensation section, a switch control signal is output to the switch unit to conduct the MOS tube K2 with low resistance, the compensation resistor Rcomp is connected with the compensation resistor network unit 4 in parallel, and if in the temperature compensation section, the MOS tube K2 is controlled to be non-conducting; fourthly, the compensation resistance network unit 2 (not in the temperature compensation section) or the parallel network of the compensation resistance network unit 2 and the compensation resistance Rcomp (in the temperature compensation section) is connected in series with the super-capacity energy storage capacitor Cbig, so that the loop current is suppressed to a preset range, and the Cbig voltage is gradually increased according to a controllable curve; and fifthly, after Cbig rises to a certain amplitude, the delay control unit 1 delays time, the control signal output of the MOS tube K1 is high, the K1 is conducted, the resistor network unit 4 is short-circuited, so that the steady-state working power consumption is reduced, and the surge current suppression process is finished.
Through the technical scheme, the surge current suppression of the ultra-large-capacity input energy storage capacitor is realized by adopting a simple circuit structure, the safety and the adaptability of the circuit are improved, and the safety of an aviation airborne power supply system is ensured.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (3)
1. The surge current suppression circuit of the super-capacity input energy storage capacitor is characterized in that: the device comprises a delay control unit (1), a temperature compensation unit (2), a reverse discharge prevention unit (3), a resistor network unit (4) and a switch unit (5); the input ends of the delay control unit (1), the temperature compensation unit (2) and the reverse discharge prevention unit (3) are connected with the power supply of the system; the output end of the reverse discharge prevention unit (3) is connected with the input end of the high-capacity energy storage capacitor Cbig; the output end of the high-capacity energy storage capacitor Cbig is connected with the input ends of the resistor network unit (4) and the switch unit (5); the output ends of the resistor network unit (4) and the switch unit (5) are connected with a power supply loop of the system; the third end of the delay control unit (1) and the third end of the temperature compensation unit (2) are respectively connected with the switch unit (5);
The suppression method of the surge current suppression circuit comprises the following steps:
1) When the power supply of the system is started, the delay control unit (1) starts delay timing; the reverse discharge prevention unit (3) is conducted in the forward direction; the pressure difference of the large-capacity energy storage capacitor Cbig is increased from 0V; the resistor network unit (4) and the high-capacity energy storage capacitor Cbig are connected in series to divide voltage to limit the current increasing rate; the temperature compensation unit (2) outputs a switch control signal after detecting the ambient temperature and comparing with a compensation temperature section, as in step 3), and the loop current is restrained to a preset range, so that the voltage controllable curve of the large-capacity energy storage capacitor Cbig is increased;
2) When the power supply of the system is stable, the time delay control unit (1) finishes timing when the voltage of the large-capacity energy storage capacitor Cbig rises to a certain amplitude; the third end of the delay control unit (1) outputs a switch control signal, the MOS tube K1 is conducted in a low-resistance mode, the resistor network unit (4) is short-circuited, the steady-state power consumption of a loop is reduced, and the surge current suppression is finished;
3) When the output of the temperature compensation unit (2) turns on a switching signal, the MOS tube K2 is conducted with low resistance, the resistance network unit (4) is connected with the compensation resistor Rcomp in parallel and then connected with the high-capacity energy storage capacitor Cbig in series; when no output switch-on signal is output, the MOS tube K2 is closed, and the resistor network unit (4) is connected in series with the high-capacity energy storage capacitor Cbig.
2. The surge current suppression circuit of a super-capacity input storage capacitor of claim 1, wherein: the resistor network unit (4) comprises a thermistor Rntc and a resistor Rnom connected in parallel.
3. The surge current suppression circuit of a super-capacity input storage capacitor of claim 1, wherein: the switching unit (5) comprises a MOS tube K2 and a compensation resistor Rcomp which are connected in series front and back, and a MOS tube K1 which is connected with the MOS tube K2 and the compensation resistor Rcomp in parallel; the third end of the delay control unit (1) is connected with the MOS tube K1, and the third end of the temperature compensation unit (2) is connected with the MOS tube K2.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710855621.1A CN107565803B (en) | 2017-09-20 | 2017-09-20 | Surge current suppression circuit and suppression method for super-capacity input energy storage capacitor |
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| CN201710855621.1A CN107565803B (en) | 2017-09-20 | 2017-09-20 | Surge current suppression circuit and suppression method for super-capacity input energy storage capacitor |
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| CN107565803A CN107565803A (en) | 2018-01-09 |
| CN107565803B true CN107565803B (en) | 2024-06-18 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108363878A (en) * | 2018-02-27 | 2018-08-03 | 中国电子科技集团公司第五十八研究所 | Circuit safety verification method and computer readable storage medium |
| CN109755928A (en) * | 2019-02-19 | 2019-05-14 | 深圳市科比特航空科技有限公司 | Anti-Back EMF Circuits and Drones |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008104276A (en) * | 2006-10-18 | 2008-05-01 | Toshiba Schneider Inverter Corp | Inverter device |
| WO2011151906A1 (en) * | 2010-06-02 | 2011-12-08 | 三菱電機株式会社 | Inverter apparatus |
| CN106026626A (en) * | 2016-06-29 | 2016-10-12 | 浪潮集团有限公司 | Surge current suppressor based on RC time delay circuit |
| CN207234663U (en) * | 2017-09-20 | 2018-04-13 | 中国电子科技集团公司第四十三研究所 | A kind of surge current suppression circuit of vast capacity input storage capacitor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN205141646U (en) * | 2015-10-27 | 2016-04-06 | 深圳市冠旭电子有限公司 | Surge current suppressing circuit |
| JP6187884B2 (en) * | 2015-11-19 | 2017-08-30 | 株式会社安川電機 | Power converter |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008104276A (en) * | 2006-10-18 | 2008-05-01 | Toshiba Schneider Inverter Corp | Inverter device |
| WO2011151906A1 (en) * | 2010-06-02 | 2011-12-08 | 三菱電機株式会社 | Inverter apparatus |
| CN106026626A (en) * | 2016-06-29 | 2016-10-12 | 浪潮集团有限公司 | Surge current suppressor based on RC time delay circuit |
| CN207234663U (en) * | 2017-09-20 | 2018-04-13 | 中国电子科技集团公司第四十三研究所 | A kind of surge current suppression circuit of vast capacity input storage capacitor |
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