CN107546976B

CN107546976B - Charge pump circuit and charge pump

Info

Publication number: CN107546976B
Application number: CN201710911110.7A
Authority: CN
Inventors: 翁建城; 陈春平
Original assignee: Zhuhai Jieli Technology Co Ltd
Current assignee: Zhuhai Jieli Technology Co Ltd
Priority date: 2017-09-29
Filing date: 2017-09-29
Publication date: 2022-03-04
Anticipated expiration: 2037-09-29
Also published as: CN107546976A

Abstract

The invention relates to a charge pump circuit and a charge pump, which comprise a charge-discharge module, a charge starting module, a charge-discharge control module and a pump capacitor. By outputting a voltage at the first terminal of the pump capacitor, PAD at one output port is reduced. Meanwhile, the output link is free from transistor voltage drop, the influence of the transistor voltage drop on the output link on the efficiency is avoided, the size of a switch tube on the output link is facilitated, and the size of the charge pump circuit is reduced on the basis.

Description

Charge pump circuit and charge pump

Technical Field

The present invention relates to the field of integrated circuit technologies, and in particular, to a charge pump circuit and a charge pump.

Background

In recent years, various portable electronic products have been rapidly developed. As an important component of electronic products, the power supply needs to have specification requirements of high efficiency, small quiescent current, small volume, low cost, and the like. Therefore, the charge pump circuit becomes the preferred power source for electronic products.

The double-increment charge pump is a main implementation mode of power supply boosting in low-voltage application of electronic products. In a traditional charge pump circuit, on a discharge link connected with a voltage output end, a port connected with an external protection circuit needs to be manufactured into a PAD (PAD), and the area of a chip is increased. Meanwhile, because the switch tube on the discharge link has voltage drop, especially in the application of driving the output voltage to be larger or the output power to be higher, in order to reduce the voltage drop of the switch tube as much as possible and improve the efficiency, the area of the switch tube needs to be correspondingly increased, so that the size of the charge pump circuit is larger, and the cost is increased.

Disclosure of Invention

Accordingly, it is desirable to provide a charge pump circuit and a charge pump for the conventional double-charge pump circuit with a larger size.

The technical scheme provided by the invention is as follows:

a charge pump circuit comprises a charge-discharge module, a charge starting module, a charge-discharge control module and a pump capacitor.

The charge-discharge module is respectively connected with the charge starting module, the charge-discharge control module, the first end of the pump capacitor and the second end of the pump capacitor.

The charge-discharge module is used for accessing power voltage and a first clock signal.

The charging starting module is connected with the second end of the pump capacitor.

The charging starting module is used for accessing a first clock signal and grounding.

And the charge and discharge control module is respectively connected with the second ends of the pump capacitors.

The charge and discharge control module is used for accessing a second clock signal and power voltage and is used for grounding.

The first end of the pump capacitor is used for outputting voltage.

A charge pump comprises the charge pump circuit.

According to the charge pump circuit and the charge pump provided by the invention, the PAD of one output port is reduced by outputting the voltage at the first end of the pump capacitor. Meanwhile, the output link is not provided with transistor voltage drop, so that the influence of the transistor voltage drop on the output link on the efficiency is avoided, the size of a switching tube on the discharge link is reduced conveniently, and the size of the charge pump circuit is reduced on the basis.

Drawings

FIG. 1 is a functional block diagram of a charge pump circuit;

FIG. 2 shows CLK₁And CLK₂Timing diagrams of non-overlapping clock driving signals;

fig. 3 is a schematic circuit diagram of a charge pump circuit.

Detailed Description

For better understanding of the objects, technical solutions and effects of the present invention, the present invention will be further explained with reference to the accompanying drawings and examples. Meanwhile, the following described examples are only for explaining the present invention, and are not intended to limit the present invention.

Based on this, in one implementationIn an example, as shown in fig. 1, the functional block diagram of the charge pump circuit includes a charge/discharge module 10, a charge start module 11, a charge/discharge control module 12, and a pump capacitor C_PUMP。

The charge-discharge module 10 is respectively connected with the charge starting module 11, the charge-discharge control module 12 and the pump capacitor C_PUMPFirst terminal CP and said pump capacitor C_PUMPAnd a second end CN.

The charge-discharge module 10 is used for accessing a power voltage V_i(VDD) and a first clock signal

The charging starting module 11 is connected with the pump capacitor C_PUMPAnd a second end CN.

The charging start module 11 is used for accessing a first clock signal

And to ground.

The charging and discharging control module 12 is respectively connected with the pump capacitor C_PUMPAnd a second end CN.

The charging and discharging control module 12 is used for accessing a second clock signal CLK₂And a supply voltage V_i(VDD) and is used for ground.

The pump capacitor C_PUMPIs used for outputting a voltage V_out(AVDDCP)。

The charge pump circuit needs to be connected with a first clock signal when in work

And a second clock signal CLK₂To drive the charge pump circuit to work. As shown in FIG. 2, is CLK₁And CLK₂In which the time period phi is₁For the charging phase, time period phi₂Is a discharge phase. Wherein the supply voltage V_i(VDD) respectively with the first clock signal

And the second clock signal CLK₂Are equal.

Optionally, the clock further comprises an inverter for inverting the phase of the first clock signal by 180 degrees to convert the clock signal CLK₁Inverting by 180 degrees to obtain a first clock signal

Based on the non-overlapping clock driving signal timing, during the charging phase phi₁First clock signal

And a second clock signal CLK₂Are all at a high level (VDD), the charging start module 11 controls the charging and discharging module 10 to be the pump capacitor C through the charging control module 12_PUMPCharging, pump the capacitor C_PUMPIs charged to VDD, wherein the pump capacitor C_PUMPThe voltage of the first end CP is VDD, and the pump capacitor C_PUMPAnd the second terminal CN is grounded. In the discharge phase phi₂First clock signal

And a second clock signal CLK₂Are all at low level, the charging start module 11 controls the charging and discharging module 10 to be the pump capacitor C through the charging control module 12_PUMPDischarging and pumping the capacitor C_PUMPThe second terminal CN is pulled up to the power supply voltage VDD, so that the pump capacitor C_PUMPIs pushed to twice VDD, the voltage output of twice VDD is the output voltage V of the charge pump circuit_out(AVDDCP) based on which the output of the charge pump circuit is doubled.

The charge pump circuit further comprises an output diode D0, and the anode of the output diode D0 is connected with the pump capacitor C_PUMPA negative electrode for outputting a voltage V_out(AVDDCP). By connection to the pump capacitor C_PUMPThe output diode D0 of the first terminal CP serves as a protection for the charge pump circuitAnd (4) acting. Optionally, the output diode is a schottky diode.

Wherein the charge pump circuit further comprises an output capacitor C_outSaid output capacitor C_outOne end of the diode is connected with the cathode of the output diode D0, and the other end is grounded. Through an output capacitor C_outThe reducing element being coupled to the output voltage V_outThe noise of (AVDDCP) plays a role of storing electric charges, outputting electric charges, and stabilizing output voltage.

As shown in fig. 3, which is a schematic circuit diagram of a charge pump circuit, the charge/discharge module 10 includes a first charge/discharge transistor M_P1A second charge-discharge transistor and M_P2And a third charge-discharge transistor M_P3(ii) a The first charge-discharge transistor M_P1The grid of the first switch is used for switching in a first clock signal

The drain electrode is connected with the pump capacitor C_PUMPA second end CN; the first charge-discharge transistor M_P1And a second charge-discharge transistor M_P2The drain electrode of the transistor is used for being connected with a power supply voltage V_i(VDD), the second charge-discharge transistor M_P2And the third charge-discharge transistor M_P3Is connected with the pump capacitor C_PUMPThe second charge-discharge transistor M, the first terminal CP of_P2Is connected with the third charge-discharge transistor M_P3Of the substrate.

Wherein, as shown in fig. 3, the charging start module 11 includes a charging start transistor M_N1(ii) a The charge start transistor M_N1The grid of the first switch is used for switching in a first clock signal

The drain electrode is connected with the pump capacitor C_PUMPAnd the source is used for grounding.

As shown in fig. 3, the charge and discharge control module 12 includes a first control transistor M_N2aOR gate OR2 and second control transistor M_N2b(ii) a The first input end of the OR gate circuit OR2 is connected with the pumpContainer C_PUMPA second input terminal for receiving a second clock signal CLK₂(ii) a The first control transistor M_N2aIs used for switching in the second clock signal CLK₂A source connected to ground and a drain connected to the second control transistor M_N2bThe second control transistor M_N2bThe grid of which is used for being connected with a power supply voltage V_i(VDD); the output end of the OR gate circuit OR2 is connected with the third charge-discharge transistor M_P3A gate electrode of (1); the second control transistor M_N2bIs connected with the third charge-discharge transistor M_P3Of the substrate.

The operating principle of the charge pump circuit provided by the present embodiment is explained below in conjunction with the non-overlapping clock driving signal timing of fig. 2 and the principle circuit of the charge pump circuit of fig. 3.

In the charging phase phi₁When CLK is used₂From 0 to VDD, a first control transistor M_N2aConducting, OR gate OR2 outputting high level, second control transistor M_N2bAnd conducting. At this time, the voltage of the node d in the charge pump circuit is pulled down to the ground, so that the second charge/discharge transistor M is driven_P2On, power supply voltage input terminal V_i(VDD) to pump capacitance C_PUMPCharging, pumping capacitor C_PUMPIs pulled down to ground, the pump capacitor C_PUMPThe first terminal CP of (1) is at VDD. In the transition phase delta phi, the first clock signal

At a high level, the second clock signal CLK₂At low level, the first control transistor M_N2aAnd a second control transistor M_N2bAnd closing. In the discharge phase phi₂Pump capacitor C_PUMPThe voltage of the second terminal CN is VDD, the output of the OR gate OR2 becomes VDD and the pump capacitor C_PUMPThe first terminal CP of (a) is twice VDD. Based on this, the third charge-discharge transistor M_P3The voltage at two ends of the oxide layer is VDD, and a third charge-discharge transistor M_P3And working in a safe state.

At the same time, the first control transistor M_N2aAnd a second control transistor M_N2bThe double-power-supply voltage source can bear double VDD voltage, so that the voltage between an oxide layer and a drain/source terminal of any transistor in the charge pump circuit is limited within VDD, so that the charge pump circuit does not have overvoltage of the oxide layer, and the problem of circuit reliability is prevented.

The charge pump circuit provided by this embodiment is implemented by using a pump capacitor C_PUMPThe first terminal CP outputs a voltage, which is reduced by PAD of one output port. Meanwhile, the voltage drop of the transistor on the output link does not exist, so that the influence of the voltage drop of the transistor on the output link on the efficiency is avoided, and the third discharge transistor, namely the third charge and discharge transistor M is reduced conveniently_P3On the basis of which the size of the charge pump circuit is reduced.

In an embodiment, a charge pump is provided, the charge pump comprising the charge pump circuit of any of the above embodiments.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A charge pump circuit is characterized by comprising a charge-discharge module, a charge starting module, a charge-discharge control module and a pump capacitor;

the charge-discharge module is respectively connected with the charge starting module, the charge-discharge control module, the first end of the pump capacitor and the second end of the pump capacitor;

the charge-discharge module is used for accessing power supply voltage and a first clock signal;

the charging starting module is connected with the second end of the pump capacitor;

the charging starting module is used for accessing a first clock signal and grounding;

the charge and discharge control module is respectively connected with the second ends of the pump capacitors;

the charge and discharge control module is used for accessing a second clock signal and power voltage and is used for grounding;

the first end of the pump capacitor is used for outputting voltage;

in a charging phase, the first clock signal and the second clock signal are both at a high level;

the charge and discharge module comprises a first charge and discharge transistor, a second charge and discharge transistor and a third charge and discharge transistor;

the grid electrode of the first charge-discharge transistor is used for accessing a first clock signal, and the drain electrode of the first charge-discharge transistor is connected with the second end of the pump capacitor;

the source electrode of the first charge-discharge transistor and the drain electrode of the second charge-discharge transistor are used for being connected with power supply voltage;

the source electrode of the second charge-discharge transistor and the source electrode of the third charge-discharge transistor are connected with the first end of the pump capacitor;

and the grid electrode of the second charge and discharge transistor is connected with the drain electrode of the third charge and discharge transistor.

The charging starting module comprises a charging starting transistor;

and the grid electrode of the charging starting transistor is used for accessing a first clock signal, the drain electrode of the charging starting transistor is connected with the second end of the pump capacitor, and the source electrode of the charging starting transistor is used for grounding.

The charge and discharge control module comprises a first control transistor, an OR gate circuit and a second control transistor;

the first input end of the OR gate circuit is connected with the second end of the pump capacitor, and the second input end of the OR gate circuit is used for accessing a second clock signal;

the grid electrode of the first control transistor is used for accessing a second clock signal, the source electrode of the first control transistor is used for grounding, the drain electrode of the first control transistor is connected with the source electrode of the second control transistor, and the grid electrode of the second control transistor is used for accessing a power supply voltage;

the output end of the OR gate circuit is connected with the grid electrode of the third charge-discharge transistor;

and the drain electrode of the second control transistor is connected with the drain electrode of the third charge-discharge transistor.

2. The charge pump circuit of claim 1, further comprising an output diode having an anode connected to the first end of the pump capacitor and a cathode for outputting a voltage.

3. The charge pump circuit of claim 2, wherein the output diode is a schottky diode.

4. The charge pump circuit of claim 2, further comprising an output capacitor having one end connected to the cathode of the output diode and the other end connected to ground.

5. The charge pump circuit of claim 1, wherein during a discharge phase, the first clock signal and the second clock signal are both at a low level.

6. The charge pump circuit of claim 1, wherein the power supply voltage is equal to a high level voltage of the first clock signal and a high level voltage of the second clock signal, respectively.

7. A charge pump comprising a charge pump circuit as claimed in any one of claims 1 to 6.