CN107451038B - Hardware event acquisition method, processor and computing system - Google Patents
Hardware event acquisition method, processor and computing system Download PDFInfo
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Abstract
The invention provides a hardware event acquisition method, a processor and a computing system. The hardware event acquisition method comprises the following steps: the method comprises the steps that a processor obtains an event identifier corresponding to a hardware event to be collected; for each event identifier, the processor writes the event identifier in the event field of the control register and writes the event identifier in the event field of an idle hardware counter, so that the hardware counter counts the hardware events to be collected according to the event identifier. The hardware event acquisition method provided by the invention can improve the acquisition efficiency of the hardware event and simultaneously improve the performance of the processor.
Description
Technical Field
The invention relates to the field of computer performance analysis, in particular to a hardware event acquisition method, a processor and a computing system.
Background
In the computer system, the performance counter can acquire the performance data of various hardware in real time, the performance data is analyzed to obtain the running state of the hardware, and the performance of the computer system can be improved by optimizing the operation bottleneck. Wherein various hardware generates events to be processed and the performance counters are sampled based on the hardware events.
At present, in a Microprocessor (MIPS) architecture processor without an interlocked pipeline stage, a performance counter is composed of a pair of registers, specifically including a 32-bit control register and a 32-bit or 64-bit count register. By setting the control register, the counting register can be configured with a specific hardware event, the counting register is self-increased every time the hardware event happens, when the highest bit of the counting register becomes 1, the hardware event overflows upwards, and the performance counter requests interruption.
However, in the above performance counter implementation scheme, each performance counter can only collect one type of hardware event at a time, when multiple types of hardware events need to be collected, performance counters corresponding to the number of hardware events are needed, and the number of registers in the processor is limited, so that the above scheme greatly limits the collection efficiency of the hardware events, and reduces the resource utilization rate and performance of the processor.
Disclosure of Invention
The invention provides a hardware event acquisition method, a processor and a computing system, which can improve the acquisition efficiency of hardware events and improve the performance of the processor.
The hardware event acquisition method provided by the invention is applied to a processor, wherein the processor comprises a performance counter and at least two hardware counters, and the performance counter comprises a control register; the hardware event collection method comprises the following steps:
the processor acquires an event identifier corresponding to a hardware event to be acquired;
for each event identifier, the processor writes the event identifier into the event field of the control register, and writes the event identifier into the event field of an idle hardware counter, so that the hardware counter automatically counts the hardware events to be collected according to the event identifier.
The invention provides a processor, comprising: a performance counter and at least two hardware counters, the performance counter including a control register; further comprising:
the acquisition module is used for acquiring an event identifier corresponding to a hardware event to be acquired;
and the processing module is used for writing the event identifier into the event field of the control register and writing the event identifier into the event field of an idle hardware counter for each event identifier so that the hardware counter automatically counts the hardware events to be acquired according to the event identifiers.
The invention provides a computing system comprising: a memory and a processor as provided in any embodiment of the invention;
the memory to store instructions;
the processor is configured to execute the instructions stored in the memory to execute the hardware event collection method provided in any embodiment of the present invention.
The invention provides a hardware event acquisition method, a processor and a computing system. According to the hardware event acquisition method provided by the invention, the performance counter is used as a configuration interface for acquiring the hardware events, the processor can establish a mapping relation between the hardware events and the hardware counters by configuring different hardware events in the control register, so that the hardware counters respectively count the hardware events, the hardware events are acquired by one performance counter at the same time, the acquisition efficiency of the hardware events is improved, and the resource utilization rate and the performance of the processor are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart of a hardware event collection method according to an embodiment of the present invention;
fig. 2A is a schematic diagram illustrating a format of a control register according to an embodiment of the invention;
fig. 2B is a schematic diagram of a format of a hardware counter according to an embodiment of the present invention;
fig. 3 is a flowchart of a hardware event collection method according to a second embodiment of the present invention;
FIG. 4 is a diagram illustrating a format of a count register according to a second embodiment of the present invention;
fig. 5 is a schematic structural diagram of a processor according to a second embodiment of the present invention;
fig. 6 is a schematic structural diagram of a computing system according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The hardware event collection method, the processor and the computing system provided by the embodiment of the invention are mainly applied to a scene needing to collect a plurality of hardware events and are used for solving the problems of low hardware event collection efficiency and low resource utilization rate of the processor at present.
Fig. 1 is a flowchart of a hardware event collection method according to an embodiment of the present invention, where the hardware event collection method is applied to a processor, where the processor may include a performance counter and at least two hardware counters, and the performance counter may include a control register, for example, in a computer system, the processor is a Central Processing Unit (CPU). As shown in fig. 1, the hardware event collecting method provided in this embodiment may include:
Specifically, the event identifier is used to uniquely distinguish different hardware events to be collected. In this embodiment, the processor obtains an event identifier, where the event identifier may be one or multiple, and correspondingly, the hardware event to be collected may be one or multiple. The present embodiment is mainly applied to a scenario in which a plurality of hardware events to be collected are present, and of course, the present embodiment may also be applied to a scenario in which only one hardware event to be collected is present. The embodiment does not limit the specific implementation manner of the event identifier, for example: may be a number, may be a string, etc.
In one implementation manner, when a tester needs to perform a performance test on a certain application program, the tester designates an application program name to be tested and a hardware event to be collected through test software, wherein the hardware event to be collected may be an event name, the test software transmits the application program name to be tested and the event name to a kernel in a parameter form, a corresponding relationship between the event name and an event identifier is stored in the kernel program, and a processor runs the kernel program to obtain the event identifier corresponding to the hardware event to be collected. After that, the application to be tested starts executing, and at the same time, the hardware events to be collected start counting.
In another implementation manner, when a tester needs to perform a performance test on an application program, the tester specifies the name of the application program to be tested and an event identifier corresponding to a hardware event to be collected through test software, the test software transmits the name of the application program to be tested and the event identifier to a kernel in a parameter form, and the processor runs the kernel program to obtain the event identifier corresponding to the hardware event to be collected. After that, the application to be tested starts executing, and at the same time, the hardware events to be collected start counting.
In the implementation mode, the kernel is bottom-layer software which provides safe access to computer hardware for a plurality of application software, the testing software and the application program to be tested both belong to the application software, and are high-level software which runs based on the kernel and the computer hardware, wherein the testing software provides a human-computer interaction interface for testing personnel.
The hardware events are corresponding to the software events, and refer to events generated by various hardware and needing to be processed. For example, in a computer system, a hardware event may be: internal pipeline clocks, number of committed instructions per cycle, committed branch instructions, committed mispredicted branch instructions, etc., processor-defined hardware events may be specifically used to:
(1) the method comprises the steps of analyzing the characteristics of a program on an instruction set hierarchy, specifically counting the number of different types of instructions in a pipeline submitting stage, and obtaining the distribution condition of the types of the dynamic execution instructions of the program.
(2) The method is used for analyzing the performance bottleneck of program codes in the process of interacting with the micro-structure of the microprocessor, and the starting point is to optimize the program mainly by counting various events causing pipeline blockage.
(3) For the exploration of the accumulated data for the design space, the starting point is to optimize the microstructure. For example, the statistics of the number of conflicts of a cache Random access memory (dcachem) of two load operations (called load) in the same beat.
And 103, for each event identifier, writing the event identifier into the event domain of the control register by the processor, and writing the event identifier into the event domain of an idle hardware counter so that the hardware counter counts the hardware events to be acquired according to the event identifier.
In this step, the performance counter in the processor is not used as an actual counter, but is used as a configuration interface of the hardware event, and the hardware counter in the processor is used as an actual counter to complete the counting of the hardware event. By configuring the hardware event in the control register of the performance counter, the processor can establish a corresponding relation between the hardware event to be collected and a certain idle hardware counter in the processor, the hardware counter automatically counts and collects the hardware event, and the hardware counter is added by 1 time when the configured hardware event occurs once.
When the number of the hardware events to be collected is multiple, the processor repeatedly executes the step, that is, one hardware event to be collected is repeatedly configured in the event domain of the control register, and the processor enables a plurality of idle hardware counters to be in one-to-one correspondence with all the hardware events to be collected, and the hardware counters count and collect the hardware events, so that all the hardware events to be collected are counted.
The position of the event field of the control register in the control register and the size of the event field are set as required, which is not limited in this embodiment.
Fig. 2A shows a specific implementation manner of the control register, and fig. 2A is a schematic format diagram of the control register according to an embodiment of the present invention, as shown in fig. 2A, the control register is a 32-bit register, the number of bits is 0 to 31, and an EVENT field (also referred to as an EVENT field) is 5 th to 14 th bits.
The position of the event field of the hardware counter in the hardware counter and the size of the event field are set as required, which is not limited in this embodiment.
Fig. 2B shows a specific implementation manner of a hardware counter, and fig. 2B is a schematic format diagram of the hardware counter according to an embodiment of the present invention, as shown in fig. 2B, the hardware counter COUNTs 64 bits, the number of the bits is 0 to 63, and the hardware counter includes an EVENT field (also referred to as an EVENT field) and a COUNT field (also referred to as a COUNT field), where the EVENT field is 0 to 9 bits, and the COUNT field is 10 to 63 bits. When a hardware EVENT corresponding to the EVENT identifier in the EVENT field occurs once, 1 is automatically added in the COUNT field.
The following describes the hardware event collection method provided in this embodiment in detail by taking specific numbers as examples. Assuming that three hardware events need to be collected, and event identifiers of the three hardware events are A, B, C, the hardware event collection method provided in this embodiment specifically includes: the processor acquires event identifications corresponding to 3 hardware events to be acquired, wherein the event identifications are A, B, C respectively, the processor firstly writes A in an event domain of a control register and writes A in an event domain of an idle hardware counter a, so that the hardware counter a automatically counts the hardware events according to the event identifications A; the processor continues to write B in the event field of the control register and writes B in the event field of an idle hardware counter B so that the hardware counter B automatically counts the hardware events according to the event identifier B; the processor continues to write C in the event field of the control register and writes C in the event field of an idle hardware counter C, so that the hardware counter C automatically counts the hardware events according to the event identifier C, and thus, the hardware counters a, b and C can count three hardware events simultaneously.
It can be seen that, in the hardware event collection method provided in this embodiment, the performance counter is used as a configuration interface for collecting hardware events, and different hardware events are configured in the control register, and the processor can establish a mapping relationship between a plurality of hardware events and a plurality of hardware counters, so that the plurality of hardware counters respectively count the plurality of hardware events, and thus, a plurality of hardware events can be collected simultaneously by one performance counter.
It should be noted that, according to actual needs, the maximum number of hardware events collected by one performance counter at the same time may be set, for example: if the processor comprises 4 performance counters, the maximum number of hardware events that can be collected by the 4 performance counters at the same time is 4 × 20 — 80.
It should be noted that, regarding the type of the performance counter, the present embodiment is not limited.
Alternatively, the performance counter may be a coprocessor 0 (CP 0) register.
The embodiment provides a hardware event collecting method, which includes: the processor obtains event identifications corresponding to the hardware events to be collected, writes the event identifications into the event field of the control register for each event identification, and writes the event identifications into the event field of an idle hardware counter, so that the hardware counter counts the hardware events to be collected according to the event identifications. In the hardware event collection method provided by this embodiment, the performance counter is used as a configuration interface of a hardware event, and can collect a plurality of hardware events at the same time, so that the collection efficiency of the hardware event can be improved, and the resource utilization rate and performance of the processor can be improved at the same time.
Fig. 3 is a flowchart of a hardware event collection method according to a second embodiment of the present invention, and this embodiment provides another implementation manner of the hardware event collection method based on the first embodiment. In the hardware event collection method provided in this embodiment, the performance counter further includes a count register, and the hardware event collection method further includes:
in step 201, if the processor obtains a hardware event collection end instruction, the processor stops counting of the hardware counter and reads an event identifier in an event domain of the hardware counter into an event domain of the control register.
Specifically, the hardware event collection end instruction is used for indicating the end of the hardware event count to be collected. It should be noted that the hardware event collection end instruction in this embodiment is only one name of an instruction, and the instruction may also be other names, and is mainly used to indicate that the count of the hardware event to be collected is ended.
In one implementation, when the execution of the application program to be tested is finished, the kernel generates a hardware event collection end instruction, and the processor executes the kernel program to obtain the hardware event collection end instruction.
In another implementation manner, when a tester stops execution of an application program through test software, a kernel generates a hardware event collection end instruction, and a processor executes the kernel program to obtain the hardware event collection end instruction.
In this step, a performance counter in the processor serves as a read-write interface of the hardware event, when a hardware event acquisition end instruction is obtained, the counting of the hardware counter is stopped, and the value acquired by the hardware counter can be further processed by reading an event identifier in an event domain of the hardware counter into an event domain of the control register.
In step 203, the processor reads the value in the count field of the hardware counter into the count register.
In this step, after the hardware event collection is completed, the processor reads the value in the count field of the hardware counter into the count register, and the performance counter is used as the read-write interface function in the hardware event collection process.
The specific format of the count register is set as required, which is not limited in this embodiment.
Fig. 4 shows a specific implementation manner of the count register, and fig. 4 is a schematic format diagram of the count register according to the second embodiment of the present invention, as shown in fig. 4, the count register is a 64-bit register, and the number of bits is 0 to 63.
In this step, the counting register stores the counting result of the hardware event to be collected, and the processor may further analyze and process the value, for example: the value is processed to learn the performance of the application.
It can be seen that, in the hardware event collection method provided in this embodiment, the performance counter is used as a read-write interface for collecting the hardware event, when the hardware event is counted, the hardware event is repeatedly configured in the control register, so that the collection result of the hardware event can be read into the count register, and the processor can perform further performance analysis according to the collection result of the hardware event. Compared with the prior art that only one hardware event can be acquired by one performance counter at a time, the hardware event acquisition method provided by the embodiment improves the acquisition efficiency of the hardware event and simultaneously improves the resource utilization rate and the performance of the processor.
The following describes the hardware event collection method provided in this embodiment in detail by taking specific numbers as examples. Assuming that the three hardware events are counted, the event identifiers are A, B, C, and the hardware counters corresponding to the three event identifiers are a, b, and c, respectively, then the hardware event collecting method provided in this embodiment specifically includes: the processor acquires a hardware event acquisition ending instruction, stops counting of hardware counters a, b and c, writes A in an event domain of the control register, reads a numerical value in the counting domain of the hardware counter a into the counting register, and performs hardware event analysis according to the numerical value in the counting register; continuing to write B in the event field of the control register, reading the numerical value in the counting field of the hardware counter B into the counting register, and analyzing the hardware event according to the numerical value in the counting register; and C is continuously written into the event field of the control register, the numerical value in the counting field of the hardware counter C is read into the counting register, and the hardware event analysis is carried out according to the numerical value in the counting register, so that the counting result of three hardware events can be obtained by one performance counter.
Optionally, the control register and the count register are CP0 registers with adjacent register numbers, and the register number of the control register is smaller than the register number of the count register.
For example, if 8 CP0 registers have a register number of 0-8, the CP0 register 0, the CP0 register 2, the CP0 register 4, and the CP0 register 6 may be control registers, the CP0 register 1, the CP0 register 3, the CP0 register 5, and the CP0 register 7 may be count registers, the CP0 register 0 and the CP0 register 1 may form a performance counter, the CP0 register 2 and the CP0 register 3 may form a performance counter, the CP0 register 4 and the CP0 register 5 may form a performance counter, and the CP0 register 6 and the CP0 register 7 may form a performance counter.
The embodiment provides a hardware event collection method, after the hardware event counting is finished, the hardware event collection result in a hardware counter is read into a counting register, a processor can perform further performance analysis according to the collection result of the hardware event, and the collection results of a plurality of hardware events can be obtained through one performance counter, so that the collection efficiency of the hardware event is improved, and the resource utilization rate and the performance of the processor are improved.
Fig. 5 is a schematic structural diagram of a processor according to an embodiment of the present invention, where the processor provided in this embodiment is configured to execute the hardware event collection method provided in any one of fig. 1 to 4. As shown in fig. 5, the processor provided in this embodiment may include: a performance counter 11 and at least two hardware counters 12, the performance counter 11 comprising a control register 111. The method can also comprise the following steps:
the obtaining module 21 is configured to obtain an event identifier corresponding to a hardware event to be collected.
The processing module 22 is configured to write an event identifier in the event field of the control register 111 for each event identifier, and write an event identifier in the event field of an idle hardware counter 12, so that the hardware counter 12 counts the hardware events to be collected according to the event identifier.
Optionally, the performance counter 11 may further include a count register 112.
The obtaining module 21 is further configured to receive a hardware event collection end instruction.
The processing module 22 is further configured to, if the obtaining module 21 obtains the hardware event collection end instruction, stop counting of the hardware counter 12, and read an event identifier in an event domain of the hardware counter 12 into the event domain of the control register 111.
The processing module 22 is further configured to read the value in the count field of the hardware counter 12 into the count register 112, and perform hardware event analysis according to the value in the count register 112.
Optionally, the control register 111 and the count register 112 are coprocessor 0 registers whose register numbers are adjacent to each other, and the register number of the control register 111 is smaller than the register number of the count register 112.
The processor provided in this embodiment is used for executing the operations executed by the processor in the method embodiments shown in fig. 1 to fig. 4, and the technical principle and the technical effect are similar and will not be described again here.
The embodiment provides a processor, including: the performance counter includes control register, still includes: the device comprises an acquisition module and a processing module. The processor provided by the embodiment can improve the acquisition efficiency of hardware events and improve the resource utilization rate and performance of the processor.
Fig. 6 is a schematic structural diagram of a computing system according to an embodiment of the present invention. As shown in fig. 6, the computing system provided in this embodiment may include: a memory 31 and a processor 32 provided by any of the method embodiments of the present invention.
A memory 31 for storing instructions.
And the processor 32 is configured to execute the instructions stored in the memory 31 to execute the hardware event collection method provided by any embodiment of the present invention.
The composition structure and the implementation principle of the processor in this embodiment specifically refer to the description of the embodiment shown in fig. 5, and the implementation principle of the hardware event acquisition method in this embodiment specifically refer to the description of any one of the embodiments shown in fig. 1 to 4, which are not described herein again.
The embodiment does not limit the specific type of the computing system, for example: the computing system may be a computer, a server, a mobile device, an electronic device, a single chip, or the like.
The present embodiment does not limit the specific type of the memory 31, for example: the Memory 31 may be a Non-Volatile Memory (NVRAM), a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), a hard disk, a Flash Memory (Flash), or the like.
The computing system provided in this embodiment may further include an input/output interface, a network interface, an input/output device, a display device, a camera, an audio input device, and the like.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (7)
1. The hardware event acquisition method is applied to a processor, wherein the processor comprises a performance counter and at least two hardware counters, and the performance counter comprises a control register and a counting register; the hardware event collection method comprises the following steps:
the processor acquires an event identifier corresponding to a hardware event to be acquired;
for each event identifier, the processor writes the event identifier into an event field of the control register, and writes the event identifier into an event field of an idle hardware counter, so that the hardware counter counts the hardware events to be collected according to the event identifier;
and the processor reads the numerical value in the counting field of the hardware counter into the counting register.
2. The method of claim 1, further comprising:
if the processor acquires a hardware event acquisition ending instruction, stopping counting of the hardware counter by the processor, and reading an event identifier in an event domain of the hardware counter into the event domain of the control register;
and the processor analyzes the hardware event according to the numerical value in the counting register.
3. The method of claim 2, wherein the control register and the count register are coprocessor 0 registers adjacent in register number, and wherein the register number of the control register is less than the register number of the count register.
4. A processor, comprising: the system comprises a performance counter and at least two hardware counters, wherein the performance counter comprises a control register and a counting register; further comprising:
the acquisition module is used for acquiring an event identifier corresponding to a hardware event to be acquired;
the processing module is used for writing the event identifier into the event field of the control register and writing the event identifier into the event field of an idle hardware counter for each event identifier so that the hardware counter counts the hardware events to be acquired according to the event identifiers;
the processing module is further configured to write a value in a count field of the hardware counter into the count register.
5. The processor of claim 4,
the acquisition module is also used for receiving a hardware event acquisition ending instruction;
the processing module is further configured to, if the obtaining module obtains the hardware event collection end instruction, stop counting of the hardware counter, and write an event identifier in an event domain of the hardware counter into the event domain of the control register;
the processing module is further used for analyzing the hardware event according to the numerical value in the counting register.
6. The processor of claim 5, wherein the control register and the count register are coprocessor 0 registers adjacent in register number, and wherein the register number of the control register is less than the register number of the count register.
7. A computing system, comprising: a memory and a processor as claimed in any one of claims 4 to 6;
the memory to store instructions;
the processor, configured to execute the instructions stored in the memory to perform the hardware event collection method according to any one of claims 1 to 3.
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| CN111209155B (en) * | 2018-11-21 | 2022-09-23 | 华夏芯（北京）通用处理器技术有限公司 | Performance detection method convenient for expansion and configuration |
| CN110688289B (en) * | 2019-09-11 | 2023-08-08 | 上海高性能集成电路设计中心 | Processor performance event dynamic monitoring method based on simulation |
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| CN105487958A (en) * | 2015-11-24 | 2016-04-13 | 无锡江南计算技术研究所 | Processor internal behavior monitoring method |
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| US7272754B2 (en) * | 2003-09-27 | 2007-09-18 | International Business Machines Corporation | Implementation-efficient multiple-counter value hardware performance counter |
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| CN1378679A (en) * | 1999-10-13 | 2002-11-06 | 全斯美达有限公司 | Programmable event computer system |
| CN101859268A (en) * | 2009-04-08 | 2010-10-13 | 英特尔公司 | Context switch sampling |
| CN102750130A (en) * | 2011-04-15 | 2012-10-24 | 国际商业机器公司 | Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions |
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