CN107402799A - The method for performing TMS320C25 chip assembly instructions is explained in X86 computers ultrahigh speed - Google Patents
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Abstract
The present invention relates to a kind of method explained in X86 computers ultrahigh speed and perform TMS320C25 chip assembly instructions, belong to power technology field.The present invention proposes a kind of method explained in X86 computers ultrahigh speed and perform TMS320C25 chip assembly instructions.This method is without using special emulator, assembly instruction can be run by efficient Fast simulation under a windows environment, by many general testing tool, magnanimity test case is performed at a high speed, the function accuracy of fast and effective checking assembly language program(me), code coverage is obtained, white-box testing is carried out to measured piece, so as to improve the testing adequacy of assembly language program(me).
Description
Technical field
The present invention relates to software testing technology field, and in particular to a kind of explained in X86 computers ultrahigh speed performs
The method of TMS320C25 chip assembly instructions.
Background technology
In software test, the programmed readability write using assembler language is poor, and code inspection efficiency is low, and related
Test support instrument is few, and adoptable means of testing is limited, or because lacking the emulator for supporting this kind of chip, causes to enter
Line code examines or Black-box Testing.Because method of testing and means are limited, also cause the quality of assembly code program barely satisfactory.
The progress of assembly language program(me) is fully tested, then cycle length, the difficulty tested are high.
The content of the invention
(1) technical problems to be solved
The technical problem to be solved in the present invention is：How to be explained in X86 computers ultrahigh speed and perform TMS320C25 chips compilation
The method of instruction.
(2) technical scheme
In order to solve the above-mentioned technical problem, explained the invention provides one kind in X86 computers ultrahigh speed and perform TMS320C25
The method of chip assembly instruction, comprises the following steps：
Code translation in S1, the assembler language file that needs are translated into C language, the code be assembly instruction or its
Corresponding binary code：The assembler language file for needing to translate is read, regularization first is carried out to code, removes invalid code,
Then valid code is analyzed, numerical value corresponding to extraction variable, the address of variable is defined as grand, the starting of identification module
Position and end position, module is set as function, extracts operational order and operand, label is extracted, is translated on request,
And with redirecting in goto sentence alternative programs, export translated C code, and the code in assembler language file to annotate
Mode inserted by row in the C code, form translated C code file；
S2, using Microsoft Visual Studio translation and compiling environments by the code compilation in C code file into can be
The code performed under Windows environment and debugging are performed at full speed, and variable or register can be checked at any time in implementation procedure
Value and situation of change.
Preferably, the step of also including distinguishing data field and program area before step S1, the instruction in described program area includes
Order execute instruction, direct jump instruction or conditional jump instructions, the code of assembly instruction translate directly into C language, redirected
Using label form, realized with goto sentences, redirecting for binary code still uses label, every binary code is turned over
C code is translated into, and encloses numbering；For the data in program area, in translation process, it is fixed that directly the data in program area are write
In the good array of justice, and it is grand the label definition of data, is directly read from array during to simulate execution；For data
Area, simulated using array.
Preferably, in step S1, according to the difference of operational order addressing system, different translation sides is performed to operational order
Formula：
In immediate addressing mode, include immediate operand in operational order, during translation by immediate operand directly with deposit
Device carries out computing；
In direct addressing method, operational order includes low 7 of data memory addresses, this 7 and data storage page
9 connections of pointer DP registers form complete 16 data memory addresses, and such DP registers point to certain in page 512
One page, every page of 128 words, 7 discrete cells for pointing to this page in instruction；
Indirect addressing mode is to provide addressable address with background register AR, can directly obtain 8 background register AR0-
The data that 16 bit address return in AR7, when translating into C code, internal memory definition is turned into 2 dimension group Unsigned short MEM
[512] [128], address is converted when simulating indirect addressing.
Preferably, in step S1, according to the operational order of different calculation methods, different interpretative systems is performed：
Addition instruction ADD DAT1 translation is divided into 4 steps, be respectively sign bit extension process, carry processing, Overflow handling and
Assignment after the completion of calculating：
The addition instruction ADD DAT1 of table 1 translation process
For multiplying order, after defining the register required for multiplication, directly the T register of the multiplier of preservation multiplication and
16 data are multiplied, and product is put into the P register for the product for preserving multiplication.
(3) beneficial effect
The present invention proposes a kind of method explained in X86 computers ultrahigh speed and perform TMS320C25 chip assembly instructions.Should
Method can run assembly instruction by efficient Fast simulation, by a variety of logical under a windows environment without using special emulator
With testing tool, magnanimity test case is performed at a high speed, the function accuracy of fast and effective checking assembly language program(me), obtains code
Covering, white-box testing is carried out to measured piece, so as to improve the testing adequacy of assembly language program(me).
Brief description of the drawings
Fig. 1 is the basic flow sheet that precompile mode handles assembly code；
Fig. 2 is the translation processing schematic diagram to measured piece；
Fig. 3 is that DSP performs the processing schematic diagram of the flow interrupted and precompile processing mode to interruption.
Embodiment
To make the purpose of the present invention, content and advantage clearer, with reference to the accompanying drawings and examples, to the present invention's
Embodiment is described in further detail.
The present invention be achieved in that using precompilation techniques in strict accordance with instruction manual TMS320C25 assembler languages or
Binary code after person's compiling translates into standard C language, is handled by precompilation techniques.Assembly code is translated into C code
After have following characteristics：
1. strictly translated by instruction manual, implementing result and implementing result one of the assembly code on dsp chip of C code
Cause；
2. after being compiled into standard C language, adoptable testing tool is more, and means of testing is more, unit testing can be conveniently carried out
And white-box testing；
3. the executable program for running on Windows environment can be compiled into, magnanimity test case is performed at a high speed, and adopt automatically
Collect and judge test result, test case execution efficiency is high.
The present invention's realizes that the basic procedure of the cross-platform Fast simulation operation of assembly language program(me) is shown in using precompile mode
Fig. 1.Explained in X86 computers ultrahigh speed and perform being achieved in that for TMS320C25 chip assembly instructions：
S1, assembly instruction or binary command are first translated into standard C language；
S2, the generation that can be performed under a windows environment is compiled into using Microsoft Visual Studio translation and compiling environments
Code is simultaneously debugged or performed at full speed, and the value and situation of change of certain variable or register, effect can be checked at any time in implementation procedure
It is similar with emulator.With reference to coverage rate test instrument, white-box testing can be carried out to assembly code directly on PC.
After step S1 translation process is as shown in Fig. 2 read the assembler language file for needing to translate, professional etiquette first is entered to code
Then change, remove the invalid codes such as annotation, then valid code is analyzed, numerical value corresponding to variable is extracted, the ground of variable
Location is defined as grand, the starting and ending of identification module, and module is set as that function (needs to insert auxiliary to the code of modularization difference
Cognizance code, identification module during for translating), operational order and operand are extracted, extracts label, on request interpretive order, and
With redirecting in goto sentence alternative programs.Translated C code is exported, and source assembly code is inserted in a manner of annotating by row
Enter in C code (convenient debugging uses), form translated C code file.Auxiliary code is write, with translated C code text
Part after compiling link, debugging or operation measured piece, carries out data interaction with peripheral environment, Mobile state survey is entered to measured piece together
Examination.
Chip TMS320C25 is fixed-point calculation chip, if floating-point operation chip, it is necessary to handle data format
(TM320C3X series floating number is that TI forms are different from ieee standard form)
Explain that the key technology for performing TMS320C25 chip assembly instructions is as follows in X86 computers：
One program area and data field processing
1. the instruction in program area
The instruction of program area has order execute instruction, direct jump instruction or conditional jump instructions, the code of assembly instruction
C language is translated directly into, is redirected using label form, is realized with goto sentences, binary code is redirected still using mark
Number, in order to redirect conveniently, every binary code is translated into C code, and enclose numbering.
The method that assembler language and binary code translate directly into C code is shown in example 1 and example 2.
Example 1：Assembly code translates directly into C code
Example 2：Binary code corresponding to assembly code translates into C code
2. the data in program area
In assembly code, program area also some fixed value datas can be used to calculate in programming, in program operation process,
Data field is moved to using special instruction.
Precompile processing mode simulates data of the programming in program area using special array, in pretreatment translation process
In, directly numerical value is write in the array defined, and data label definition to be grand, directly from array during to simulate execution
Middle reading.
The mode of data in processing PM program areas is shown in example 3.
Example 3：Handle the mode of the data in PM program areas
3. data field is simulated
Precompile processing mode, come analogue data area, for example defines the array of the size of 512k × 32 directly using array
Unsigned int MEM [0x80000], TMS320C25 addressing spaces are 64K × 16, using 9 page pointers and 7 bit address knots
The addressing system of conjunction, therefore data field can be defined as 2 dimension group unsigned short MEM [512] [128].
Example 4：The simulation of DM data fields uses
The storehouse size of VC6.0 thread default allocations is 1M, defines larger array if desired more than 1M, it is necessary to weight
It is new that storehouse size is set.
2nd, addressing system is handled
Addressing system typically has immediate addressing mode, direct addressing method, indirect addressing mode, register addressing, deposit
A variety of addressing systems such as device indirect addressing, indexed addressing, relative addressing, here with immediate addressing mode, direct addressing method and
Exemplified by this 3 kinds of addressing systems of indirect addressing mode, when illustrating assembler language to translate into C language, various addressing how are handled.
1. immediate addressing mode
In immediate addressing mode, immediate operand is included in coding line, immediate directly carries out computing with register.Processing
Immediate addressing mode is shown in example 5.
Example 5：The processing of immediate addressing mode
| Assembly code | Translate into C code |
| Value in 8 ← ACC of ADDK adds immediate 8 | ACC=ACC+8； |
| Value in 9 ← ACC of SUBK subtracts immediate 8 | ACC=ACC-9； |
2. direct addressing method
In direct addressing method, coding line includes low 7 of data memory addresses, and this 7 refer to data storage page
9 connections of pin (DP) register form complete 16 data memory addresses, and such DP registers point to certain in page 512
One page, every page of 128 words, 7 discrete cells for pointing to this page in instruction.The processing mode of direct addressin is shown in example 6.
Example 6：The processing of direct addressing method
3. indirect addressing mode
Indirect addressing mode is to provide addressable address with background register (AR), can directly obtain 8 background registers
(AR0-AR7) data that the bit address of some in 16 returns.During due to translating into C code, direct addressin is handled for convenience, in
Depositing definition turns into 2 dimension group Unsigned short MEM [512] [128], all to need to enter address when simulating indirect addressing
Line translation.The processing mode of indirect addressing is shown in example 7.
Example 7：The processing of indirect addressing mode
3rd, computational methods
1. addition and subtraction
The instruction of plus and minus calculation is more, and the instruction of conventional plus-minus is shown in Table 1.
The conventional plus-minus instruction of table 1
Plus-minus command operating is also influenceed by sign bit extended register (SXM) and overflow protection register (OVM), also shadow
Ring carry status register (C).Assembly statement ADD DAT1 (ACC=ACC+DAT1) are performed, if register SXM is 1, show 16
Bit variable DAT1 is signed number, needs to carry out symbol Bits Expanding when being added with 32 bit accumulators；If register SXM is 0, show
16 bit variable DAT1 are unsigned number, need not carry out symbol Bits Expanding during addition；If register OVM is 1, it is necessary to be overflowed
Protection；If register OVM is 0, it is not necessary to carries out overflow protection.
If assembly statement ADD DAT1 are translated directly into C code：ACC=ACC+MEM [P_DP] [DAT1], program fortune
Guild is wrong, because being related to symbol Bits Expanding, overflow protection and carry.In view of symbol Bits Expanding, carry and overflow guarantor
After shield, translation will be much more complex.
When carrying out add operation, first have to be defined the register that addition uses, the definition side that program uses
Formula is shown in example 8.
Example 8：Define plus and minus calculation it is used register and grand
After symbol Bits Expanding, carry and overflow protection, the translation of ADD DAT1 assembly instructions is divided into 4 steps, respectively
It is assignment after the completion of sign bit extension process, carry processing, Overflow handling and calculating.Specific processing mode example 9.
Example 9：The translation process of addition instruction (ADD DAT1)
2. multiplication
DSP execution efficiency is high, can carry out the parallel computation of addition and multiplication simultaneously, therefore multiplying order is used with adding
Method instructs independent register, and the operation of multiplying order is usually the data (16 or 8) and T register in instruction
(16) multiplications, are then placed in P register (32).The value of P register is put after being shifted by the requirement of PM shift registers
Enter in ACC.Conventional multiplying order is shown in Table 2.
The conventional multiplying order of table 2
The processing mode that multiplication calculates is, after the register required for definition multiplication, directly T register (16) and 16
Position data are multiplied, and product is put into P register (32), and due to being that 16 digits multiply 16 digits, product is put into 32 deposits
Device, do not consider to overflow.Processing mode is shown in example 10 and example 11.
Example 10：Register is used to obtain in multiplying
Example 11：The translation processing of multiplying
3. other computings and redirect
It is conventional with or, ask negative and the computing such as redirect and be shown in Table 3.
Other conventional computings of table 3
Consider to overflow with addition to carry except asking negative computing to need, the detailed processing mode of other command functions is shown in example 12.
The translation processing mode of other instructions of example 12
4th, the processing of interrupt service routine
Precompile processing mode simulates the execution of DSP interrupt program by the way of interrupt service routine is directly invoked.
In DSP true environments, if generating interrupt signal, DSP can determine whether to allow to respond the interruption, if allowing, perform
Corresponding interrupt service routine, wherein interrupt requests inquiry, interrupt allow inquiry, interrupt priority level judge etc. operation be by
What DSP hardware itself judged, performed parallel with programmed instruction；When the condition of interruption all meets, then save routine performs pointer
(PC), then start to perform interrupt routine, after the completion of execution, and recovery routine performs pointer (PC), and program continuation order performs.
Function call returns to the function of continuing executing with function after having the function for performing and calling, therefore can use and directly invoke function
Mode carrys out the execution of simulation interruption service routine.
Precompile processing mode simulation interruption, which performs, 2 kinds of modes, and the first is that the shape interrupted is handled in strict accordance with DSP
Formula, after every instruction has performed, all carry out whether interrupt inquiry has interruption, if meeting condition, call interrupt service routine；
Second is to directly invoke interruption in the place for being expected to perform interrupt service routine, does not go to inquire about the value of each register, saves
Omit and often performed the operation that an instruction is intended to inquiry interruption.
Precompile is shown in Fig. 3 to the processing mode of interruption compared with DSP true environments are to the processing mode of interruption.
The invention discloses the method for explaining execution TMS320C25 chip assembly instructions in X86 computers ultrahigh speed, this method
Without using special emulator, assembly instruction can be run by efficient Fast simulation under a windows environment, surveyed by many general
Trial work has, and the present invention can perform magnanimity test case, the function accuracy of fast and effective checking assembly language program(me), to quilt at a high speed
Survey part and carry out white-box testing, so as to improve the adequacy of assembly language program(me) test.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, some improvement and deformation can also be made, these are improved and deformation
Also it should be regarded as protection scope of the present invention.
Claims (4)
1. a kind of explain the method for performing TMS320C25 chip assembly instructions in X86 computers ultrahigh speed, it is characterised in that including
Following steps：
Code translation in S1, the assembler language file that needs are translated is into C language, and the code is assembly instruction or it is corresponding
Binary code：The assembler language file for needing to translate is read, regularization first is carried out to code, removes invalid code, then
Valid code is analyzed, numerical value corresponding to extraction variable, the address of variable is defined as grand, the original position of identification module
And end position, module is set as function, extracts operational order and operand, label is extracted, is translated, be used in combination on request
Redirecting in goto sentence alternative programs, translated C code is exported, and side of the code in assembler language file to annotate
Formula is inserted in the C code by row, forms translated C code file；
S2, using Microsoft Visual Studio translation and compiling environments by the code compilation in C code file into can be
The code performed under Windows environment and debugging are performed at full speed, and variable or register can be checked at any time in implementation procedure
Value and situation of change.
2. the method as described in claim 1, it is characterised in that also include the step for distinguishing data field and program area before step S1
Suddenly, the instruction in described program area includes order execute instruction, direct jump instruction or conditional jump instructions, the code of assembly instruction
C language is translated directly into, is redirected using label form, is realized with goto sentences, binary code is redirected still using mark
Number, every binary code is translated into C code, and enclose numbering；For the data in program area, in translation process, directly
Connect and the data in program area are write in the array defined, and be grand the label definitions of data, it is straight during to simulate execution
Connect and read from array；For data field, simulated using array.
3. the method as described in claim 1, it is characterised in that right according to the difference of operational order addressing system in step S1
Operational order performs different interpretative systems：
In immediate addressing mode, immediate operand is included in operational order, directly enter immediate operand with register during translation
Row computing；
In direct addressing method, operational order includes low 7 of data memory addresses, this 7 and data storage page pointer
9 connections of DP registers form complete 16 data memory addresses, and such DP registers point to a certain in page 512
Page, every page of 128 words, 7 discrete cells for pointing to this page in instruction；
Indirect addressing mode is to provide addressable address with background register AR, can directly be obtained in 8 background register AR0-AR7
The data that 16 bit address return, when translating into C code, internal memory definition is turned into 2 dimension group Unsigned short MEM [512]
[128], address is converted when simulating indirect addressing.
4. the method as described in claim 1 or 2 or 3, it is characterised in that in step S1, according to the operation of different calculation methods
Instruction, performs different interpretative systems：
Addition instruction ADD DAT1 translations are divided into 4 steps, are sign bit extension process, carry processing, Overflow handling and calculating respectively
After the completion of assignment：
The addition instruction ADD DAT1 of table 1 translation process
For multiplying order, after defining the register required for multiplication, directly the T register of the multiplier of preservation multiplication and 16
Data are multiplied, and product is put into the P register for the product for preserving multiplication.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109992516A (en) * | 2019-04-03 | 2019-07-09 | 北京中科寒武纪科技有限公司 | A kind of detail programming method, apparatus and Related product |
| CN110825386A (en) * | 2019-11-01 | 2020-02-21 | 腾讯科技（深圳）有限公司 | Code compiling method and device and storage medium |
| CN114035767A (en) * | 2021-08-27 | 2022-02-11 | 常熟理工学院 | TEC-XP16 combined logic controller instruction design method |
| CN119883373A (en) * | 2025-03-25 | 2025-04-25 | 飞腾信息技术有限公司 | Real vector operation processing method, device, equipment and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004252807A (en) * | 2003-02-21 | 2004-09-09 | Matsushita Electric Ind Co Ltd | Software development support equipment |
| CN101414278A (en) * | 2008-12-01 | 2009-04-22 | 浙大网新科技股份有限公司 | Method for debugging binary application program based on dynamic inverse compiling technique |
| CN105044653A (en) * | 2015-06-30 | 2015-11-11 | 武汉大学 | A software consistency detection method for smart meters |
| CN105630678A (en) * | 2015-12-22 | 2016-06-01 | 国网天津市电力公司 | Intelligent ammeter software reliability detector and detection method for intelligent ammeter software reliability |
-
2017
- 2017-07-25 CN CN201710609948.0A patent/CN107402799B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004252807A (en) * | 2003-02-21 | 2004-09-09 | Matsushita Electric Ind Co Ltd | Software development support equipment |
| CN101414278A (en) * | 2008-12-01 | 2009-04-22 | 浙大网新科技股份有限公司 | Method for debugging binary application program based on dynamic inverse compiling technique |
| CN105044653A (en) * | 2015-06-30 | 2015-11-11 | 武汉大学 | A software consistency detection method for smart meters |
| CN105630678A (en) * | 2015-12-22 | 2016-06-01 | 国网天津市电力公司 | Intelligent ammeter software reliability detector and detection method for intelligent ammeter software reliability |
Non-Patent Citations (1)
| Title |
|---|
| 邢文峰: ""RISC/DSP系统仿真器的研究"", 《中国优秀博硕士学位论文全文数据库(硕士) 信息科技辑》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109992516A (en) * | 2019-04-03 | 2019-07-09 | 北京中科寒武纪科技有限公司 | A kind of detail programming method, apparatus and Related product |
| CN109992516B (en) * | 2019-04-03 | 2022-08-26 | 寒武纪(西安)集成电路有限公司 | Programming debugging method and device and related product |
| CN110825386A (en) * | 2019-11-01 | 2020-02-21 | 腾讯科技（深圳）有限公司 | Code compiling method and device and storage medium |
| CN110825386B (en) * | 2019-11-01 | 2023-07-14 | 腾讯科技（深圳）有限公司 | Code compiling method and device and storage medium |
| CN114035767A (en) * | 2021-08-27 | 2022-02-11 | 常熟理工学院 | TEC-XP16 combined logic controller instruction design method |
| CN114035767B (en) * | 2021-08-27 | 2024-07-09 | 常熟理工学院 | Instruction design method for TEC-XP16 combinational logic controller |
| CN119883373A (en) * | 2025-03-25 | 2025-04-25 | 飞腾信息技术有限公司 | Real vector operation processing method, device, equipment and storage medium |
| CN119883373B (en) * | 2025-03-25 | 2025-07-04 | 飞腾信息技术有限公司 | Real vector operation processing method, device, equipment and storage medium |
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