CN107404353B - FPGA-based LiFi signal modulation method and modulator - Google Patents
FPGA-based LiFi signal modulation method and modulator Download PDFInfo
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- H—ELECTRICITY
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- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/11—Arrangements specific to free-space transmission, i.e. transmission through air or vacuum
- H04B10/114—Indoor or close-range type systems
- H04B10/116—Visible light communication
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- H—ELECTRICITY
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- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/50—Transmitters
- H04B10/516—Details of coding or modulation
- H04B10/548—Phase or frequency modulation
- H04B10/556—Digital modulation, e.g. differential phase shift keying [DPSK] or frequency shift keying [FSK]
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Abstract
The invention relates to a Field Programmable Gate Array (FPGA) -based LiFi signal modulation method and a modulator, wherein the method comprises the following steps: inputting 8-bit data in parallel at a frequency f0, wherein each bit of data is binary 1 or binary 0; judging whether the input data is binary 1 or binary 0, if the input data is binary 1, gating to output a second carrier wave with the frequency of f2, and if the input data is binary 0, gating to output a first carrier wave with the frequency of f 1; the carrier wave with the frequency f1 is obtained by dividing the clock excitation source fc by N, the carrier wave with the frequency f2 is obtained by dividing the clock excitation source fc by 2N, and the frequency f0 is equal to the frequency f 2. The modulation method and the modulator provided by the embodiment of the invention can ensure that the light can keep a normal lighting function no matter whether data transmission exists or not and no matter what data is transmitted.
Description
Technical Field
The invention relates to the technical field of signal modulation and demodulation, in particular to a Field Programmable Gate Array (FPGA) -based LiFi signal modulation method and a modulator.
Background
The method adopts a visible Light Fidelity (LiFi) technology to solve the problem of multipoint signal access, can realize simultaneous access of multiple computers to the local area network and simultaneously transmit data, has the characteristics of resisting radio interference, not requiring application of a radio frequency spectrum, correctly receiving data under the condition that clocks at the receiving end and the transmitting end are not synchronous, and is economical and applicable, is a novel technology for accessing multiple PC terminals to the local area network, and is in a research and development stage at home and abroad.
The LiFi technology is a communication mode which takes modulated LED light as a data transmission carrier and can simultaneously solve the problems of indoor lighting illumination and data transmission. Because the lighting requirement of the lamp light is firstly solved, for the data to be transmitted which is not processed, the lamp light is extinguished when no data is transmitted or a 0 signal is transmitted. Therefore, the signal to be transmitted needs to be coded by using the multi-point access transmission mode of the LiFi technology, and the code type can ensure that the light can keep a normal lighting function no matter whether data transmission exists or not and no matter what data is transmitted.
Disclosure of Invention
The invention aims to provide a Field Programmable Gate Array (FPGA) -based LiFi signal modulation method and a modulator.
In order to achieve the above object, the embodiments of the present invention provide the following technical solutions:
a Field Programmable Gate Array (FPGA) -based LiFi signal modulation method comprises the following steps:
inputting 8-bit data in parallel at a frequency f0, wherein each bit of data is binary 1 or binary 0;
0/1 the decision unit judges whether the input data is binary 1 or binary 0, if it is binary 1, the second carrier wave with the output frequency of f2 is gated, if it is binary 0, the first carrier wave with the output frequency of f1 is gated;
the carrier wave with the frequency f1 is obtained by dividing the clock excitation source fc by N, the carrier wave with the frequency f2 is obtained by dividing the clock excitation source fc by 2N, and the frequency f0 is equal to the frequency f 2.
In the modulation method, the input data is binary 0 or binary 1 all the time, and the line always transmits high-level signals for a long time when the data is not sent, so that the normal illumination of the lamplight can be ensured no matter whether the data transmission exists or not and no matter what data is transmitted. And f0, f2, f1/2, f0, f2, f1/2 and the receiving sampling frequency fs 8f0 are sent, and sampling at 3/8 of a T0 period can be carried out before accurate decision output. At this time, at the midpoint of 2/8-4/8 periods of the T0 cycle, f1 is in the low level section of the second half of the 1 st cycle, and f2 is in the high level section of the second half of the first half of the cycle. The transmit and receive front and back error times at 3/8T0 are constant at one fs period level. If the clock signal is low, the clock signal can be judged to be 1, if the clock signal is high, the clock signal can be judged to be 0, so that the 0/1 output judgment sampling unit can correctly judge signals of 1 and 0, further, the data can be correctly received under the condition that the system clocks at the transmitting end and the receiving end are not synchronous, and the cost increase and the technical complexity caused by synchronous clock extraction in the traditional receiving circuit are eliminated.
According to an embodiment of the present invention, the method further includes: the data transmission method is characterized in that 8-bit data input in parallel is used as one frame, a start flag bit is added at the beginning of each frame of data and is represented by two f1 periods, and a high level with the duration of T0 is sent after one frame of data is ended to represent the end of one frame of data, and 2FSK signals with two frequencies of f1 and f2 are sent during data transmission. By setting the start mark and the end mark, 8-bit data in each frame can be separated from other frames, and data interpretation errors caused by mixing of multi-frame data are avoided.
An FPGA-based LiFi signal modulator, comprising:
an input buffer for buffering 8-bit data input in parallel at a frequency f0/10, each bit data being a binary 1 or a binary 0;
a clock excitation source for generating an oscillation frequency having a frequency fc;
the frequency divider is used for respectively carrying out N frequency division and 2N frequency division on the oscillation frequency with the frequency fc to obtain a first carrier with the frequency of f1 and a second carrier with the frequency of f 2;
0/1 decision unit, used for judging whether the input data is binary 1 or binary 0, if it is binary 1, gating the second carrier wave whose output frequency is f2, if it is binary 0, gating the first carrier wave whose output frequency is f 1;
and the 8-bit counter is used for controlling the serial output of the parallelly input 8-bit data to the 0/1 decision unit, and has the counting frequency of f 0.
Compared with the prior art, the invention has the beneficial effects that: the modulation method and the modulator provided by the embodiment of the invention can represent 0 and 1 by two different frequencies, so that a signal with one frequency can be transmitted under the condition that the transmission signal is continuously 0, and the LED light is not extinguished. By setting the starting zone bit and the ending zone bit, the receiving end can correctly and continuously receive the 2FSK signals transmitted by the modulator. The method can also ensure that the data is correctly received under the condition that the clocks of the receiving and transmitting end systems are not synchronous, and the cost increase and the technical complexity caused by the extraction of the synchronous clock in the traditional receiving circuit are eliminated, so that the data transmission by utilizing the light becomes possible, and the data transmission is safe, reliable and quicker. In addition, the demodulation method and the demodulator provided by the embodiment of the invention are realized based on the FPGA, the operation speed is higher, and the reliability is high.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of an FPGA-based LiFi signal modulator according to an embodiment of the present invention.
Fig. 2 shows a 2FSK modulated data transmission format for LiFi signaling.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-2, the present embodiment provides an FPGA-based LiFi signal modulator, including:
an input buffer for buffering 8-bit data input in parallel at a frequency f0, each bit data being a binary 1 or a binary 0;
a clock excitation source for generating an oscillation frequency having a frequency fc;
the frequency divider is used for respectively carrying out N frequency division and 2N frequency division on the oscillation frequency with the frequency fc to obtain a first carrier with the frequency of f1 and a second carrier with the frequency of f 2;
0/1 decision unit, used for judging whether the input data is binary 1 or binary 0, if it is binary 1, gating the second carrier wave whose output frequency is f2, if it is binary 0, gating the first carrier wave whose output frequency is f 1;
and the 8-bit counter has the counting frequency of f0 and is used for controlling the serial output of the parallelly input 8-bit data to the 0/1 judgment unit according to the position serial number of each bit data.
8 switches SW 0-SW 7 on the BASYS or other development boards can be used as the input d8xbitin of 8-bit parallel data, the BTN0 button key is used as the input of the system reset signal, and a high level reset signal is generated when the key is pressed.
An 8-bit counter i is designed to control the parallel input 8-bit data to be output in series according to the position serial number of each bit data. The count frequency should coincide with the rate at which data is sent serially, so is f 0. Thus, by outputting d8xbitin (i) to the serial port fsk2xout, an output of 8-bit parallel data to 8-bit serial data can be obtained.
When data is output serially, it is determined whether d8xbitin (i) bit "1" or "0", and if d8xbitin (i) is "1", strobe f2, fsk2xout is f2, and if d8xbitin (i) is "0", strobe f1, fsk2xout is f 1. Thereby converting the 8-bit parallel data d8xbitin into the 2FSK output signal FSK2 xout.
By way of example, the determination of the frequency of the 2FSK signal is considered to be the following elements: the data transfer rate, the transmission characteristics and cost of the optoelectronic signal receiving circuit, and the complexity of the implementation technique. Here, the optical signal is amplified using an LM324 operational amplifier, in consideration of optical signal amplification using a low-cost high-gain amplifier. The LM324 is a four-op-amp device with a differential input, so that when the signal is within 10kHz (-3dB), there is an amplification characteristic of 100dB, and after 10kHz, the amplification characteristic drops sharply, resulting in waveform distortion, and therefore, the carrier frequency setting of the transmission 2FSK signal may be selected such that f1 is 10kHz and f2 is 5 kHz. If a higher data transmission rate is required, an amplifier with a higher gain bandwidth is selected.
When the input clock is fc 100MHz, it is necessary to divide fc to obtain a square wave signal with a frequency of f 1-10 kHz, f 2-5 kHz, and f 0-1/T0-1/200 μ s-5 kHz.
There are two methods for dividing the clock fc: one is to count and divide the clock fc continuously, and the frequency fn after the division is fc/N; the other is to press 2 to the clock fcnFrequency division is carried out, and the frequency fn after frequency division is fc/2n。
When the continuous counting frequency division is adopted, an arbitrary frequency division f1 is obtained by setting a parameter N, N is fc/f1 is 100MHz/10kHz is 10000, N is an arbitrary positive integer, high level 1 is output at N/2 clock cycles Tc time, and low level 0 is output at N/2 Tc time at the transmitting end. When f1 is 10kHz, N is 10000, i.e. f1 is 100MHz/10000 is 10 kHz.
When the receiving end identifies the carriers f1 and f2 in the 2FSK signal, at least 2 pulses of f1 carriers and 1 pulse of f2 should be received in the set per-bit data transmission time T0, and based on the transmission rate, the receiving is performed by receiving 2 pulses of f1 carriers and 1 pulse of f2 in the per-bit data transmission time T0, that is, if f1 is 10kHz, f2 is 5kHz, if f0 is 1/T0 is 5kHz, then there are cases where f2 is 5kHz
So that the transmission rate Rb of the baseband data,
the 2FSK signal is transmitted in 8 bits as a frame when transmitted. In order to allow the receiving end to correctly distinguish signals of each frame during continuous transmission, in the above modulation method, when 2FSK signals are transmitted, 8-bit data input in parallel is one frame, and a start flag bit is added at the beginning of each frame of data, and represented by two f1 cycles. A high level of time duration T0 is sent after the end of a frame to indicate the end of a frame. Thus, a data frame occupies 10T 0 cycles in real time. By setting the start mark and the end mark of the data frame, 8-bit data in each frame can be separated from other frames, and data interpretation errors caused by mixing of multi-frame data are avoided.
In the modulator, the input data is binary 0 or binary 1, and the line always transmits high level signals for a long time when the data is not sent, so that the normal illumination of the lamp light can be ensured no matter whether the data is transmitted or not and no matter what data is transmitted. And f0, f2, f1/2, f0, f2, f1/2 and the receiving sampling frequency fs 8f0 are sent, and sampling at 3/8 of a T0 period can be carried out before accurate decision output. At this time, at the midpoint of 2/8-4/8 periods of the T0 cycle, f1 is in the low level section of the second half of the 1 st cycle, and f2 is in the high level section of the second half of the first half of the cycle. The transmit and receive front and back error times at 3/8T0 are constant at one fs period level. If the clock signal is low, the clock signal can be judged to be 1, if the clock signal is high, the clock signal can be judged to be 0, so that the 0/1 output judgment sampling unit can correctly judge signals of 1 and 0, further, the data can be correctly received under the condition that the system clocks at the transmitting end and the receiving end are not synchronous, and the cost increase and the technical complexity caused by synchronous clock extraction in the traditional receiving circuit are eliminated.
In addition, by setting f 0-f 2-f 1/2, the transmission rate can be made to be the most efficient. Specifically, the clock frequency generated by the circuit board crystal oscillator is fc, but the actually transmitted frequency is different according to needs, the actually required transmission rate is f0, or 1-bit data is transmitted every T0 time, so that f0 is obtained by dividing fc, the multiple of frequency division is 2N, that is, f0 is fc/2N, that is, fc is divided by 2N, and the data transmission rate can be adjusted by adjusting the size of N. Since "1" is transmitted by the carrier f1 and "0" is transmitted by the carrier f2, when the counter is received at the receiving end, it is recognized that "1" is received by 2 pulses received when f1 is received by the counter, and it is determined that digital "0" is received by 1 pulse received when f2 is received, so that T2 is 2T1, or f1 is 2f 2. Here, f0 is f2 is f1/2, f0 is fc/2N, f0 is f2 is 2f1, f2 is fc/2N, and f1 is fc/N.
Correspondingly, the modulation method which can be realized based on the modulator comprises the following steps:
8-bit data, each of which is binary 1 or binary 0, is input in parallel at a frequency f 0/10.
Judging whether the input data is binary 1 or binary 0, if the input data is binary 1, gating to output a second carrier wave with the frequency of f2, and if the input data is binary 0, gating to output a first carrier wave with the frequency of f 1;
the carrier wave with the frequency f1 is obtained by dividing the clock excitation source fc by N, the carrier wave with the frequency f2 is obtained by dividing the clock excitation source fc by 2N, and the frequency f0 is equal to the frequency f 2.
In the method, 8-bit data input in parallel is taken as one frame, a start flag bit is added at the beginning of each frame of data, two f1 periods are used for representing, a high level of T0 duration is sent after one frame of data is finished, and a 2FSK signal of 0/1 signals input at two frequencies of f1 and f2 is sent during data transmission.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention.
Claims (2)
1. A Field Programmable Gate Array (FPGA) -based LiFi signal modulation method is characterized by comprising the following steps:
inputting 8-bit data in parallel at a frequency f0, wherein each bit of data is binary 1 or binary 0; the 8-bit data is a frame, a starting marker bit is added at the beginning of each frame of data and is represented by two f1 periods, and a high level with the time length of T0 is sent after one frame of data is ended to represent the end of one frame of data;
0/1 the decision unit samples at 3T0/8, judges whether the input data is binary 1 or binary 0, if it is binary 1, the second carrier wave with frequency f2 is gated and output, if it is binary 0, the first carrier wave with frequency f1 is gated and output;
the carrier wave with the frequency f1 is obtained by dividing the clock excitation source fc by N, the carrier wave with the frequency f2 is obtained by dividing the clock excitation source fc by 2N, and the frequency f0 is equal to the frequency f 2.
2. An FPGA-based LiFi signal modulator, comprising:
an input buffer for buffering 8-bit data input in parallel at a frequency f0/10, each bit data being a binary 1 or a binary 0;
an 8-bit counter with a count frequency of f0 for controlling serial output of 8-bit data inputted in parallel to 0/1
A decision unit; the 8-bit data is a frame, a starting marker bit is added at the beginning of each frame of data and is represented by two f1 periods, and a high level with the time length of T0 is sent after one frame of data is ended to represent the end of one frame of data;
0/1 decision unit, for sampling at 3T0/8, judging whether the input data is binary 1 or binary 0, if it is binary 1, gating the second carrier wave with frequency f2, if it is binary 0, gating the first carrier wave with frequency f 1;
a clock excitation source for generating an oscillation frequency having a frequency fc;
a frequency divider for dividing the oscillation frequency of fc by N and 2N respectively to obtain the frequency of fc
A first carrier of f1, a second carrier of frequency f 2.
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| CN102984106B (en) * | 2012-12-18 | 2015-03-04 | 天津光电通信技术有限公司 | Binary frequency shift keying modulation system |
| CN105072069B (en) * | 2015-08-07 | 2018-07-31 | 株洲南车时代电气股份有限公司 | A kind of FSK modulation circuit |
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