CN107393964A - A kind of high-performance FINFET device and preparation method thereof - Google Patents
A kind of high-performance FINFET device and preparation method thereof Download PDFInfo
- Publication number
- CN107393964A CN107393964A CN201710523018.3A CN201710523018A CN107393964A CN 107393964 A CN107393964 A CN 107393964A CN 201710523018 A CN201710523018 A CN 201710523018A CN 107393964 A CN107393964 A CN 107393964A
- Authority
- CN
- China
- Prior art keywords
- fin
- finfet device
- semiconductor substrate
- preparation
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 11
- 239000010703 silicon Substances 0.000 abstract description 11
- 238000000427 thin-film deposition Methods 0.000 abstract 1
- 230000005669 field effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a kind of high-performance FINFET device and preparation method thereof, circulated using the multiplicating of isotropic etching thin film deposition anisotropic etching, multiple arcs groove is formed in silicon fin side wall, so as to improve the length of silicon fin, W/L is proportional to according to driving current, W is silicon fin length, L is grid length, because W increases, therefore, the driving current of FINFET device is increased.Further, by carrying out ion implanting to Semiconductor substrate, using cvd dielectric layer in groove, after next groove is etched, dielectric layer is all removed, so as to reduce the width of fin, improves the arrangement density of the fin on substrate, the grid length L on single fin is reduced, further improves driving current.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of high-performance FINFET device and preparation method thereof.
Background technology
With the continuous development of semiconductor technology, gate oxide thickness, exhaust layer depth, channel length constantly reduces, short
Channelling effect because its drain-induced barrier reduces, degenerate all the more obvious by subthreshold behavior.Traditional plane MOSFET is partly being led
Body technique development encounters unprecedented difficulty.Fin formula field effect transistor (Fin Field Effect Transistor,
FINFET short-channel effect, furthermore its manufacture craft and traditional planar channeling gold) restrained effectively by the structure of multiple-grid
The manufacture craft compatibility of category-oxide semiconductor field effect transistor is good, is increasingly becoming the device architecture of main flow.
Generally, excellent FINFET device needs to have higher grid control ability, current driving ability and suppressed short
The ability of channelling effect.Therefore, the driving current for improving FINFET device is to obtain the effective means of high-performance FINFET device
One of.
The content of the invention
In order to overcome problem above, the present invention is intended to provide a kind of high-performance FINFET device and preparation method thereof, is utilized
Silicon fin side wall forms multiple arcs groove, to improve FINFET driving current.
In order to achieve the above object, the invention provides a kind of FINFET device, the fin side wall of FINFET device is with more
Individual arc groove so that the grid and the contact interface of fin being covered on fin are in multiple arcs therewith.
Preferably, the arc groove of the fin side wall is hemispherical.
Preferably, it is raised that tip is formed between the adjacent arc groove.
Preferably, the material of the fin is monocrystalline silicon.
In order to achieve the above object, present invention also offers a kind of preparation method of FINFET device, it includes：
Step 01：Semi-conductive substrate is provided；
Step 02：Using isotropic etching, etch semiconductor substrates, there is arc so as to be formed in the semiconductor substrate
At least two grooves of side wall；
Step 03：Dielectric layer is formed in trenched side-wall and bottom and semiconductor substrate surface；
Step 04：Using anisotropic etching, the dielectric layer of channel bottom is removed；
Step 05：Using isotropic etching, continue etching downwards from channel bottom, so as in the semiconductor of channel bottom
Another groove with curved wall is formed in substrate；
Step 06：Repeat step 03~05, so as to form the fin with multiple arcs recess sidewall in the semiconductor substrate.
Preferably, in the step 04, in addition to, continue to use anisotropic etching certain depth downwards, it is vertical to be formed
Side wall.In the step 06, repeat step 03~05, it is located at arc so as to be formed on the fin with multiple arcs recess sidewall
Upright side walls between groove.
Preferably, in the step 03, dielectric layer is formed by gas-phase deposition.
Preferably, the dielectric layer formed is oxide film, in the step 01, in addition to：Semiconductor substrate is carried out
Ion implanting, form the Semiconductor substrate with doping type.
Preferably, in the step 04, during anisotropic etching, using plasma etching and Semiconductor substrate table
The vertical all faces in face.
Preferably, after the step 04 and before the step 05, in addition to：Remove all remaining media
Layer.
A kind of high-performance FINFET device of the present invention and preparation method thereof, sinks by using isotropic etching-film
The multiplicating circulation of product-anisotropic etching, forms multiple arcs groove, so as to improve the length of silicon fin in silicon fin side wall
Degree, W/L is proportional to according to driving current, and W is silicon fin length, and L is grid length, because W increases, therefore, FINFET device
Driving current is increased.Further, using cvd dielectric layer in groove, after next groove is etched, will be situated between
Matter layer all removes, and so as to reduce the width of fin, improves the arrangement density of the fin on substrate, reduces the grid length on single fin
L, further improve driving current.
Brief description of the drawings
Fig. 1 is the structural representation of the FINFET device of the preferred embodiment of the present invention
Fig. 2 is the structural representation of the FINFET device of the preferred embodiment of the present invention
Fig. 3 is the schematic flow sheet of the preparation method of the FINFET device of the preferred embodiment of the present invention
Fig. 4~9 are each step schematic diagram of the preparation method of Fig. 3 FINFET device
Embodiment
To make present disclosure more clear understandable, below in conjunction with Figure of description, present disclosure is made into one
Walk explanation.Certainly the invention is not limited in the specific embodiment, the general replacement known to those skilled in the art
Cover within the scope of the present invention.
The present invention is described in further detail below in conjunction with 1~9 and specific embodiment.It should be noted that accompanying drawing is adopted
With very simplified form, using non-accurately ratio, and only to it is convenient, clearly reach and aid in illustrating the mesh of the present embodiment
's.
Referring to Fig. 1, the FINFET device of the present embodiment is located in Semiconductor substrate 00, the fin side wall tool of FINFET device
There is multiple arcs recess sidewall 02 so that the grid and the contact interface of fin being covered on fin are in multiple arcs therewith.Preferably,
The arc groove side wall 02 of fin side wall is hemispherical.The perpendicular of certain interval can be set between adjacent arc groove side wall 02
Straight sidewall, as shown in figure 1, can also set without interval, so that forming point between adjacent arc groove side wall 02
End is raised, as shown in Figure 2.In the present embodiment, the material of fin can be adopted as monocrystalline silicon.
In addition, referring to Fig. 3, a kind of preparation method of FINFET device of the present embodiment includes：
Step 01：Referring to Fig. 4, provide semi-conductive substrate 00；
Specifically, Semiconductor substrate 00 can be, but not limited to use monocrystalline substrate.It can be, but not limited to serve as a contrast semiconductor
Bottom 00 carries out ion implanting, so that Semiconductor substrate 00 has a doping type, for example, p-type or N-type.
Step 02：Referring to Fig. 5, using isotropic etching, etch semiconductor substrates 00, so as in Semiconductor substrate 00
It is middle to form at least two groove G1 with arc groove side wall 02；
Specifically, isotropic etching using plasma dry etching or wet corrosion technique.Due to groove G1 it
Between form silicon fin, therefore, the groove G1 at least two of required formation, so as to form at least one silicon fin.The material of fin can be with
It is identical with Semiconductor substrate 00, such as monocrystalline silicon, it can also differ.
Step 03：Referring to Fig. 6, form dielectric layer J in groove G1 side walls and bottom and the surface of Semiconductor substrate 00；
Specifically, can be, but not limited to be preferably come metallization medium layer J, dielectric layer J using chemical vapor deposition method
Oxide film, it is here silica membrane.
Step 04：Referring to Fig. 7, using anisotropic etching, the dielectric layer J of removal groove G1 bottoms；
Specifically, during anisotropic etching, it can be etched with using plasma and be put down with the surface of Semiconductor substrate 00
Capable all faces.
In the present embodiment, after step 04 and before step 05, in addition to：All remaining dielectric layers are removed, from
And reduce the width of silicon fin, increase the arrangement density of silicon fin.
Step 05：Referring to Fig. 8, using isotropic etching, continue etching downwards from groove G1 bottoms, so as in groove
Another groove G2 with arc groove side wall 02 is formed in the Semiconductor substrate 00 of G1 bottoms；
Step 06：Referring to Fig. 9, repeat step 03~05, has multiple arcs so as to be formed in Semiconductor substrate 00
The fin of recess sidewall 02.
Specifically, in the fin with multiple arcs recess sidewall 02 obtained, the end of arc groove side wall 02 is connected, from
And tip is formed between adjacent arc groove side wall 02.
It should be noted that in step 04, have to obtain between the arc groove of the side wall for the fin for making finally to obtain
The upright side walls of certain altitude, after the dielectric layer of channel bottom is removed, it can also continue to use anisotropic etching one downwards
Depthkeeping degree, form upright side walls.
So, repeat step 03~05 in step 06, so that the multiple fins with arc groove side wall formed
On arc groove between upright side walls, as shown in Figure 1.
Although the present invention is disclosed as above with preferred embodiment, right embodiment is illustrated only for the purposes of explanation, and
Be not used to limit the present invention, those skilled in the art can make without departing from the spirit and scope of the present invention it is some more
Dynamic and retouching, the protection domain that the present invention is advocated should be defined by claims.
Claims (10)
1. a kind of FINFET device, it is characterised in that the fin side wall of FINFET device has multiple arcs groove so that is covered in
The contact interface of grid and fin on fin is in multiple arcs therewith.
2. FINFET device according to claim 1, it is characterised in that the arc groove of the fin side wall is hemispherical.
3. FINFET device according to claim 1, it is characterised in that tip is formed between the adjacent arc groove
It is raised.
4. FINFET device according to claim 1, it is characterised in that the material of the fin is monocrystalline silicon.
A kind of 5. preparation method of FINFET device, it is characterised in that including：
Step 01：Semi-conductive substrate is provided；
Step 02：Using isotropic etching, etch semiconductor substrates, there is curved wall so as to be formed in the semiconductor substrate
At least two grooves；
Step 03：Dielectric layer is formed in trenched side-wall and bottom and semiconductor substrate surface；
Step 04：Using anisotropic etching, the dielectric layer of channel bottom is removed；
Step 05：Using isotropic etching, continue etching downwards from channel bottom, so as in the Semiconductor substrate of channel bottom
It is middle to form another groove with curved wall；
Step 06：Repeat step 03~05, so as to form the fin with multiple arcs recess sidewall in the semiconductor substrate.
6. preparation method according to claim 5, it is characterised in that in the step 04, in addition to, continue to use downwards
Anisotropic etching certain depth, form upright side walls.In the step 06, repeat step 03~05, so as to multiple
The upright side walls between arc groove are formed on the fin of arc groove side wall.
7. preparation method according to claim 5, it is characterised in that in the step 03, dielectric layer is formed by gas
Phase depositing operation.
8. preparation method according to claim 5, it is characterised in that the dielectric layer formed is oxide film, the step
In rapid 01, in addition to：Ion implanting is carried out to Semiconductor substrate, forms the Semiconductor substrate with doping type.
9. preparation method according to claim 5, it is characterised in that in the step 04, during anisotropic etching,
Using plasma etches all faces vertical with semiconductor substrate surface.
10. preparation method according to claim 5, it is characterised in that after the step 04 and the step 05 it
Before, in addition to：Remove all remaining dielectric layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710523018.3A CN107393964B (en) | 2017-06-30 | 2017-06-30 | High-performance FINFET device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710523018.3A CN107393964B (en) | 2017-06-30 | 2017-06-30 | High-performance FINFET device and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107393964A true CN107393964A (en) | 2017-11-24 |
| CN107393964B CN107393964B (en) | 2020-10-02 |
Family
ID=60334856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710523018.3A Active CN107393964B (en) | 2017-06-30 | 2017-06-30 | High-performance FINFET device and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107393964B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070231997A1 (en) * | 2006-03-31 | 2007-10-04 | Doyle Brian S | Stacked multi-gate transistor design and method of fabrication |
| CN102446972A (en) * | 2010-10-08 | 2012-05-09 | 台湾积体电路制造股份有限公司 | Transistor having notched fin structure and method of fabricating the same |
| CN104078324A (en) * | 2013-03-29 | 2014-10-01 | 中国科学院微电子研究所 | Stacked nanowire fabrication method |
| CN104282559A (en) * | 2013-07-02 | 2015-01-14 | 中国科学院微电子研究所 | Stacked nanowire MOS transistor and manufacturing method thereof |
| CN104779283A (en) * | 2014-01-09 | 2015-07-15 | 中芯国际集成电路制造(上海)有限公司 | FINFET device capable of enhancing gate control and current drive and manufacturing method |
-
2017
- 2017-06-30 CN CN201710523018.3A patent/CN107393964B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070231997A1 (en) * | 2006-03-31 | 2007-10-04 | Doyle Brian S | Stacked multi-gate transistor design and method of fabrication |
| CN102446972A (en) * | 2010-10-08 | 2012-05-09 | 台湾积体电路制造股份有限公司 | Transistor having notched fin structure and method of fabricating the same |
| CN104078324A (en) * | 2013-03-29 | 2014-10-01 | 中国科学院微电子研究所 | Stacked nanowire fabrication method |
| CN104282559A (en) * | 2013-07-02 | 2015-01-14 | 中国科学院微电子研究所 | Stacked nanowire MOS transistor and manufacturing method thereof |
| CN104779283A (en) * | 2014-01-09 | 2015-07-15 | 中芯国际集成电路制造(上海)有限公司 | FINFET device capable of enhancing gate control and current drive and manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107393964B (en) | 2020-10-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI544529B (en) | Finfet device and method for manufacturing the same | |
| CN104795332B (en) | The forming method of fin formula field effect transistor | |
| KR102067171B1 (en) | A semiconductor device and method of fabricating the same | |
| CN104347421A (en) | Method for forming finned field-effect transistor (FET) | |
| CN103579074B (en) | The forming method of semiconductor structure | |
| CN104217998B (en) | The method that integrated circuit and manufacture have the integrated circuit of cladding non-planar transistor structure | |
| CN103295902A (en) | Finned field-effect tube and forming method thereof | |
| US9076870B2 (en) | Method for forming fin-shaped structure | |
| CN104347409B (en) | The forming method of semiconductor structure | |
| CN104425264B (en) | The forming method of semiconductor structure | |
| CN104425263B (en) | The forming method of semiconductor structure | |
| CN109585379A (en) | Semiconductor devices and forming method thereof | |
| CN105576024B (en) | Semiconductor structure and forming method thereof | |
| CN107045979B (en) | The forming method of semiconductor structure | |
| CN103855021A (en) | Manufacturing method for FinFET device | |
| CN108155149A (en) | The forming method and semiconductor structure of fin field effect pipe | |
| CN103578995B (en) | Form the method for FinFET | |
| CN107393964A (en) | A kind of high-performance FINFET device and preparation method thereof | |
| CN104425277B (en) | The forming method of transistor | |
| CN103531476A (en) | Semiconductor device manufacturing method | |
| CN102129982A (en) | Manufacturing method of fine pattern of semiconductor and FIN body of fin type field effect transistor | |
| CN108155241B (en) | Anti-irradiation multi-gate device and preparation method thereof | |
| CN109148294B (en) | Semiconductor structure and forming method thereof | |
| CN104143514B (en) | The forming method of multiple gate field effect transistor | |
| CN104157573A (en) | Preparation method for FinFET structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |