CN107370488A - Error correction/encoding method and device - Google Patents
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Abstract
The invention provides a kind of error correction/encoding method and device, wherein, this method includes：The bit sequence for treating Error Correction of Coding to first is segmented；To the part or all of bit sequence fragment after segmentation, error checking and correction coding is carried out respectively；Each bit sequence fragment composition second after error checking and correction is encoded treats the bit sequence of Error Correction of Coding, and treats that error correcting code bits sequence carries out forward error correction coding to described second, generates bit sequence to be sent；Send the bit sequence to be sent.By the present invention, solve the problems, such as the error correction coding scheme error correcting capability deficiency in correlation technique, reduce the code check of true form word, decoding performance can be improved.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to an error correction coding method and apparatus.
Background
A digital communication system generally includes a transmitting end, a source encoder, a channel encoder, a modulator, and the like, and a receiving end, a demodulator, a channel decoder, a source decoder, and a sink, as shown in fig. 1, which is a schematic diagram of a digital communication system according to the related art. The channel encoder is used for introducing redundant information to information bits according to a certain rule so that a receiving end channel decoder can correct bit errors generated when the information is transmitted on a channel to a certain extent.
Common channel coding methods include bit xor coding, block coding, BCH coding, reed-solomon (RS) coding, fountain coding, low density parity check (ldpc) coding, Turbo coding, polar coding, convolutional coding, and the like; the unnecessary channel coding method usually has different applicable scenes and different coding and decoding performances. Sometimes, special optimization of these channel coding methods is required to improve the performance of channel coding.
A more typical application scenario requiring an increase in channel coding/decoding performance is an ultra-reliable application in mobile communications. The ultra-reliable application generally comprises application scenes with high requirements on data transmission reliability, such as vehicle networking and industrial control. Ultra-reliable applications generally have two characteristics: 1) the error rate of the data blocks of the ultra-reliable data transmission must be 4 to 5 orders of magnitude lower than the block error rate of the normal data transmission; 2) the length of the data block is usually not long, generally below 1000 bits, and it is difficult for the conventional channel coding method to obtain sufficient coding gain.
The LDPC code is a linear block code based on a sparse check matrix, and low-complexity coding and decoding can be realized by using the sparsity of the check matrix, so that the LDPC code is practical. The aforementioned Gallager code is a regular LDPC code (regular LDPC pc), and Luby and Mitzenmacher et al have generalized the Gallager code to propose an irregular LDPC code (irregular LDPC pc). The LDPC code has many decoding algorithms, wherein an information transfer algorithm (Message paging algorithm) or a Belief Propagation algorithm (BP algorithm) is a mainstream and basic algorithm of the LDPC code, and many improved effective decoding algorithms are currently developed.
The graphical representation of the LDPC parity check matrix is a bipartite graph. The bipartite graph and the check matrix have a one-to-one correspondence relationship, and an M-by-N parity check matrix H defines that each codeword with N bits satisfies M parity checksConstraint of the set. A bipartite graph includes N variable nodes and M parity nodes. When the m-th check involves the n-th bit, i.e. the element H in the m-th row and n-th column of Hm，nWhen 1, there will be one connection line connecting the check node m and the variable node n. In the bipartite graph, any node of the same class cannot be connected, and the total number of edges in the bipartite graph is equal to the number of non-zero elements in the check matrix.
One class of special LDPC codes is becoming mainstream applications due to their structured nature. The parity check matrix H of the LDPC code is an (M × z) × (N × z) matrix, which is formed by M × N block matrices, each block matrix is a different power of a basic permutation matrix of z × z, and when the basic permutation matrix is a unit matrix, they are cyclic shift matrices of the unit matrix (the text defaults to right shift). Having the form:
if it is not
If it is notIs an integer greater than or equal to 0, is definedWhere P is a standard permutation matrix of z × z, as follows:
by such powersEach can be uniquely identifiedThe power of the blocking matrix can be represented by 0 and the matrix can be represented by-1, thus, if each blocking matrix of H is replaced by its power, a power matrix H of M × N is obtainedb. Here, definition HbIs the basis matrix of H, H being called HbThe spreading matrix of (2). In actual encoding, z is the code length/number of columns of the base matrix N, and is referred to as the spreading factor.
For example, a matrix
The following parameter z and a base matrix H of 2 × 4 may be usedbExpanding to obtain:
z is 3 and
therefore, it can also be said that the encoder of the LDPC code is composed of the basic matrix HbThe spreading factor z and the selected basic permutation matrix are uniquely generated.
The basic check matrix of the LDPC code can also be written as follows:
wherein,is the systematic bit portion of the base check matrix,there are a series of Kb's,is the parity bit portion of the base check matrix,there are Mb columns. Where Kb is a positive integer and Kb-Mb, where Nb is the number of columns of the basic check matrix of the low density parity check code and Mb is the number of rows of the basic check matrix of the low density parity check code; in the system bit and check bit portions of the basic check matrix, the column weights of the columns may be the same or different. The weight refers to the number of non-zero elements (or non-1 elements) in the column.
For the problem of insufficient error correction capability of the error correction coding scheme in the related art, no solution is provided at present.
Disclosure of Invention
The embodiment of the invention provides an error correction coding method and device, which at least solve the problem of insufficient error correction capability of an error correction coding scheme in the related art.
According to an embodiment of the present invention, there is provided an error correction encoding method including: segmenting a first bit sequence to be error-correction coded; respectively carrying out error check coding on part or all of the segmented bit sequence segments; forming each bit sequence segment after error check coding into a second bit sequence to be error correction coded, and carrying out forward error correction coding on the second bit sequence to be error correction coded to generate a bit sequence to be transmitted; and transmitting the bit sequence to be transmitted.
Optionally, the first bit sequence to be error-corrected comprises at least one of: a sequence of information bits; and carrying out error check coding on the whole information bit sequence.
Optionally, the error checking encoding comprises at least one of: cyclic redundancy check coding, BCH code coding, RS code coding and parity check coding.
Optionally, segmenting the first bit sequence to be error correction encoded comprises: and uniformly or non-uniformly segmenting the bit sequence to be coded according to the number of preset bit sequence segments or the length of the bit sequence segments.
Optionally, the forming, by the bit sequence segments after the error check coding, a second bit sequence to be coded with error correction, and performing forward error correction coding on the second bit sequence to be coded with error correction, and the generating a bit sequence to be transmitted includes: firstly, carrying out forward error correction coding on each information bit sequence consisting of bits at corresponding positions in each bit sequence segment after error check coding to obtain respective check bit sequence; forming a new bit sequence segment by using bits at corresponding positions in each check bit sequence; and synthesizing each bit sequence segment after the original error check coding and the new bit sequence segment into a third bit sequence to be error correction coded, and carrying out forward error correction coding on the third bit sequence to be error correction coded to generate a bit sequence to be transmitted.
Optionally, the forward error correction coding comprises at least one of: bit exclusive or coding, block code coding, BCH code coding, RS code coding, fountain code coding, low density parity check code coding, Turbo code coding, polarization code coding, convolutional code coding.
Optionally, in a case that the forward error correction coding method is low density parity check code coding, segmenting the first bit sequence to be error correction coded includes: dividing a bit sequence to be coded into Kb sections, wherein Kb is a positive integer, and Kb is Nb-Mb, wherein Nb is the column number of a basic check matrix of the low-density parity check code, and Mb is the row number of the basic check matrix of the low-density parity check code; or, the segmentation is performed in units of E bits, where E is a positive integer, and E ═ z-K3, where z is a spreading factor of the low density parity check code, and K3 is a redundant bit length after error check coding is performed on a part or all of the segmented bit sequence segments, respectively.
Optionally, in a case that the forward error correction coding method is low density parity check code coding, performing error check coding on the segmented partial bit sequence segments respectively includes: selecting bit sequence fragments with the weight of the system bit part of the basic check matrix of the low-density parity check code larger than a preset threshold value from the segmented bit sequence fragments; and carrying out error check coding on the selected bit sequence segment.
According to another embodiment of the present invention, there is also provided an error correction encoding apparatus including: the device comprises a segmenting module, a coding module and a decoding module, wherein the segmenting module is used for segmenting a first bit sequence to be error-correction coded; the error check coding module is used for respectively carrying out error check coding on part or all of the bit sequence fragments after segmentation; the forward error correction coding module is used for forming each bit sequence segment after error check coding into a second bit sequence to be error correction coded, and performing forward error correction coding on the second bit sequence to be error correction coded to generate a bit sequence to be sent; and the sending module is used for sending the bit sequence to be sent.
Optionally, the segmentation module is further configured to: and uniformly or non-uniformly segmenting the bit sequence to be coded according to the number of preset bit sequence segments or the length of the bit sequence segments.
Optionally, the forward error correction coding module is further configured to: firstly, carrying out forward error correction coding on each information bit sequence consisting of bits at corresponding positions in each bit sequence segment after error check coding to obtain respective check bit sequence; forming a new bit sequence segment by using bits at corresponding positions in each check bit sequence; and synthesizing each bit sequence segment after the original error check coding and the new bit sequence segment into a third bit sequence to be error correction coded, and carrying out forward error correction coding on the third bit sequence to be error correction coded to generate a bit sequence to be transmitted.
Optionally, when the forward error correction coding method is low density parity check coding, the segmentation module is further configured to: dividing a bit sequence to be coded into Kb sections, wherein Kb is a positive integer, and Kb is Nb-Mb, wherein Nb is the column number of a basic check matrix of the low-density parity check code, and Mb is the row number of the basic check matrix of the low-density parity check code; or, the segmentation is performed in units of E bits, where E is a positive integer, and E ═ z-K3, where z is a spreading factor of the low density parity check code, and K3 is a redundant bit length after error check coding is performed on a part or all of the segmented bit sequence segments, respectively.
Optionally, when the forward error correction coding method is low density parity check coding, the error check coding module includes: a selecting unit, configured to select, from the segmented bit sequence segments, a bit sequence segment in which a weight of a system bit portion of a basic check matrix of the low-density parity-check code is greater than a preset threshold; and the error check coding unit is used for carrying out error check coding on the selected bit sequence segment.
According to still another embodiment of the present invention, there is also provided a storage medium. The storage medium is configured to store program code for performing the steps of: segmenting a first bit sequence to be error-correction coded; respectively carrying out error check coding on part or all of the segmented bit sequence segments; forming each bit sequence segment after error check coding into a second bit sequence to be error correction coded, and carrying out forward error correction coding on the second bit sequence to be error correction coded to generate a bit sequence to be transmitted; and transmitting the bit sequence to be transmitted.
By the invention, the bit sequence to be error-correction coded is segmented, the segmented bit sequence segments are respectively subjected to error check coding, and then the bit sequence segments subjected to error check coding are subjected to forward error correction coding to generate the bit sequence to be transmitted, so that a decoder can judge whether the current bit sequence segment is correct or not according to the error check code of each bit sequence segment in the decoding process, if the current bit sequence segment is correct, the decoder regards the current bit sequence segment as a definite bit and does not need to continuously decode the current bit sequence, which is equivalent to shortening code decoding, reducing the code rate of the original code word, improving the decoding performance and solving the problem of insufficient error correction capability of an error correction coding scheme in the related technology.
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The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
fig. 1 is a schematic diagram of a digital communication system according to the related art;
FIG. 2 is a flow chart of a method of error correction coding according to an embodiment of the invention;
fig. 3 is a block diagram of a structure of an error correction encoding apparatus according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating an error correction encoding process according to a first embodiment of the invention;
fig. 5 is a schematic diagram of an error correction encoding process according to a second embodiment of the invention.
Detailed Description
The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
Aiming at the characteristic of ultra-reliable application, the embodiment of the invention provides a novel error correction coding method, which increases the way of carrying out segmented coding on a bit sequence to be coded, further enhances the error correction capability of a code word and improves the coding gain.
In the present embodiment, an error correction coding method is provided, and fig. 2 is a flowchart of an error correction coding method according to an embodiment of the present invention, as shown in fig. 2, the method includes the following steps:
step S202, segmenting a first bit sequence to be error-correction coded;
step S204, error check coding is respectively carried out on part or all of the segmented bit sequence segments;
step S206, forming each bit sequence segment after error check coding into a second bit sequence to be error correction coded, and performing forward error correction coding on the second bit sequence to be error correction coded to generate a bit sequence to be transmitted;
step S208, transmitting the bit sequence to be transmitted.
In this embodiment, through the above steps, the bit sequence to be error-correction encoded is segmented, the segmented bit sequence segments are respectively error-check encoded, and then the bit sequence segments after error-check encoding are forward error-correction encoded to generate the bit sequence to be transmitted, so that the decoder can determine whether the current bit sequence segment is correct according to the error-check code of each bit sequence segment in the decoding process, and if the current bit sequence segment is correct, the decoder regards the current bit sequence segment as a definite bit and does not need to decode the current bit sequence, which is equivalent to shortening code decoding, reducing the code rate of the original codeword, improving decoding performance, and solving the problem of insufficient error-correction capability of the error-correction encoding scheme in the related art.
As a preferred implementation manner, for step S202, the coded bit sequence to be error-corrected includes an information bit sequence or a bit sequence obtained by performing overall error-checking coding on the information bit sequence; wherein the error checking code can be any code with error checking function, including but not limited to cyclic redundancy check code, BCH code, reed-solomon code (RS code) code, parity code. Similarly, the error check coding in step S204 may be any coding having an error check function, including but not limited to cyclic redundancy check coding, BCH code coding, reed-solomon code (RS code) coding, and parity coding.
As a preferred implementation manner, for step S202, the segmenting the bit sequence to be error correction coded may be: and uniformly segmenting or non-uniformly segmenting the bit sequence to be coded according to the number of preset bit sequence segments or the length of the bit sequence segments.
As a preferred embodiment, for step S206, the method may further include:
step S2062: firstly, carrying out forward error correction coding on each information bit sequence consisting of bits at corresponding positions in each bit sequence segment after error check coding to obtain respective check bit sequence; the forward error correction coding refers to coding with an error correction function, and includes but is not limited to bit exclusive or coding, block code coding, BCH code coding, reed solomon code (RS code) coding, fountain code coding, low density parity check code coding, Turbo code coding, polarization code coding, and convolutional code coding;
step S2064: bits at corresponding positions in each check bit sequence form a new bit sequence segment;
step S2066: and forming a new bit sequence to be error-correction coded by the bit sequence segments after the original error check coding and the new bit sequence segment in the step S2064, and performing forward error correction coding on the new bit sequence to be error-correction coded to generate a bit sequence to be transmitted.
As a preferred implementation manner, for step S206, the forward error correction coding may refer to coding with an error correction function, including but not limited to bit exclusive or coding, block code coding, BCH code coding, reed solomon code (RS code) coding, fountain code coding, low density parity check code coding, Turbo code coding, polarization code coding, and convolutional code coding.
Alternatively, if the forward error correction coding method is low density parity check code coding, in step a, the transmitting end divides the bit sequence to be coded into Kb segments, where Kb is a positive integer and Kb is Nb-Mb, where Nb is the number of columns of the basic check matrix of the low density parity check code and Mb is the number of rows of the basic matrix of the low density parity check code; or,
if the fec coding method is low density parity check code coding, in step a, the transmitting end performs segmentation in units of E bits, where E is a positive integer and E-z-K3, where z is a spreading factor of the low density parity check code, and K3 is a redundant bit length of each bit sequence segment after error check coding in step b.
Alternatively, in the case that the fec coding method is low density parity check code coding, the segmented partial bit sequence segments may be subjected to error check coding, for example, the partial bit sequence segments subjected to error check coding may be selected according to the systematic bit partial column weight of the basic check matrix of the low density parity check code. Specifically, a bit sequence segment whose systematic bit part weight of the basic check matrix of the low-density parity check code is greater than a preset threshold may be selected from the segmented bit sequence segments; and carrying out error check coding on the selected bit sequence segment.
Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
In this embodiment, an error correction coding apparatus is further provided, and the apparatus is used to implement the foregoing embodiments and preferred embodiments, and the description that has been already made is omitted. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
Fig. 3 is a block diagram of a structure of an error correction encoding apparatus according to an embodiment of the present invention, as shown in fig. 3, the apparatus including: a segmenting module 32, configured to segment the first bit sequence to be error-correction encoded; an error check coding module 34, configured to perform error check coding on part or all of the bit sequence segments segmented by the segmentation module 32; a forward error correction coding module 36, configured to combine each bit sequence segment after the error check coding module 34 performs error check coding into a second bit sequence to be error correction coded, and perform forward error correction coding on the second bit sequence to be error correction coded, so as to generate a bit sequence to be sent; a sending module 38, configured to send the bit sequence to be sent generated by the forward error correction coding module 36.
Optionally, the segmenting module 32 may be further configured to uniformly segment or non-uniformly segment the bit sequence to be coded according to a preset number of bit sequence segments or a length of a bit sequence segment.
Optionally, the forward error correction coding module 36 may be further configured to: firstly, carrying out forward error correction coding on each information bit sequence consisting of bits at corresponding positions in each bit sequence segment after error check coding to obtain respective check bit sequence; forming a new bit sequence segment by using bits at corresponding positions in each check bit sequence; and synthesizing each bit sequence segment after the original error check coding and the new bit sequence segment into a third bit sequence to be error correction coded, and carrying out forward error correction coding on the third bit sequence to be error correction coded to generate a bit sequence to be transmitted.
Optionally, when the forward error correction coding method is low density parity check coding, the segmentation module 32 may be further configured to: dividing a bit sequence to be coded into Kb sections, wherein Kb is a positive integer, and Kb is Nb-Mb, wherein Nb is the column number of a basic check matrix of the low-density parity check code, and Mb is the row number of the basic check matrix of the low-density parity check code; or, the segmentation is performed in units of E bits, where E is a positive integer, and E ═ z-K3, where z is a spreading factor of the low density parity check code, and K3 is a redundant bit length after error check coding is performed on a part or all of the segmented bit sequence segments, respectively.
Optionally, when the forward error correction coding method is low density parity check coding, the error check coding module may include: a selecting unit, configured to select, from the segmented bit sequence segments, a bit sequence segment in which a weight of a system bit portion of a basic check matrix of the low-density parity-check code is greater than a preset threshold; and the error check coding unit is used for carrying out error check coding on the selected bit sequence segment.
It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in different processors in any combination.
The following description is given in conjunction with the preferred embodiments, which combine the above embodiments and their preferred embodiments. In the following preferred embodiments, there is provided a method of error correction coding during data transmission, the method comprising:
a, a transmitting end segments a bit sequence to be error-correction coded;
b, respectively carrying out error check coding on each bit sequence segment after segmentation;
c, forming a new bit sequence to be error-correction coded by each bit sequence segment after error check coding, and carrying out forward error correction coding on the new bit sequence to be error-correction coded to generate a bit sequence to be transmitted;
and d, the transmitting end transmits the bit sequence to be transmitted.
Further, for step a, the coded bit sequence to be error-corrected includes an information bit sequence or a bit sequence obtained by performing overall error check coding on the information bit sequence; wherein the error check coding refers to any coding with error check function, including but not limited to cyclic redundancy check coding, BCH code coding, reed-solomon code (RS code) coding, parity check coding;
further, for step a, the segmenting the bit sequence to be error-correction coded means uniformly segmenting or non-uniformly segmenting the bit sequence to be coded according to the number of preset bit sequence segments or the length of the bit sequence segments;
further, for step b, the error check coding refers to any coding with an error check function, including but not limited to cyclic redundancy check coding, BCH code coding, reed-solomon code (RS code) coding, parity code;
further, for step c, the method may further comprise:
step c 1: firstly, carrying out forward error correction coding on each information bit sequence consisting of bits at corresponding positions in each bit sequence segment after error check coding to obtain respective check bit sequence; the forward error correction coding refers to coding with an error correction function, and includes but is not limited to bit exclusive or coding, block code coding, BCH code coding, reed solomon code (RS code) coding, fountain code coding, low density parity check code coding, Turbo code coding, polar code (polar code) coding, and convolutional code coding;
step c 2: bits at corresponding positions in each check bit sequence form a new bit sequence segment;
step c 3: combining each bit sequence segment after the original error check coding and the new bit sequence segment in the step c2 to form a new bit sequence to be error correction coded, and performing forward error correction coding on the new bit sequence to be error correction coded to generate a bit sequence to be sent;
further, for step c, the fec coding refers to coding with error correction function, including but not limited to bit xor coding, block code coding, BCH code coding, reed solomon code (RS code) coding, fountain code coding, low density parity check code coding, Turbo code coding, Polar code (Polar code) coding, convolutional code coding;
further, for steps a to c, if the forward error correction coding method is low density parity check code coding, in step a, the transmitting end divides the bit sequence to be coded into Kb segments, where Kb is a positive integer and Kb is Nb-Mb, where Nb is the number of columns of the basic check matrix of the low density parity check code and Mb is the number of rows of the basic matrix of the low density parity check code; or,
if the fec coding method is low density parity check code coding, in step a, the transmitting end performs segmentation in units of E bits, where E is a positive integer and E-z-K3, where z is a spreading factor of the low density parity check code, and K3 is a redundant bit length of each bit sequence segment after error check coding in step b.
Further, for a predetermined threshold, when the systematic bit weight of the basic check matrix of the low density parity check code corresponding to a part of the bit sequence segments is greater than the threshold, then the part of the bit sequence segments may be forward error check encoded.
The above proposed error correction coding scheme is described below in several specific embodiments:
the first embodiment is as follows:
a transmitting end transmits a bit sequence to be coded to a receiving end, wherein the length of the bit sequence to be coded is K bits, K1 bits are information bits, K2 bits are check bits generated after the information bits are subjected to error check coding, K, K1 and K2 are all non-negative integers, and K is K1+ K2; the error check coding includes but is not limited to cyclic redundancy check coding, BCH code coding, reed-solomon code (RS code) coding, parity check coding; in this example, the error-checking encoding is assumed to be Cyclic Redundancy Check (CRC) encoding.
Fig. 4 is a schematic diagram of an error correction coding process according to an embodiment of the present invention, and as shown in fig. 4, a transmitting end performs the following processing on a bit sequence to be coded:
the sending end segments the bit sequence to be coded according to the number of preset bit sequence segments or the length of the bit sequence segments, in this example, assuming that the number of segments is C segments, the bit sequence to be coded with K bits is uniformly divided into C bit sequence segments, and the length of each bit sequence segment is CA bit. If K cannot be divided exactly by C, adding in one of the bit sequence segmentsKnown bits at both transmitting and receiving ends; whereinIndicating a ceiling operation.
The sending end carries out error check coding on each bit sequence segment respectively, K3 is a check bit generated after each bit sequence segment is subjected to error check coding, and the length of each bit sequence subjected to error check coding isA bit; the error check coding includes but is not limited to cyclic redundancy check coding, BCH code coding, reed-solomon code (RS code) coding, parity check coding; in this example, it is assumed that the error-checking encoding mode of each bit sequence segment is Cyclic Redundancy Check (CRC) encoding.
The sending end makes the bit sequence fragments subjected to error check coding into a new bit sequence to be coded, and the length of the new bit sequence to be coded is K + C K3 bits, orA bit. And the transmitting end carries out forward error correction coding on the coded bit sequence to generate a bit sequence to be transmitted. Wherein the forward error correction coding includes, but is not limited to, bit exclusive or coding, block code coding, BCH code coding, reed-solomon code (RS code) coding, fountain code coding, low density parity check code coding, Turbo code coding, polarization code coding, convolutional code coding; in this example, it is assumed that the new forward error correction coding method of the bit sequence to be coded is low density parity check code (LDPC) coding.
Example two:
a transmitting end transmits a bit sequence to be coded to a receiving end, wherein the length of the bit sequence to be coded is K bits, K1 bits are information bits, K2 bits are check bits generated after the information bits are subjected to error check coding, K, K1 and K2 are all non-negative integers, and K is K1+ K2; the error check coding includes but is not limited to cyclic redundancy check coding, BCH code coding, reed-solomon code (RS code) coding, parity check coding; in this example, the error-checking encoding is assumed to be Cyclic Redundancy Check (CRC) encoding.
Fig. 5 is a schematic diagram of an error correction coding process according to a second embodiment of the present invention, and as shown in fig. 5, a transmitting end performs the following processing on a bit sequence to be coded:
the sending end is according to the number of the preset bit sequence fragments orThe length of the bit sequence segment is to segment the bit sequence to be coded, in this example, assuming that the number of segments is C, the bit sequence to be coded of K bits is uniformly divided into C bit sequence segments, and the length of each bit sequence segment isA bit. If K cannot be divided exactly by C, adding in one of the bit sequence segmentsKnown bits at both transmitting and receiving ends; whereinIndicating a ceiling operation.
The sending end carries out error check coding on each bit sequence segment respectively, K3 is a check bit generated after each bit sequence segment is subjected to error check coding, and the length of each bit sequence subjected to error check coding isA bit; the error check coding includes but is not limited to cyclic redundancy check coding, BCH code coding, reed-solomon code (RS code) coding, parity check coding; in this example, it is assumed that the error-checking encoding mode of each bit sequence segment is Cyclic Redundancy Check (CRC) check encoding.
And the transmitting end respectively carries out forward error correction coding on each information bit sequence consisting of bits at corresponding positions in the C bit sequence fragments after error check coding to obtain respective check bit sequences. For example, forward error correction coding is performed on the ith bit of the first bit sequence segment and the ith bit of the second bit sequence segment, … the ith bit of the C-th bit sequence segment, and the ith information bit sequence consisting of C bits, to obtain the ith check bit sequence, wherein the length of the check bit sequence is T bits, wherein i is a positive integer, andand so on, all together haveRespectively carrying out forward error correction coding on information sequences with the length of C bits to obtainA check bit sequence with length of T bits. Wherein the forward error correction coding includes, but is not limited to, bit exclusive or coding, block code coding, BCH code coding, reed-solomon code (RS code) coding, fountain code coding, low density parity check code coding, Turbo code coding, polar code coding, convolutional code coding. In this example bit exclusive or coding is assumed.
Bits at corresponding positions in each check bit sequence form a new bit sequence segment; e.g. the jth bit of the first check bit sequence and the jth bit of the second check bit sequence, …, thThe jth bit of each bit sequence segment forms a new bit sequence segment, wherein the length of the new bit sequence isBits, where j is a positive integer, and 1 ≦ j ≦ T; and so on, there are a total of T new bit sequence segments.
The sending end combines the C bit sequence segments after the original error check coding and the T new bit sequence segments to form a new bit sequence to be error-corrected, and the length of the new bit sequence to be error-corrected isA bit. And the sending end carries out forward error correction coding on the new bit sequence to be error-corrected. The forward error correction coding includes, but is not limited to, bit XOR coding, block code coding, BCH code codingCodes, reed-solomon code (RS code) codes, fountain code codes, low density parity check code codes, Turbo code codes, Polar code (Polar code) codes, convolutional code codes. In this example a Polar code (Polar code) code is assumed.
Example three:
a transmitting end transmits a bit sequence to be coded to a receiving end, wherein the length of the bit sequence to be coded is K bits, K1 bits are information bits, K2 bits are check bits generated after the information bits are subjected to error check coding, K, K1 and K2 are all non-negative integers, and K is K1+ K2; in this example, the error-checking encoding is assumed to be Cyclic Redundancy Check (CRC) encoding.
The sending end carries out the following processing on a bit sequence to be coded:
the transmitting end segments the bit sequence to be coded according to the number of preset bit sequence segments or the length of the bit sequence segments, in this example, the number of segments is assumed to be Kb segments, where Kb is a basic matrix H of a low density parity check code (LDPC)bSubtracting the number of rows from the number of columns, dividing the K-bit sequence to be coded into Kb bit sequence segments uniformly, wherein the length of each bit sequence segment isA bit. If K cannot be divided exactly by Kb, then adding in one of the bit sequence segmentsKnown bits at both transmitting and receiving ends; whereinIndicating a ceiling operation.
The sending end carries out error check coding on each bit sequence segment respectively, and K3 is a check bit generated after each bit sequence segment is subjected to error check coding and then subjected to error checkThe length of each bit sequence after coding isA bit; in this example, it is assumed that the error-checking encoding mode of each bit sequence segment is Cyclic Redundancy Check (CRC) encoding.
The sending end makes the bit sequence fragments subjected to the error check coding into a new bit sequence to be coded, and the length of the new bit sequence to be coded is K + Kb K3 bits, orA bit. And the transmitting end carries out forward error correction coding on the coded bit sequence to generate a bit sequence to be transmitted. In this example, it is assumed that the new forward error correction coding method of the bit sequence to be coded is low density parity check code (LDPC) coding.
Example four:
a transmitting end transmits a bit sequence to be coded to a receiving end, wherein the length of the bit sequence to be coded is K bits, K1 bits are information bits, K2 bits are check bits generated after the information bits are subjected to error check coding, K, K1 and K2 are all non-negative integers, and K is K1+ K2; in this example, the error-checking encoding is assumed to be Cyclic Redundancy Check (CRC) encoding.
The sending end carries out the following processing on a bit sequence to be coded:
the transmitting end segments the bit sequence to be encoded according to the number of preset bit sequence segments or the length of the bit sequence segments, in this example, it is assumed that the length of the bit sequence segments is E bits, where E is a positive integer, and E ═ z-K3, where z is a spreading factor of the low density parity check code, and K3 is the redundant bit length after error check encoding of each bit sequence segment. The K bits of the bit sequence to be coded are evenly divided intoAnd each bit sequence segment is E bits in length. If K cannot be divided exactly by E, adding in one of the bit sequence segmentsKnown bits at both transmitting and receiving ends; whereinIndicating a ceiling operation.
The sending end carries out error check coding on each bit sequence fragment respectively, K3 is a check bit generated after each bit sequence fragment is subjected to error check coding, and the length of each bit sequence subjected to error check coding is z bits; in this example, it is assumed that the error-checking encoding mode of each bit sequence segment is Cyclic Redundancy Check (CRC) encoding.
The sending end makes the bit sequence segments which are subjected to error check coding into a new bit sequence to be coded, and the length of the new bit sequence with coding isA bit. And the transmitting end carries out forward error correction coding on the bit sequence to be coded to generate a bit sequence to be transmitted. In this example, it is assumed that the new forward error correction coding method of the bit sequence to be coded is low density parity check code (LDPC) coding.
Example five:
a transmitting end transmits a bit sequence to be coded to a receiving end, wherein the length of the bit sequence to be coded is K bits, K1 bits are information bits, K2 bits are check bits generated after the information bits are subjected to error check coding, K, K1 and K2 are all non-negative integers, and K is K1+ K2; in this example, the error-checking encoding is assumed to be Cyclic Redundancy Check (CRC) encoding.
The sending end carries out the following processing on a bit sequence to be coded:
the transmitting end segments the bit sequence to be coded according to the number of preset bit sequence segments or the length of the bit sequence segments, in this example, the number of segments is assumed to be Kb segments, where Kb is a basic matrix H of a low density parity check code (LDPC)bSubtracting the row number from the middle column number, then dividing the bit sequence to be coded of K bits into Kb bit sequence segments non-uniformly, and carrying out error check coding on only part of the bit sequence segments;
among Kb bit sequence segments, there are W1 first-class bit sequence segments, each of which has a length of z bits, and W2 second-class bit sequence segments, each of which has a length of E bits, where E is a positive integer, and E ═ z-K3, K3 is a redundant bit length after error check encoding of the second-class bit sequence segments. Kb-W1 + W2;
the W2 second bit sequence fragments correspond to heavier columns of the systematic bit portion of the base check matrix of the low density parity check code. For example, in the system level part of the basic education matrixWherein the weight of W2 is greater than or equal to the preset threshold; the indices of the W2 columns are I ═ I, respectively1,I2,I3,...,Iw2]Then the W2 second bit sequence segments correspond to the W2 bit sequence segments referenced I in Kb bit sequence segments; the rest bit sequence segments are the W1 first-class bit sequence segments;
and respectively carrying out error check coding on each bit sequence fragment of the W2 second-class bit sequence fragments, and adding K3 error check bits after each second-class bit sequence fragment. In this example, it is assumed that the error-checking encoding mode of each bit sequence segment is Cyclic Redundancy Check (CRC) encoding.
And the sending end makes the bit sequence fragments subjected to error check coding into a new bit sequence to be coded, wherein the length of the new bit sequence with coding is z × Kb bits. And the transmitting end carries out forward error correction coding on the bit sequence to be coded to generate a bit sequence to be transmitted. In this example, it is assumed that the new forward error correction coding method of the bit sequence to be coded is low density parity check code (LDPC) coding.
The beneficial effect of the scheme provided by this embodiment is mainly represented in that, when a channel decoder at a receiving end decodes a codeword which is error correction coded by this embodiment, the decoder can judge whether the current bit sequence segment is correct or not according to the error check code of each bit sequence segment in the decoding process, if so, the decoder regards the current bit sequence segment as a definite bit and does not need to decode the current bit sequence continuously, which is equivalent to shortening the code decoding, reducing the code rate of the original codeword and improving the decoding performance; meanwhile, the embodiment also provides forward error correction of the corresponding position bits among the bit sequence segments, which is equivalent to adding one-level inner code protection, thereby improving the performance of final decoding.
In particular, the present embodiment also specifically proposes, for the low density parity check code, matching the number of bit sequence fragments with parameters of a basic matrix of the low density parity check code, or matching the length of the bit sequence fragments with the size of a spreading factor of the low density parity check code, so that the segmented error check and the low density parity check code proposed by the present embodiment can be perfectly combined, and the efficiency and performance of encoding and decoding can be improved.
In particular, since the ldpc code has different error correction capabilities for different parts of the codeword, this embodiment also proposes a non-uniform segmentation and partial error check method specifically for the ldpc code, and performs error check only on columns with heavier column weights in the systematic bit part of the basic check matrix of the ldpc code. The method has the advantages that the error check is carried out on the bit sequence segment with stronger error correction capability, whether the bit sequence segment is decoded correctly or not can be confirmed as soon as possible, the bit sequence segment which is decoded correctly can be regarded as a confirmed bit, and the current bit sequence does not need to be decoded continuously, which is equivalent to shortening the code decoding, reducing the code rate of the original code word and improving the decoding performance; meanwhile, since only error check bits need to be added to part of the bit sequence segments, the overhead is also reduced.
The embodiment of the invention also provides a storage medium. Alternatively, in the present embodiment, the storage medium may be configured to store program codes for performing the following steps:
step S202, segmenting a first bit sequence to be error-correction coded;
step S204, error check coding is respectively carried out on part or all of the segmented bit sequence segments;
step S206, forming each bit sequence segment after error check coding into a second bit sequence to be error correction coded, and performing forward error correction coding on the second bit sequence to be error correction coded to generate a bit sequence to be transmitted;
step S208, transmitting the bit sequence to be transmitted.
Optionally, in this embodiment, the storage medium may include, but is not limited to: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk, which can store program codes.
Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation manners, and this embodiment is not described herein again.
It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (13)
1. An error correction encoding method, comprising:
segmenting a first bit sequence to be error-correction coded;
respectively carrying out error check coding on part or all of the segmented bit sequence segments;
forming each bit sequence segment after error check coding into a second bit sequence to be error correction coded, and carrying out forward error correction coding on the second bit sequence to be error correction coded to generate a bit sequence to be transmitted;
and transmitting the bit sequence to be transmitted.
2. The method according to claim 1, characterized in that the first sequence of coded bits to be error corrected comprises at least one of:
a sequence of information bits;
and carrying out error check coding on the whole information bit sequence.
3. The method of claim 1 or 2, wherein the error checking encoding comprises at least one of:
cyclic redundancy check coding, BCH code coding, RS code coding and parity check coding.
4. The method of claim 1, wherein segmenting the first bit sequence to be error correction encoded comprises:
and uniformly or non-uniformly segmenting the bit sequence to be coded according to the number of preset bit sequence segments or the length of the bit sequence segments.
5. The method of claim 1, wherein the forming the bit sequence segments after error check coding into a second bit sequence to be error correction coded, and performing forward error correction coding on the second bit sequence to be error correction coded to generate a bit sequence to be transmitted comprises:
firstly, carrying out forward error correction coding on each information bit sequence consisting of bits at corresponding positions in each bit sequence segment after error check coding to obtain respective check bit sequence;
forming a new bit sequence segment by using bits at corresponding positions in each check bit sequence;
and synthesizing each bit sequence segment after the original error check coding and the new bit sequence segment into a third bit sequence to be error correction coded, and carrying out forward error correction coding on the third bit sequence to be error correction coded to generate a bit sequence to be transmitted.
6. The method according to any of claims 1 to 5, wherein the forward error correction coding comprises at least one of:
bit exclusive or coding, block code coding, BCH code coding, RS code coding, fountain code coding, low density parity check code coding, Turbo code coding, polarization code coding, convolutional code coding.
7. The method according to claim 6, wherein in case the forward error correction coding method is low density parity check code coding, segmenting the first bit sequence to be error correction coded comprises:
dividing a bit sequence to be coded into Kb sections, wherein Kb is a positive integer, and Kb is Nb-Mb, wherein Nb is the column number of a basic check matrix of the low-density parity check code, and Mb is the row number of the basic check matrix of the low-density parity check code; or,
and segmenting according to the unit of E bits, wherein E is a positive integer, and E is z-K3, wherein z is a spreading factor of the low-density parity check code, and K3 is the redundant bit length after error check coding is respectively carried out on part of or all of the segmented bit sequence fragments.
8. The method of claim 6, wherein, in the case that the forward error correction coding method is low density parity check coding, respectively performing error check coding on the segmented partial bit sequence segments comprises:
selecting bit sequence fragments with the weight of the system bit part of the basic check matrix of the low-density parity check code larger than a preset threshold value from the segmented bit sequence fragments;
and carrying out error check coding on the selected bit sequence segment.
9. An error correction encoding apparatus, comprising:
the device comprises a segmenting module, a coding module and a decoding module, wherein the segmenting module is used for segmenting a first bit sequence to be error-correction coded;
the error check coding module is used for respectively carrying out error check coding on part or all of the bit sequence fragments after segmentation;
the forward error correction coding module is used for forming each bit sequence segment after error check coding into a second bit sequence to be error correction coded, and performing forward error correction coding on the second bit sequence to be error correction coded to generate a bit sequence to be sent;
and the sending module is used for sending the bit sequence to be sent.
10. The apparatus of claim 9, wherein the segmentation module is further configured to:
and uniformly or non-uniformly segmenting the bit sequence to be coded according to the number of preset bit sequence segments or the length of the bit sequence segments.
11. The apparatus of claim 9, wherein the forward error correction coding module is further configured to:
firstly, carrying out forward error correction coding on each information bit sequence consisting of bits at corresponding positions in each bit sequence segment after error check coding to obtain respective check bit sequence;
forming a new bit sequence segment by using bits at corresponding positions in each check bit sequence;
and synthesizing each bit sequence segment after the original error check coding and the new bit sequence segment into a third bit sequence to be error correction coded, and carrying out forward error correction coding on the third bit sequence to be error correction coded to generate a bit sequence to be transmitted.
12. The apparatus of claim 9, wherein when the forward error correction coding method is low density parity check coding, the segmentation module is further configured to:
dividing a bit sequence to be coded into Kb sections, wherein Kb is a positive integer, and Kb is Nb-Mb, wherein Nb is the column number of a basic check matrix of the low-density parity check code, and Mb is the row number of the basic check matrix of the low-density parity check code; or,
and segmenting according to the unit of E bits, wherein E is a positive integer, and E is z-K3, wherein z is a spreading factor of the low-density parity check code, and K3 is the redundant bit length after error check coding is respectively carried out on part of or all of the segmented bit sequence fragments.
13. The apparatus of claim 9, wherein when the forward error correction coding method is low density parity check coding, the error check coding module comprises:
a selecting unit, configured to select, from the segmented bit sequence segments, a bit sequence segment in which a weight of a system bit portion of a basic check matrix of the low-density parity-check code is greater than a preset threshold;
and the error check coding unit is used for carrying out error check coding on the selected bit sequence segment.
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| CN1282307C (en) * | 2004-03-05 | 2006-10-25 | 上海交通大学 | Method of adding circular test bit before coding Turbo product code |
| CN101383618B (en) * | 2007-09-05 | 2013-02-27 | 中兴通讯股份有限公司 | Encoding method for cyclic redundancy check code of transmission block |
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