CN107331295A - Display pannel - Google Patents
Display pannel Download PDFInfo
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- CN107331295A CN107331295A CN201610284602.3A CN201610284602A CN107331295A CN 107331295 A CN107331295 A CN 107331295A CN 201610284602 A CN201610284602 A CN 201610284602A CN 107331295 A CN107331295 A CN 107331295A
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- clock
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Computer Hardware Design (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A kind of display pannel, including substrate, multiple data wires, multiple gate lines, power line and gate driving circuit.Power line couples a voltage source.Gate driving circuit is arranged in a visible area of display pannel, is coupled to gate line and power line, and produce multiple gate drive signals according to an initial pulse.Gate line is formed by the first metal layer on substrate, data wire is formed by the second metal layer above the first metal layer, power line is formed by one the 3rd metal level above second metal layer, and at least one view field of a view field with power line on substrate on substrate of data wire is overlapping.
Description
Technical field
The present invention relates to a kind of display pannel, being particularly arranged on gate driving circuit comprising one kind can
Display pannel in vision area.
Background technology
In general display, drive circuit is important driving element.With driving chip in conventional art
As the drive circuit of panel.In recent years, a kind of integrated gate leve drive circuit (Integrated Gate are developed
Driver), it is that gate driving circuit is made on panel, this technology is also collectively referred to as grid on panel and driven
Dynamic device (Gate driver on panel, abbreviation GOP).
Since the development of GOP technologies, the general practice is all by the circuit integrated sides in substrate both sides of GOP
Frame area.But this way can occupy the frame space of panel both sides, allow frame to have suitable width.And it is right
In mobile communications device now, Wearable device and the automobile-used middle control product such as instrument board, pole narrow frame and non-
The design of square type panel gradually turn into product trend, if therefore on display apparatus module must realize narrow frame and
Non-rectangle design, with general tradition by GOP circuit designs the way of frame can have certain limitation and
Difficulty.
Accordingly, it would be desirable to a kind of novel circuit design and layout, to realize pole narrow frame design demand.
The content of the invention
The present invention disclose a kind of display pannel, including multiple data wires, multiple gate lines, power line with
And gate driving circuit.Power line couples a voltage source.Gate driving circuit is arranged on the display pannel
A visible area in, be coupled to gate line and power line, and multiple grids are produced according to an initial pulse
Drive signal.Gate line is formed by the first metal layer on a substrate, and data wire is by positioned at first
One second metal layer of metal layer is formed, and power line is by one the 3rd gold medal above second metal layer
Category layer is formed, and data wire at least one view field on substrate with power line on substrate
A view field it is overlapping.
The present invention separately discloses a kind of display pannel, including multiple gate lines, multiple clock cables and
One gate driving circuit.Clock cable is to provide multiple clock signals.Gate driving circuit is arranged on
In one visible area of display pannel, gate line and clock cable are coupled to, and according to a starting
The multiple gate drive signals of pulses generation.Gate line is with clock cable by one first on a substrate
Metal level is formed, and gate line is parallel with clock cable.
The present invention separately discloses a kind of display pannel, including multiple data wires, multiple gate lines, Duo Geshi
Clock signal wire, a power line and a gate driving circuit.Clock cable is to provide multiple clock letters
Number.Power line couples a voltage source.Gate driving circuit is arranged in a visible area of display pannel,
Gate line, clock cable and power line are coupled to, and multiple grids are produced according to an initial pulse and is driven
Dynamic signal.Gate line is formed with clock cable by a first metal layer, and gate line and clock signal
Line is parallel, and data wire is formed by a second metal layer, and power line is formed by one the 3rd metal level.
Brief description of the drawings
Fig. 1 is to show the display equipment block diagram according to one embodiment of the invention.
Fig. 2 be show described in embodiment according to the first aspect of the invention to be arranged on display pannel visual
Gate driver circuitry topology figure in area.
Fig. 3 is the top view for showing a kind of electronic installation example according to one embodiment of the invention.
Fig. 4 is the square for showing the one-level driver element described in embodiment according to the first aspect of the invention
Figure.
Fig. 5 is to show the several levels driver element described in first embodiment according to the first aspect of the invention
Circuit diagram.
Fig. 6 is to show the signal waveforms according to one embodiment of the invention.
Fig. 7 is that the layout for the block for showing the picture element matrix according to one embodiment of the invention is overlooked
Figure.
Fig. 8 A are that the layout for the block for showing the picture element matrix according to one embodiment of the invention is saturating
View.
Fig. 8 B are to show the drive in display pannel visible area according to one embodiment of the invention
The layout profile of moving cell circuit region.
Fig. 9 A are the top views for showing a kind of electronic installation example according to one embodiment of the invention.
Fig. 9 B are to show non-in display pannel visible area according to one embodiment of the invention
The layout profile of driver element circuit region.
Figure 10 A are to show the several levels driver element described in second embodiment according to the first aspect of the invention
Circuit diagram.
Figure 10 B are to show the several levels driver element described in 3rd embodiment according to the first aspect of the invention
Circuit diagram.
Figure 11 A are to show the gate driving circuit described in fourth embodiment according to the first aspect of the invention
And clock signal schematic representation.
Figure 11 B are to show the signal waveforms described in fourth embodiment according to the first aspect of the invention.
Figure 12 is the square for showing n-th grade of driver element described in embodiment according to the second aspect of the invention
Figure.
Figure 13 A are to show the several levels driver element described in first embodiment according to the second aspect of the invention
Circuit diagram.
Figure 13 B are to show the signal waveforms described in first embodiment according to the second aspect of the invention.
Figure 14 A are to show the several levels driver element described in second embodiment according to the second aspect of the invention
Circuit diagram.
Figure 14 B are to show the signal waveforms described in second embodiment according to the second aspect of the invention.
Figure 15 A are to show the several levels driver element described in 3rd embodiment according to the second aspect of the invention
Circuit diagram.
Figure 15 B are to show the several levels driver element described in fourth embodiment according to the second aspect of the invention
Circuit diagram.
Figure 16 A are to show the signal waveforms described in sixth embodiment according to the second aspect of the invention.
Figure 16 B are to show another signal waveform described in sixth embodiment according to the second aspect of the invention
Figure.
Figure 16 C are to show another signal wave again described in sixth embodiment according to the second aspect of the invention
Shape figure.
Figure 17 is to show described to be according to another embodiment of the present invention arranged on display pannel visible area
Interior gate driver circuitry topology figure.
Figure 18 is the layout for the block for showing picture element matrix described according to another embodiment of the present invention
Top view.
Figure 19 A are display clock signal and gate drive signal example oscillograms when parasitic capacitance is small.
Figure 19 B are display clock signal and gate drive signal example oscillograms when parasitic capacitance is big.
Figure 20 is to show the gate driving circuit described in first embodiment according to the third aspect of the invention we
Organization Chart.
Figure 21 is to show the signal waveforms described in first embodiment according to the third aspect of the invention we.
Figure 22 is the ripple example for showing gate drive signal.
【Symbol description】
100~display equipment；
101~display pannel；
102~input block；
110~gate driving circuit；
120~data drive circuit；
130~picture element matrix；
140~control chip；
200th, 200 ', 1700, AA~visible area；
200-1、200-2、200-3、210、220、
2201~ripple；
310th, 320~driver element circuit region；
500th, 1500, GOP, GOP_E, GOP_F, GOP_M~driver element；
501st, 1501~pull-up control circuit；
502nd, 1502~pull-up output circuit；
503rd, 1503~pull-down control circuit；
504th, 1504-1,1504-2~drop-down output circuit；
Active~semiconductor active layer；
BP1, BP2, BP3~insulating barrier；
Cb (n), Cb (n+1), Cccom, Ccp, Cxcg, Cxcv~electric capacity；
CE~common electrode；
CK、CK1、CK2、CK3、CK4、CK5、CKA、CKB、CKC、CKD、CKA_E、
CKB_E, CKA_F, CKB_F, CKA_M, CKB_M, CLK~clock cable；
DL, DL (1), DL (2), DL (3), DL (4), DL (5), DL (6)~data wire；
GE~grid；
GI~gate dielectric；
GL, GL (1), GL (2), GL (3), GL (4), GL (n-1), GL (n), GL (n+1)~grid
Line；
M1, M2, M3~metal level；
GOUT~gate drive signal；PFA~planarization layer；
PE~pixel electrode；
RESET~slot signal；
SD~source/drain；
STV, STV1, STV2~initial pulse；
T1(n)、T1(n+1)、T2(n)、T2(n+1)、T3(n)、T3(n+1)、T4(n-1)、T4(n)、T4(n+1)、
T4a (n), T4a (n+1)~transistor；
VSS~power line.
Embodiment
For enable the present invention above and other objects, features and advantages become apparent, it is cited below particularly go out
Preferred embodiment, and coordinate accompanying drawing, elaborate.
Fig. 1 is to show the display equipment block diagram according to one embodiment of the invention.As illustrated,
Display equipment 100 may include a display pannel 101, a data drive circuit 120 and a control core
Piece 140.Display pannel 101 includes a gate driving circuit 110 and a picture element matrix 130, wherein grid
Pole drive circuit 110 is arranged in picture element matrix 130.Picture element matrix 130 includes multiple pixel cells,
Each pixel cell is coupled to one group of gate line and data wire interlocked.Gate driving circuit 110 is used to many
Individual gate line produces corresponding gate drive signal to drive pixel cell.Data drive circuit 120 is used to
Produce corresponding data drive signal to provide view data to pixel cell in multiple data wires.Control core
Piece 140 is to produce multiple clock signals, including clock signal, reset signal and initial pulse etc..
In addition, display equipment 100 can further comprise an input block 102.Input block 102 is used
In reception picture signal, and export to control chip 140.Embodiments in accordance with the present invention, display dress
Put 100 to can be applied in an electronic installation, wherein electronic installation there are numerous embodiments, including：One moves
Mobile phone, a digital camera, a personal digital assistant, a mobile computer, a desktop PC,
One television set, a vapour vehicle display, a portable optic disk, which are dialled, puts device or any including image display work(
The device of energy.
It is worth noting that, in some embodiments of the invention, the data drive circuit of display equipment
It can be integrated into control chip 140.In these embodiments, view data can pass through control chip 140
There is provided to picture element matrix 130.Therefore, the framework shown in Fig. 1 be only the present invention various embodiments in
One of which, and it is not limited to the scope of the present invention.
In general, display pannel includes visible area (Active Area, AA) and rim area (Frame
Area).According to one embodiment of the invention, gate driving circuit 110 is arranged on display pannel 101
Visible area in.A variety of gate driving circuits proposed by the invention will be described in greater detail below.
According to the first aspect of the invention, all elements of gate driving circuit 110 are arranged on display
In the visible area of device panel 101.
Fig. 2 be show described in embodiment according to the first aspect of the invention to be arranged on display pannel visual
Gate driver circuitry topology figure in area.As illustrated, gate driving circuit may include to be arranged on display
Multiple driver element GOP in panel visible area (AA) 200.Gate driving circuit is coupled at least one electricity
Source line, and at least two clock cables, wherein power line is coupled to voltage source VSS, to provide
Reference voltage VGL needed for system, and clock cable is coupled to clock source, to provide at least two
Clock signal CKA and CKB.Gate driving circuit receives initial pulse STV and involution by signal wire
Signal RESET, and multiple gate drive signals are produced in response to initial pulse STV, then by slot signal
RESET closes afterbody driver element GOP.
According to one embodiment of the invention, driver element GOP can form a matrix, and one of driving is single
Member may be provided between multiple data lines.Therefore, the layout of a driver element can be across several pixels
Unit.For example, in one embodiment of the invention, as shown in figure 5, a driver element can be set
Between 6 data lines, therefore the layout of a driver element can be across 5 pixel cells.In other words
Say, according to one embodiment of the invention, for a line (row) pixel cell of picture element matrix, it is configured
Driver element quantity less than display pannel data wire quantity.It is worth noting that, in this hair
In bright other embodiment, a driver element also may be disposed at more than 6 or less than 6 data lines
Between, therefore the present invention is not limited to any embodiment.
Fig. 3 is the top view for showing a kind of electronic installation example according to one embodiment of the invention,
The scope 310 and 320 wherein outlined by dotted line represents the driver element circuit region of gate driving circuit,
It may correspond to the driver element circuit region 210 and 220 shown in Fig. 2, to illustrate raster data model electricity
Relative position of wherein two columns (column) driver element on the panel visible area of electronic installation in road.
According to one embodiment of the invention, the raster data model electricity in the visible area of display pannel is arranged on
Road may include N grades of driver elements, and wherein N is a positive integer.Fig. 4 is to show real according to of the invention one
Apply the block diagram of n-th grade of driver element described in example, wherein n is a positive integer, and 0<n≦N.Drive
Moving cell 500 may include pull-up control circuit 501, pull-up output circuit 502, pull-down control circuit 503
And drop-down output circuit 504, wherein pull-up output circuit 502 is coupled to drop-down output circuit 504
Nth bar gate lines G L (n), the output to control gate drive signal.As shown in figure 4, driving is single
Member 500 all elements be arranged in the visible area of display pannel, and signal wire be arranged on it is aobvious
Show the rim area of device panel.
In the first aspect of the present invention embodiment, due to being only left signal lead in the rim area of both sides, because
This can realize pole narrow frame design demand, can more realize non-rectangle panel design requirement.
Fig. 5 is to show the several levels driver element described in first embodiment according to the first aspect of the invention
Circuit diagram.For concise explanation, Fig. 5 only shows the one of a column (column) driver element of gate driving circuit
Part, wherein this column driver element, such as transistor T1 (n), T1 (n+1), T2 (n) shown in figure,
T2 (n+1), T3 (n), T3 (n+1), T4 (n-1) and T4 (n) and electric capacity Cb (n) and Cb (n+1), are set
Put between data wire DL (1)~DL (6), wherein data wire DL (1)~DL (6) is only illustrating, rather than limit
Determine the scope of the present invention.
Transistor T1 corresponds to the pull-up output circuit of the driver element shown in Fig. 4, transistor T2 correspondences
In the pull-up control circuit of driver element as shown in Figure 4, transistor T3 corresponds to drive as shown in Figure 4
The pull-down control circuit of moving cell, the drop-down that transistor T4 corresponds to driver element as shown in Figure 4 is exported
Circuit.Notice is known, the pull-up output circuit of the first embodiment of first aspect, pull-up control circuit,
Pull-down control circuit is illustrated with drop-down output circuit exemplified by respectively including a transistor, but is implemented at other
In example, aforementioned circuit also can respectively include more than one transistor.
According to one embodiment of the invention, n-th grade of driver element may include transistor T1 (n), T2 (n),
T3 (n), T4 (n) and electric capacity Cb (n).There is transistor T1 (n) one first pole to be coupled to clock cable
CKA, and one second pole are coupled to nth bar gate lines G L (n).Transistor T2 (n) has a control pole
(n-1) article gate lines G L (n-1) is coupled to one first pole, and one second pole is coupled to transistor T1 (n)
Control pole.There is transistor T3 (n) control pole to be coupled to (n+1) article gate lines G L (n+1), and one the
One pole is coupled to transistor T2 (n) the second pole, and one second pole is coupled to power line VSS.Transistor
There is T4 (n) control pole to be coupled to clock cable CKB, and one first pole is coupled to nth bar gate line
GL (n), and one second pole are coupled to power line VSS.
Fig. 6 is to show the signal waveforms according to one embodiment of the invention.As gate lines G L (n-1)
On grid impulse when arriving at, transistor T2 (n) is switched on, and then turns on transistor T1 (n).Treat clock
When clock pulses on signal wire CKA is arrived at, gate line can be transferred to by the transistor T1 (n) of conducting
GL (n) outputs are used as grid impulse.When the grid impulse on gate lines G L (n+1) is arrived at, transistor
T3 (n) is switched on, the voltage of pull-down transistor T1 (n) control pole, to close transistor T1 (n).Together
Sample, when the clock pulses on clock cable CKB is arrived at, transistor T4 (n) is switched on, drop-down
Nth bar gate lines G L (n) voltage.
As shown in figure 5, driver elements at different levels drive only comprising 4 transistors compared in traditional design
Unit needs at least 13 transistors, and gate driving circuit proposed by the invention can effectively reduce visible area
The loss of interior pixel aperture ratio.
In addition, in an embodiment of the present invention, in order to further reduce pixel aperture ratio in visible area
The layout of circuit signal line can be also further designed in loss, visible area.
According to the first embodiment of the present invention, the gate line of display pannel is formed by a first metal layer,
Data wire is formed by a second metal layer, and coupling voltage source VSS power line is formed by one the 3rd metal level,
Wherein the first metal layer is formed on a substrate, and second metal layer is formed above the first metal layer, and
3rd metal level is formed above second metal layer, wherein, substrate can be rigid substrate or flexible substrate.
Because data wire and power line are formed at different metal levels, data wire can be spatially overlapping with power line
(that is, data wire can be overlapping with the view field of power line one), thereby reduces pixel aperture ratio loss.In addition,
According to the first embodiment of the present invention, clock cable is formed by the first metal layer, and flat with gate line
OK.The contact of different metal interlayer can be connected by contact hole (contact via).
Fig. 7 is that the layout for the block for showing the picture element matrix according to one embodiment of the invention is overlooked
Clock cable CK can represent any clock cable as described in the present invention in figure, figure, for example, on
Any one of the clock cable CKA and CKB stated, data wire DL can be represented as described herein
Any data line, for example, any one of above-mentioned data wire D (1)~D (6).As illustrated, clock
Signal wire CK is parallel with gate lines G L (n), GL (n+1) etc., and data wire DL and power line VSS
A view field it is overlapping (therefore representing data wire DL and power line VSS using the same line in Fig. 7).
As shown in fig. 7, because no signal wire is by pixel electrode open region, can not only obtain higher open
Mouth rate, the aperture opening ratio that can also be allowed between pixel cell remains consistent, it is to avoid similar vertical line (vertical occur
) etc. line image quality unfavorable condition.
Fig. 8 A are that the layout for the block for showing the picture element matrix according to one embodiment of the invention is saturating
View.PE is pixel electrode, and CE is common electrode.As shown in Figure 8 A, in the design of the present invention,
Clock cable CLK layout is not overlapping with pixel electrode PE, therefore the voltage of pixel electrode will not
There is coupled problem.
Fig. 8 B are shown in the layout profile of the driver element circuit region in display pannel visible area, its
For the layout profile of the tangent line put by A points to A ' shown in Fig. 8 A.As shown in Figure 8 B, respectively
Metal level is sequentially formed on substrate, and wherein GE is the gate line for being formed at the first metal layer, and GI is grid
Pole dielectric layer (Gate Insulator), SD is the source/drain for the transistor for being formed at second metal layer, Active
For semiconductor active layer, BP1, BP2 and BP3 are insulating barrier, and PFA is planarization layer, and PE is pixel
Electrode, M3 is the 3rd metal level, and CE is common electrode, pixel electrode PE and common electrode CE material
Matter is transparent conductive oxide, for example indium tin oxide (indium tin oxide, ITO), indium-zinc oxide
(indium zinc oxide, IZO), fluorine doped tin oxide (fluorine doped tin oxide, FTO), mix aluminium
Zinc oxide (aluminum doped zinc oxide, AZO), gallium-doped zinc oxide (gallium doped zinc
Oxide, GZO).According to one embodiment of the invention, due to coupling voltage source VSS power line by the
Three metal levels are formed, therefore in driver element circuit region, the 3rd metal level is to transfer overvoltage source VSS's
Voltage signal.
It is worth noting that, the layout stacking mode shown in Fig. 8 B is only the one of various embodiments of the present invention
Kind, to illustrate idea of the invention, but it is not used to limit the scope of the present invention.
The application of embedded touch technology (touch in cell) in addition, the setting of the 3rd metal level can also arrange in pairs or groups,
Common electrode CE is connected using the 3rd metal level, for transmitting touch-control sensing signal, products application is improved
And surcharge.
Fig. 9 A are the top views for showing a kind of electronic installation example according to one embodiment of the invention.
Fig. 9 B are to show the non-driven in display pannel visible area according to one embodiment of the invention
The layout profile in element circuit area.As shown in Figure 9 A, can be by common electricity in display pannel visible area
Pole CE changes as touch-control sensing electrode for inductance capacitance.As shown in Figure 9 B, the 3rd metal is utilized
The setting of layer, in non-driven element circuit area, the 3rd metal level M3 is connected to jointly by contact hole
Electrode CE.
As described above, in the first embodiment of the present invention, clock cable is formed by the first metal layer, and
And it is parallel with gate line.In other embodiments of the invention, clock cable also can be by other metal levels
Formed.
According to the second embodiment of the present invention, the gate line of display pannel is formed by the first metal layer M1,
Data wire is formed by second metal layer M2, and coupling voltage source VSS power line is by the 3rd metal level M3
Formed, and clock cable can be changed to be formed by second metal layer M2, and it is parallel with data wire.
Figure 10 A are to show the several levels driver element described in second embodiment according to the first aspect of the invention
Circuit diagram.For concise explanation, Figure 10 A only show that a column (column) driving of gate driving circuit is single
A part for member, and data wire DL (1)~DL (6) is only to illustrate, and non-limiting the scope of the present invention.
As illustrated, clock cable CKA is parallel with data wire with CKB and is arranged at intervals.
In addition, according to the third embodiment of the invention, the gate line of display pannel is by the first metal layer M1
Formed, data wire is formed by second metal layer M2, coupling voltage source VSS power line is by the 3rd metal
Layer M3 is formed, and clock cable can be changed to be formed by the 3rd metal level M3, and with data wire weight
It is folded.
Figure 10 B are to show the several levels driver element described in 3rd embodiment according to the first aspect of the invention
Circuit diagram.For concise explanation, Figure 10 B only show that a column (column) driving of gate driving circuit is single
A part for member, and data wire DL (1)~DL (6) is only to illustrate, and non-limiting the scope of the present invention.
As illustrated, clock cable CKA and CKB it is parallel with the power line for coupling voltage source VSS and
Be arranged at intervals, and with data line overlap.It is worth noting that, in order to be able to show transistor AND gate clock
Overlapped in the tie point of signal wire and transistor AND gate power line, Fig. 5, Figure 10 A and Figure 10 B
Data wire is separately drawn with power line or the data wire overlapped with clock cable.However, must
It will be understood that when data wire and power line or data wire with clock cable are formed at different gold
When belonging to layer, its wiring can be spatially overlapping, makes its view field overlapping as shown in Fig. 7 with Fig. 8 B.
Furthermore it is noted that in other embodiments of the invention, the data wire of different metal level,
Power line can be spatially also not overlapping with the wiring of clock cable, thus the present invention layout not
It is limited to the above embodiments.
According to the fourth embodiment of the invention, the quantity of clock signal can be also further added by, to reduce driving
The work period of transistor in unit.
Figure 11 A are to show the gate driving circuit described in fourth embodiment according to the first aspect of the invention
Schematic diagram.As illustrated, the driver elements at different levels in gate driving circuit can be respectively coupled to clock signal
Line CKA, CKB, CKC and CKD, and can order persistent loop according to this.
Figure 11 B are to show the signal waveforms described in fourth embodiment according to the first aspect of the invention.
As illustrated, after initial pulse STV is arrived at, clock cable CKA, CKB, CKC and CKD
Nonoverlapping clock pulses is sequentially provided, clock pulses will be sequentially by gate lines G L (1), GL (2), GL (3)
Exported with GL (4), the embodiment compared to Fig. 5 and shown in Fig. 6, transistor in driver element (for example,
Transistor T1 and T4) work period can be reduced to 25% by 50%.Thus, it is possible to decrease driving is single
The time that transistor unit is biased in first, it is effectively increased circuit reliability.
As described above, in the first aspect of the present invention, all elements of gate driving circuit 110 are set
In the visible area of display pannel 101.And in the second aspect of the present invention, gate driving circuit 110
Subelement may be disposed in the rim area of display pannel 101.
Figure 12 is the square for showing n-th grade of driver element described in embodiment according to the second aspect of the invention
Figure, wherein n is a positive integer, and 0<n≦N.Driver element 1500 may include pull-up control circuit
1501st, pull-up output circuit 1502, pull-down control circuit 1503 and drop-down output circuit 1504-1 with
1504-2, wherein pull-up output circuit 1502 and drop-down output circuit 1504-1 and 1504-2 are coupled to the
N bar gate lines G L (n), the output to control gate drive signal.As shown in figure 12, driver element
1500 drop-down output circuit 1504-1 and 1504-2 is arranged on the frame of display pannel with signal wire
Area.
Figure 13 A are to show the several levels driver element described in first embodiment according to the second aspect of the invention
Circuit diagram, wherein transistor T1 corresponds to the pull-up output circuit of the driver element shown in Figure 12, brilliant
Body pipe T2 corresponds to the pull-up control circuit of driver element as shown in figure 12, and transistor T3 corresponds to
The pull-down control circuit of driver element as shown in figure 12, transistor T4 and T4a corresponds to such as Figure 12
The drop-down output circuit of shown driver element.Notice is known, the first embodiment of second aspect it is upper
Output circuit, pull-up control circuit, pull-down control circuit are drawn with drop-down output circuit respectively to include a crystalline substance
Illustrate exemplified by body pipe, but in other embodiments, aforementioned circuit also can respectively include more than one transistor.
For concise explanation, Figure 13 A only show the part an of column (column) driver element of gate driving circuit,
Wherein a part of element of this column driver element, such as transistor T1 (n), T1 (n+1) shown in figure,
T2 (n), T2 (n+1), T3 (n), T3 (n+1) and electric capacity Cb (n) and Cb (n+1), are arranged on data wire
Between DL (1)~DL (5), and other parts element, such as transistor T4 (n), T4 (n+1), T4a (n) with
T4a (n+1) is arranged on rim area.Wherein data wire DL (1)~DL (5) is only to illustrate, and non-limiting
The scope of invention.
According to one embodiment of the invention, n-th grade of driver element may include transistor T1 (n), T2 (n),
T3 (n), T4 (n), T4a (n) and electric capacity Cb (n).Transistor T1 (n)~T3 (n) coupling mode and Fig. 5
Shown embodiment is identical, will not be repeated here.In this embodiment, transistor T4 (n) has a control
Pole is coupled to clock cable CK1, and one first pole is coupled to nth bar gate lines G L (n), and one
Two poles are coupled to power line VSS, and transistor T4a (n) coupling mode is identical with transistor T4 (n).
Figure 13 B are to show the signal waveforms described in first embodiment according to the second aspect of the invention.
When the grid impulse on gate lines G L (n-1) is arrived at, transistor T2 (n) is switched on, and then turns on crystal
Pipe T1 (n)., can be by the transistor T1 (n) of conducting when the clock pulses on clock cable CKA is arrived at
Gate lines G L (n) outputs are transferred to as grid impulse.When the grid impulse on gate lines G L (n+1) is arrived at
When, transistor T3 (n) is switched on, the voltage of pull-down transistor T1 (n) control pole, to close crystal
Pipe T1 (n).Similarly, when the clock pulses on clock cable CK1 is arrived at, transistor T4 (n)
It is switched on T4a (n), drop-down nth bar gate lines G L (n) voltage.
Though it is worth noting that, having increased two clock cables CK1 and CK2 in Figure 13 A newly, it is used to
Clock signal is provided to be not limited to the transistor T4 (n) and T4a (n) for being arranged on rim area, but the present invention
This.In other embodiments of the invention, the transistor T4 (n) and T4a (n) for being arranged on rim area also can be such as
Clock cable CKB is coupled to shown in Figure 14 A, Figure 15 A and Figure 15 B.In other words, in the present invention
Other embodiment in, being arranged at the transistor that the transistor AND gate of rim area is arranged in visible area can couple
To identical clock cable.
With the first embodiment of the first aspect of the present invention, in the first embodiment of the second aspect of the present invention
In, clock cable is formed by the first metal layer M1, and as shown in FIG. 13A, in visible area with
Gate line is parallel.In other embodiments of the invention, clock cable can also be formed by other metal levels.
Figure 14 A are to show the several levels driver element described in second embodiment according to the second aspect of the invention
Circuit diagram.Circuit shown in Figure 14 A and Figure 13 A duplicates, and difference is only that the crystalline substance for being arranged on rim area
Body pipe T4 (n) and T4a (n) is coupled to clock cable CKB, is being arranged at the transistor T4 (n+1) of rim area
Clock cable CKA is coupled to T4a (n+1).Figure 14 B are shown according to the second aspect of the invention
Signal waveforms described in second embodiment.It is worth noting that, the signal waveform shown in Figure 14 B also may be used
Shared for Figure 15 A and Figure 15 B circuit.
In the 3rd embodiment of the second aspect of the present invention, the gate line of display pannel is by the first metal
Layer M1 is formed, and data wire is formed by second metal layer M2, and coupling voltage source VSS power line is by the
Three metal level M3 are formed, and clock cable can be changed to be formed by second metal layer M2, and with number
It is parallel according to line.
Figure 15 A are to show the several levels driver element described in 3rd embodiment according to the second aspect of the invention
Circuit diagram.For concise explanation, Figure 15 A only show that a column (column) driving of gate driving circuit is single
A part for member, and data wire DL (1)~DL (5) is only to illustrate, and non-limiting the scope of the present invention.
As illustrated, clock cable CKA/CKB is parallel with data wire and is arranged at intervals.
In addition, in the fourth embodiment of the second aspect of the present invention, the gate line of display pannel is by first
Metal level M1 is formed, and data wire is formed by second metal layer M2, coupling voltage source VSS power line
Formed by the 3rd metal level M3, and clock cable can be changed to be formed by the 3rd metal level M3, and
With data line overlap.
Figure 15 B are to show the several levels driver element described in fourth embodiment according to the second aspect of the invention
Circuit diagram.For concise explanation, Figure 15 B only show that a column (column) driving of gate driving circuit is single
A part for member, and data wire DL (1)~DL (5) is only to illustrate, and non-limiting the scope of the present invention.
As illustrated, clock cable CKA/CKB with couple voltage source VSS power line it is parallel and
Every setting, and with data line overlap.It is worth noting that, in order to be able to show that transistor AND gate clock is believed
Weight in the tie point of number line and transistor AND gate power line, Figure 13 A, Figure 14 A, Figure 15 A and Figure 15 B
The folded data wire set is separately drawn with power line or the data wire overlapped with clock cable.
It must be understood, however, that when data wire is formed at power line or data wire with clock cable
During different metal level, its wiring can be spatially overlapping, makes its view field as shown in Fig. 7 and Fig. 8 B
It is overlapping.Furthermore it is noted that in other embodiments of the invention, different metal level
Data wire, power line can be spatially also not overlapping with the wiring of clock cable, therefore the present invention
Layout is not limited to the above embodiments.
In addition, the quantity of the clock signal in the 5th embodiment of the second aspect of the present invention, visible area
Also it can increase as shown in Figure 11 A as more than two, the work period to reduce transistor in visible area.
In addition, in the sixth embodiment of the second aspect of the present invention, when driver element is arranged on rim area
When element is coupled to different clock cables as shown in FIG. 13A from the element being arranged in visible area, carry
The quantity that supply is arranged on the clock signal of the element of rim area can be also further added by, to reduce rim area
The work period of transistor.
Figure 16 A are to show the signal waveforms described in sixth embodiment according to the second aspect of the invention,
This embodiment be Figure 13 A shown in second aspect first embodiment more increase a clock cable CK3
Embodiment.As illustrated, clock cable CK1, CK2 and CK3 are sequentially provided nonoverlapping clock
Transistor T4 and T4a not at the same level are given in pulse, therefore, compared to the embodiment shown in Figure 13 B, set
33% can be reduced in the work period of the transistor (for example, transistor T4 and T4a) of rim area by 50%.
Figure 16 B are to show another signal waveform described in sixth embodiment according to the second aspect of the invention
Figure, this embodiment be Figure 13 A shown in second aspect first embodiment more increase by two clock cables
CK3 and CK4 embodiment.As illustrated, clock cable CK1, CK2, CK3 and CK4 according to
Sequence provides nonoverlapping clock pulses to transistor T4 and T4a not at the same level, therefore, compared to Figure 13 B
Shown embodiment, is arranged on the work period of the transistor (for example, transistor T4 and T4a) of rim area
25% can be reduced to by 50%.
Figure 16 C are to show another signal wave again described in sixth embodiment according to the second aspect of the invention
Shape figure, this embodiment be Figure 13 A shown in second aspect first embodiment more increase by three clock signals
Line CK3, CK4 and CK5 embodiment.As illustrated, clock cable CK1, CK2, CK3,
CK4 and CK5 are sequentially provided nonoverlapping clock pulses to transistor T4 and T4a not at the same level, therefore,
Compared to the embodiment shown in Figure 13 B, the transistor (for example, transistor T4 and T4a) of rim area is arranged on
Work period can be reduced to 20% by 50%.
Therefore, according to the sixth embodiment in the second aspect of the present invention, the transistor unit of rim area by
Time to bias can be lowered, and be effectively increased circuit reliability.
Example illustrated above.For example, though clock cable CKA and CKB is visual in Fig. 2
Layout in area 200 is horizontal, and layouts of the power line VSS in visible area 200 is longitudinal direction, but this
Invention is not limited to this.
Figure 17 is to show described to be according to another embodiment of the present invention arranged on display pannel visible area
Interior gate driver circuitry topology figure.As illustrated, in this embodiment, clock cable CKA with
Layouts of the CKB in visible area 200 is longitudinal direction, and layouts of the power line VSS in visible area 200 is
Laterally.
However, either with transversely or longitudinally extending to being connected with driver element GOP in visible area, all without
Method avoids clock signal from being caused to drive scarce capacity by effect of parasitic capacitance in visible area, and then
Cause gate line output signal deep fades.
Figure 18 is the layout for the block for showing picture element matrix described according to another embodiment of the present invention
Top view.As illustrated, clock cable CLKA/CLKB staggeredly can be formed with power line VSS and posted
Raw electric capacity Cxcv, clock cable CLKA/CLKB staggeredly can form parasitic capacitance with gate line
Cxcg, clock cable CLKA/CLKB can produce parasitic capacitance by open region with pixel electrode
Ccp, and clock cable CLKA/CLKB can form parasitic capacitance by open region with common electrode
Cccom.When panel resolution is higher, the parasitic capacitance formed is also just bigger, causes clock signal
Driving force is deteriorated.
Figure 19 A are display clock signal and gate drive signal example oscillograms when parasitic capacitance is small.Figure
19B is display clock signal and gate drive signal example oscillogram when parasitic capacitance is big.As illustrated,
When parasitic capacitance is big, the driving force of clock signal can be deteriorated, and in turn result in gate drive signal generation
Serious distortion.
In order to solve the above problems, in the third aspect of the present invention, novel clock signal cabling cloth is proposed
The clock signal sequence configuration method of office's framework and novelty, is caused with scattered parasitic capacitance to clock signal
Influence.
Driver element circuit in embodiment according to the third aspect of the invention we, visible area can be divided into many
Individual region, driver element circuit region as escribed above.The division of circuit region is not limited to vertical or horizontal draw
Point.The circuit of each driver element circuit region configures exclusive clock cable to drive corresponding driver element.
For example, in one embodiment of this invention, the first driver element circuit region and second in visible area
Driver element circuit region is driven by different groups of clock cable.
Figure 20 is to show the gate driving circuit described in first embodiment according to the third aspect of the invention we
Organization Chart.In this embodiment, before, during and after the driver element circuit in visible area 200 ' is divided into
Driver element circuit region 200-1 marked in three regions of section, such as figure includes leading portion driver element
GOP_F, driver element circuit region 200-2 include stage casing driver element GOP_M and driver element electricity
Road area 200-3 includes back segment driver element GOP_E.Each driver element circuit region is believed using different clocks
Number driving.For example, driver element circuit region 200-1 is by first group of clock signal CKA_F and CKB_F
Driving, driver element circuit region 200-2 is driven by second group of clock signal CKA_M and CKB_M,
Driver element circuit region 200-3 is driven by the 3rd group of clock signal CKA_E and CKB_E, that will post
Raw capacitor averaging is distributed in three groups of clock cables.
Figure 21 is to show the signal waveforms described in first embodiment according to the third aspect of the invention we.Root
According to the concept of the third aspect of the present invention, the clock that different driver element circuit regions is configured into different groups is believed
Number, and timing controller of arranging in pairs or groups provides the clock signal of timesharing, can effectively reduce clock cable institute
The parasitic capacitance experienced only original 1/3rd.
In particular, the clock signal of different groups can be distributed in different time output clock pulses,
To drive the driver element in corresponding driver element circuit region.By taking the framework shown in Figure 20 as an example, three
Group clock signal can export clock pulses as shown in figure 21 in the way of timesharing in the different time.Driving
The interval that moving cell circuit region 200-3 need to be operated, clock signal CKA_E and CKB_E can export clock
Pulse, now, clock signal CKA_M and CKB_M and CKA_F and CKB_F state are
Without output.For example, clock signal CKA_M and CKB_M and CKA_F and CKB_F voltage
Level is pulled low to reference voltage VGL level.Drivings at different levels in driver element circuit region 200-3
Unit is sequentially operated and finished, and the driver elements at different levels in driver element circuit region 200-2 can be operated sequentially.
Now, clock signal CKA_M and CKB_M can export clock pulses, clock signal CKA_E with
CKB_E state will be converted to no output.For example, clock signal CKA_E and CKB_E and
CKA_F and CKB_F voltage level is pulled low to reference voltage VGL level.When driver element electricity
Driver elements at different levels in road area 200-2, which are sequentially operated, to be finished, at different levels in driver element circuit region 200-1
Driver element can be operated sequentially.Now, clock signal CKA_F and CKB_F can export clock pulses,
Clock signal CKA_M and CKB_M state will be converted to no output.For example, clock signal
CKA_E and CKB_E and CKA_M and CKB_M voltage level is pulled low to reference voltage
VGL level.Consequently, it is possible to the parasitic capacitance experienced of clock cable only original 1/3rd.
Though it is worth noting that, in the above-described embodiments, to fairly set out idea of the invention, it will drive
Element circuit is divided into three regions, but the present invention is not limited thereto.Those skilled in the art, are not taking off
From in the spirit and scope of the present invention, when a little change and retouching can be done, for example, driver element circuit is drawn
It is divided into two regions, or the region of more than three.In addition, the dividing mode of driver element circuit is not also limited
Before, during and after above-mentioned or the dividing mode of left, center, right.
Furthermore it is noted that though in the above-described embodiments, each driver element circuit region is coupled to two
Bar clock cable is to receive corresponding clock signal, but the present invention is not limited thereto.In its of the present invention
In his embodiment, each driver element circuit region can also be respectively coupled to as shown in Figure 11 A more than two when
Clock signal wire, such as driver element GOP shown in Figure 11 A can be considered as in same driver element circuit region
Driver element, the driver element in this driver element circuit region be respectively coupled to clock cable CKA,
CKB, CKC and CKD, and can order persistent loop according to this, to reduce transistor in visible area
Work period.
Furthermore it is noted that the concept that the third aspect of the present invention is introduced can be applied not only to this
All elements for the gate driving circuit that the first aspect embodiment of invention is introduced are arranged on display
Framework in the visible area of panel, can also be applied to that the second aspect of the present invention embodiment introduced by grid
The subelement of pole drive circuit is arranged on the framework in the rim area of display pannel, includes such as Figure 13 A
The shown transistor couples being arranged on the transistor AND gate for being arranged on rim area in visible area to it is different when
The embodiment framework of clock signal wire, as shown in 14A, 15A and 15B figure will be arranged on rim area
Transistor AND gate be arranged on the transistor couples in visible area to identical clock cable embodiment framework,
And the increase shown in 16A, 16B and 16C figure is supplied to the clock for the element for being arranged on rim area to believe
Number quantity embodiment framework.
In other words, in the clock signal sequence configuration method that the third aspect of the present invention is proposed, knot
Each group clock signal zone configuration is closed, and the distribution of each group clock signal exports clock arteries and veins in the different time
The technology of punching, the driver element circuit region that each group clock signal is only responsible at itself has output when need to operate,
Remaining time maintains its voltage in reference voltage VGL level without exporting.Consequently, it is possible to can not only have
The parasitic capacitance that effect reduction clock cable is experienced, can more save power dissipation, can also reduce driving
The time that transistor unit is biased in unit, it is effectively increased circuit reliability.In addition, clock signal
Time without output can also avoid gate drive signal from producing unnecessary ripple.For example, can avoid such as figure
Gate drive signal GOUT shown in 22, can be because of clock cable CLK when being not necessary to produce pulse
Clock pulses output and produce ripple 2201.
In claims this is used to ordinal numbers such as " first ", " second ", " the 3rd " of modified elements
Body is not implied performed by precedence or method between any priority, order of priority, each element
The order of step, and be used only as identifying distinguishing the difference member with same names (there are different ordinal numbers)
Part.
Although the present invention is disclosed as above with preferred embodiment, so it is not limited to the present invention, ability
Field technique personnel without departing from the spirit and scope of the present invention, when can do it is a little change with retouching, therefore
Protection scope of the present invention is worked as to be defined depending on appended claims confining spectrum.
Claims (17)
1. a kind of display pannel, including：
Substrate；
Multiple data wires；
Multiple gate lines；
Power line, couples voltage source；And
Gate driving circuit, is arranged in the visible area of the display pannel, be coupled to the gate line with
The power line, and multiple gate drive signals are produced according to initial pulse,
Wherein described gate line is formed by the first metal layer on the substrate, the data wire by positioned at
Second metal layer above the first metal layer is formed, and the power line is by above the second metal layer
3rd metal level is formed, and at least one view field on the substrate of the data wire and the electricity
The view field of source line on the substrate is overlapping.
2. display pannel as claimed in claim 1, in addition to multiple clock cables, are coupled to this
Gate driving circuit, to provide multiple clock signals, wherein the clock cable is by first metal
Layer is formed, and parallel with the gate line.
3. display pannel as claimed in claim 1, in addition to multiple clock cables, are coupled to this
Gate driving circuit, to provide multiple clock signals, wherein the clock cable is by second metal
Layer is formed, and the clock cable is parallel with the data wire.
4. display pannel as claimed in claim 1, in addition to multiple clock cables, are coupled to this
Gate driving circuit, to provide multiple clock signals, wherein the clock cable is by the 3rd metal
Layer is formed, and the clock cable is parallel with the power line, and the data wire at least one at this
The view field's weight of at least one of view field on substrate and the clock cable on the substrate
It is folded.
5. display pannel as claimed in claim 1, the wherein gate driving circuit include N grades of drivings
Unit, and wherein n-th grade driver element include：
The first transistor, the first clock cable is coupled to the first pole, and the second pole is coupled to
N bar gate lines；
Second transistor, (n-1) article gate line, and the second pole are coupled to control pole and the first pole
Couple the control pole of the first transistor；And
Third transistor, (n+1) article gate line is coupled to control pole, the first pole be coupled to this second
Second pole of transistor, and the second pole are coupled to the power line,
Wherein n and N are positive integer, and 0<n≦N.
6. display pannel as claimed in claim 5, wherein n-th grade of driver element also include：
4th transistor, second clock signal wire is coupled to control pole, and the first pole is coupled to nth bar
Gate line, and the second pole are coupled to the power line.
7. display pannel as claimed in claim 5, in addition to：
4th transistor, second clock signal wire is coupled to control pole, and the first pole is coupled to nth bar
Gate line, and the second pole are coupled to the power line,
Wherein the 4th transistor is arranged in the rim area of the display pannel.
8. a kind of display pannel, including：
Multiple gate lines；
Multiple clock cables, to provide multiple clock signals；And
Gate driving circuit, is arranged in the visible area of the display pannel, be coupled to the gate line with
And the clock cable, and multiple gate drive signals are produced according to initial pulse,
Wherein described gate line is formed with the clock cable by the first metal layer on substrate, and
And the gate line is parallel with the clock cable.
9. display pannel as claimed in claim 8, in addition to：
Substrate；
Power line, couples voltage source；And
Multiple data wires,
Wherein described data wire is formed by the second metal layer above the first metal layer, the power line
Formed by the 3rd metal level above the second metal layer, and the data wire at least one
View field of the view field with the power line on the substrate on the substrate is overlapping.
10. display pannel as claimed in claim 9, the wherein gate driving circuit include N grades of drivings
Unit, and wherein n-th grade driver element include：
The first transistor, the first clock cable is coupled to the first pole, and the second pole is coupled to
N bar gate lines；
Second transistor, (n-1) article gate line, and the second pole are coupled to control pole and the first pole
Couple the control pole of the first transistor；And
Third transistor, (n+1) article gate line is coupled to control pole, the first pole be coupled to this second
Second pole of transistor, and the second pole are coupled to the power line,
Wherein n and N are positive integer, and 0<n≦N.
11. display pannel as claimed in claim 10, wherein n-th grade of driver element also include：
4th transistor, second clock signal wire is coupled to control pole, and the first pole is coupled to nth bar
Gate line, and the second pole are coupled to the power line.
12. display pannel as claimed in claim 10, in addition to：
4th transistor, second clock signal wire is coupled to control pole, and the first pole is coupled to nth bar
Gate line, and the second pole are coupled to the power line,
Wherein the 4th transistor is arranged in the rim area of the display pannel.
13. a kind of display pannel, including：
Multiple data wires；
Multiple gate lines；
Multiple clock cables, to provide multiple clock signals；
Power line, couples voltage source；And
Gate driving circuit, is arranged in the visible area of the display pannel, be coupled to the gate line,
The clock cable and the power line, and multiple gate drive signals are produced according to initial pulse,
Wherein described gate line is formed with the clock cable by the first metal layer, and the gate line
Parallel with the clock cable, the data wire is formed by second metal layer, and the power line is by the 3rd gold medal
Category layer is formed.
14. display pannel as claimed in claim 13, the wherein the first metal layer are formed on substrate,
The second metal layer is formed above the first metal layer, and the 3rd metal level is formed at second gold medal
Belong to above layer, and at least one view field on the substrate of the data wire and the power line exist
View field on the substrate is overlapping.
15. display pannel as claimed in claim 13, the wherein gate driving circuit include N grades of drives
Moving cell, and wherein n-th grade driver element include：
The first transistor, the first clock cable is coupled to the first pole, and the second pole is coupled to
N bar gate lines；
Second transistor, (n-1) article gate line, and the second pole are coupled to control pole and the first pole
Couple the control pole of the first transistor；And
Third transistor, (n+1) article gate line is coupled to control pole, the first pole be coupled to this second
Second pole of transistor, and the second pole are coupled to the power line,
Wherein n and N are positive integer, and 0<n≦N.
16. display pannel as claimed in claim 15, wherein n-th grade of driver element also include：
4th transistor, second clock signal wire is coupled to control pole, and the first pole is coupled to nth bar
Gate line, and the second pole are coupled to the power line.
17. display pannel as claimed in claim 15, in addition to：
4th transistor, second clock signal wire is coupled to control pole, and the first pole is coupled to nth bar
Gate line, and the second pole are coupled to the power line,
Wherein the 4th transistor is arranged in the rim area of the display pannel.
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| CN109870838A (en) * | 2017-12-05 | 2019-06-11 | 夏普株式会社 | Display device with touch panel |
| US10726758B2 (en) | 2018-12-04 | 2020-07-28 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel |
| WO2021031280A1 (en) * | 2019-08-20 | 2021-02-25 | Tcl华星光电技术有限公司 | Gate driver on array-type display panel |
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| CN103278984A (en) * | 2012-12-27 | 2013-09-04 | 上海天马微电子有限公司 | Thin film transistor array substrate, display panel and liquid crystal display |
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| WO2015190488A1 (en) * | 2014-06-13 | 2015-12-17 | シャープ株式会社 | Shift-register circuit and display device containing same |
| US20150379955A1 (en) * | 2014-06-30 | 2015-12-31 | Samsung Display Co., Ltd. | Display device |
| CN104503177A (en) * | 2014-12-23 | 2015-04-08 | 上海天马微电子有限公司 | Array substrate, manufacturing method thereof and display panel |
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| CN109870838A (en) * | 2017-12-05 | 2019-06-11 | 夏普株式会社 | Display device with touch panel |
| CN109493726A (en) * | 2018-12-04 | 2019-03-19 | 武汉华星光电半导体显示技术有限公司 | Display panel |
| US10726758B2 (en) | 2018-12-04 | 2020-07-28 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel |
| WO2021031280A1 (en) * | 2019-08-20 | 2021-02-25 | Tcl华星光电技术有限公司 | Gate driver on array-type display panel |
| CN113920943A (en) * | 2020-07-07 | 2022-01-11 | 京东方科技集团股份有限公司 | Display device and manufacturing method thereof |
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