CN107301138B - A kind of universal serial bus bridging method and serial bus system - Google Patents
A kind of universal serial bus bridging method and serial bus system Download PDFInfo
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- CN107301138B CN107301138B CN201710404362.0A CN201710404362A CN107301138B CN 107301138 B CN107301138 B CN 107301138B CN 201710404362 A CN201710404362 A CN 201710404362A CN 107301138 B CN107301138 B CN 107301138B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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Abstract
The invention discloses a kind of universal serial bus bridging method and serial bus systems, which comprises when main controller accesses Serial Peripheral Interface (SPI) host equipment, the CS and CLK signal of the CPLD detection Serial Peripheral Interface (SPI) host equipment；It is to be checked measure the CS signal it is effective when, CPLD to main controller send IRQ interrupt signal, with drive the main controller by data to be sent be written transmitter register；When detecting rising edge every time, data to be sent are sent to Serial Peripheral Interface (SPI) host equipment one by one；After data to be sent are sent, IRQ interrupt signal is sent to main controller, to drive the main controller that transmitter register is written in next data to be sent, and is repeated the above steps until detecting that the CS signal is invalid.The present invention realizes the communication between main equipment and main equipment by CPLD switching, and efficiency of transmission is high and reliability is stablized.
Description
Technical field
The present invention relates to serial bus technology field, in particular to a kind of universal serial bus bridging method and universal serial bus system
System.
Background technique
Serial Peripheral Interface is widely used in embedded device, is generally used for the communication of slow devices, clock frequency one
As at several megahertzs or less.Serial Peripheral Interface system is divided into main equipment and carries out point-to-point communication from equipment, and main equipment generates
Clock signal, from the clock sending and receiving data of equipment utilization main equipment.The host is embedded master cpu, and slave is other outer
Enclose chip.
But when the equipment being connect with master cpu by Serial Peripheral Interface (SPI) can only do main equipment, master cpu is with regard to only
It can do from equipment.However, existing master cpu is not supported generally from equipment mode, and the I/O pin of master cpu may quilt
It occupies and can not achieve from functions of the equipments.
Thus the prior art could be improved and improve.
Summary of the invention
In view of the deficiencies in the prior art, the invention aims to provide a kind of universal serial bus bridging method and universal serial bus
System.
To achieve the goals above, the technical solution adopted in the present invention is as follows:
A kind of universal serial bus bridging method is applied to a programmable logic device (CPLD) comprising following steps:
A, when main controller accesses Serial Peripheral Interface (SPI) host equipment, the CPLD detects Serial Peripheral Interface (SPI) host equipment
CS and CLK signal；
B, it is to be checked measure the CS signal it is effective when, CPLD to main controller send IRQ interrupt signal, to drive the master control
Transmitter register is written in data to be sent by device；
C, when detecting rising edge every time, data to be sent are sent to Serial Peripheral Interface (SPI) host equipment one by one；
D, after data to be sent are sent, to main controller send IRQ interrupt signal, with drive the main controller will under
Transmitter register is written in one data to be sent, and the C and step D that repeats the above steps is until detect that the CS signal is nothing
Effect.
The universal serial bus bridging method, wherein it is described it is to be checked measure the CS signal it is effective when specifically: it is to be checked to measure
The level of the CS signal is low level.
The universal serial bus bridging method, wherein the step C, it is described every time detect rising edge when, will be to be sent
Data are sent to Serial Peripheral Interface (SPI) host equipment one by one and specifically include:
C1, the rising edge for detecting CLK signal；
C2, when detecting the rising edge of CLK signal for the first time, by the data to be sent in transmitter register according to MSB
The mode first sent out sends a bit；
C3, when detecting the rising edge of CLK signal for the second time, by the data to be sent in transmitter register according to MSB
The mode first sent out sends a bit, and so on until transmitter register in data to be sent be sent.
The universal serial bus bridging method, wherein the step C, it is described every time detect rising edge when, will be to be sent
Data are sent to one by one after Serial Peripheral Interface (SPI) host equipment further include:
D01, CPLD read the level signal of the MOSI of Serial Peripheral Interface (SPI) host equipment；
D02, when detecting failing edge every time, receive the data that Serial Peripheral Interface (SPI) is sent, and receive described
Data are saved to receiving register.
The universal serial bus bridging method, wherein the D is specifically included:
D1, when band send data be sent after, CPLD to main controller send IRQ interrupt signal；
Transmitter register is written in next data to be sent by D2, the driving main controller, and write-in register is inscribed
The data copy received is into memory；
D3, the C- step D2 that repeats the above steps are until detect that the CS signal is invalid.
The universal serial bus bridging method, wherein it is described detect that the CS signal is invalid after further include:
The interruption irq signal being transmitted is sent to main controller, drives the main controller to receive transmission, and stop to transmission
Register and the operation that register is written.
The universal serial bus bridging method, wherein the length of the data to be sent is 8 bit.
The universal serial bus bridging method, wherein the length for receiving data is 8 bit, and described to be sent
Data and/or receive data carry protocol information to identify valid data.
A kind of serial bus system comprising main controller, a programmable logic device (CPLD) and at least serial peripheral connects
Mouth host equipment, wherein the CPLD stores a plurality of instruction, and described instruction is suitable for being loaded by processor and being executed any institute as above
State universal serial bus bridging method.
The serial bus system, wherein the master controller is connected by universal serial bus with the CPLD, and described
CPLD provides IRQ interrupt signal for the master controller, and the CPLD passes through MOSI data line, MISO data line, CLK clock line
And CS chip select line is connected with the Serial Peripheral Interface (SPI) host equipment.
The utility model has the advantages that compared with prior art, the present invention provides a kind of universal serial bus bridging method and universal serial bus systems
System, which comprises when main controller accesses Serial Peripheral Interface (SPI) host equipment, the CPLD detects Serial Peripheral Interface (SPI) master
The CS and CLK signal of machine equipment；It is to be checked measure the CS signal it is effective when, CPLD to main controller send IRQ interrupt signal, with drive
It moves the main controller and transmitter register is written into data to be sent；When detecting rising edge every time, one by one by data to be sent
It is sent to Serial Peripheral Interface (SPI) host equipment；After data to be sent are sent, IRQ interrupt signal is sent to main controller, with
It drives the main controller that transmitter register is written in next data to be sent, and repeats the above steps until detecting the CS
Signal is invalid.The present invention realizes communication between main equipment and main equipment by CPLD switching, and efficiency of transmission height with
And reliability is stablized.
Detailed description of the invention
Fig. 1 is the flow chart of universal serial bus bridging method preferred embodiment provided by the invention.
Fig. 2 is the structure principle chart of serial bus system preferred embodiment provided by the invention.
Fig. 3 is the relational graph of Serial Peripheral Interface (SPI) main equipment timing and IRQ provided by the invention.
Specific embodiment
The present invention provides a kind of universal serial bus bridging method and serial bus system, to make the purpose of the present invention, technical side
Case and effect are clearer, clear, and the present invention is described in more detail as follows in conjunction with drawings and embodiments.It should be appreciated that
Described herein specific examples are only used to explain the present invention, is not intended to limit the present invention.
Those skilled in the art of the present technique are appreciated that unless expressly stated, singular " one " used herein, " one
It is a ", " described " and "the" may also comprise plural form.It is to be further understood that being arranged used in specification of the invention
Diction " comprising " refer to that there are the feature, integer, step, operation, element and/or component, but it is not excluded that in the presence of or addition
Other one or more features, integer, step, operation, element, component and/or their group.It should be understood that when we claim member
Part is " connected " or when " coupled " to another element, it can be directly connected or coupled to other elements, or there may also be
Intermediary element.In addition, " connection " used herein or " coupling " may include being wirelessly connected or wirelessly coupling.It is used herein to arrange
Diction "and/or" includes one or more associated wholes for listing item or any cell and all combinations.
Those skilled in the art of the present technique are appreciated that unless otherwise defined, all terms used herein (including technology art
Language and scientific term), there is meaning identical with the general understanding of those of ordinary skill in fields of the present invention.Should also
Understand, those terms such as defined in the general dictionary, it should be understood that have in the context of the prior art
The consistent meaning of meaning, and unless idealization or meaning too formal otherwise will not be used by specific definitions as here
To explain.
With reference to the accompanying drawing, by the description of the embodiment, further explanation of the contents of the invention are made.
Fig. 1 is please referred to, Fig. 1 is the flow chart of the preferred embodiment of universal serial bus bridging method provided by the invention.It is described
Method is applied to a programmable logic device (CPLD), can specifically include:
S100, when main controller accesses Serial Peripheral Interface (SPI) host equipment, the CPLD detects Serial Peripheral Interface (SPI) host
The CS and CLK signal of equipment.
Specifically, the main controller can be embedded master cpu, and the Serial Peripheral Interface (SPI) host equipment can be with master control
The peripheral chip of device.The main controller access Serial Peripheral Interface (SPI) host equipment refers to the main controller and Serial Peripheral Interface (SPI)
SPI transmission is carried out between host equipment.In the present embodiment, the serial peripheral main equipment be host, the main controller be from
Machine.The main controller is connected with the Serial Peripheral Interface (SPI) host equipment by the CPLD；When the main controller is serially outer
If Interface Host equipment, main controller is accessed by local bus, and is sent to after the escape of CPLD to Serial Peripheral Interface (SPI)
Host equipment.
As shown in Fig. 2, the main controller is connected by this ground series bus with the CPLD, and the CPLD is described
Master controller provides IRQ(Interrupt Request, interrupt requests) interrupt signal, the CPLD passes through MOSI(Master
Output Slaver Input, main output is from input) data line, MISO(Master Input Slaver Output, master is defeated
Enter from output) data line, CLK clock line and CS(Chip select, piece choosing) chip select line and the Serial Peripheral Interface (SPI) host
Equipment is connected.For Serial Peripheral Interface (SPI) host equipment to CPLD tranmitting data register signal, the CS piece selects the CLK timeline
Line sends CS chip selection signal to CPLD for Serial Peripheral Interface (SPI) host equipment, and the MISO data line is serially outer for CPLD
If Interface Host equipment sends data；The MOSI data line sends data to CPLD for Serial Peripheral Interface (SPI) main equipment.
The CPLD detects the CS and CLK signal of Serial Peripheral Interface (SPI) main equipment, and institute using the sampling time of 66MHz
The high level for stating the sampling time reads the level of detected signal.The detected signal includes CS signal and CLK signal.
S200, it is to be checked measure the CS signal it is effective when, CPLD to main controller send IRQ interrupt signal, drive the master
It controls device and transmitter register is written into data to be sent.
Specifically, the CS signal effectively refers to that the level of the CS signal is lower, i.e., the level of the described CS signal is
Low level.For example, the high level is 1, low level 0.After the CS signal is effective, the CPLD sends IRQ to main controller
Interrupt signal drives the main controller that transmitter register is written in data to be sent by the IRQ interrupt signal.In this implementation
In, the data to be sent are a byte data.The interrupt signal drives one that main controller will write in transmitter register
A byte data latches for sending.
In one embodiment of the invention, the CPLD sends IRQ interrupt signal, the main controller response to main controller
Interrupt requests remove interrupt signal at first in interrupting ISR program, then the data to be sent write-in of a byte are sent deposit
Device simultaneously locks.The CPLD described in this way can according to the clock signal detected by the data forwarding to be sent of the locking to serial
Peripheral Interface main equipment.
S300, every time detect rising edge when, data to be sent are sent to Serial Peripheral Interface (SPI) host equipment one by one.
Specifically, the first time that the above-mentioned edge of the CLK signal refers to detects that CLK signal is low level, second of detection
It is high level to CLK signal；The failing edge of the CLK signal refers to that first detects that CLK signal is high level, the second detection
It is low level to CLK signal.It is worth explanation, the first time detection refers to the detection twice being connected with the second detection,
The first time is detected as preceding one-time detection, described to be detected as current detection for the second time.
Illustratively, described when detecting rising edge every time, data to be sent are sent to Serial Peripheral Interface (SPI) one by one
Host equipment specifically includes:
S301, the rising edge for detecting CLK signal；
S302, when detecting the rising edge of CLK signal for the first time, by the data to be sent in transmitter register according to
The mode that MSB is first sent out sends a bit；
S303, when detecting the rising edge of CLK signal for the second time, by the data to be sent in transmitter register according to
The mode that MSB is first sent out sends a bit, and so on until transmitter register in data to be sent be sent.
Specifically, the first time, which detects, refers to when the CS signal is effective, and CLK signal rises for the first time
Edge.Described detect for the second time refers to and detects adjacent rising edge for the first time.That is, detecting that CLK believes every time
When number there is rising edge, connect to the data of a bit of the data to be sent in transmitter register are sent to serial peripheral
Mouth main equipment.In the present embodiment, one byte (8bit) with send data sent out in such a way that MSB is first sent out
It send, that is to say, that sent in such a way that most significant bit is first sent out.It, can be in the variant embodiment of the present embodiment
Sent using other modes, for example, using LSB(least significant bit) first send out by the way of etc..
In one embodiment of the invention, the data of main controller are sent to Serial Peripheral Interface (SPI) main equipment by the CPLD
While, the data that Serial Peripheral Interface (SPI) main equipment is sent also are received, and the data received are sent to main control device.
Correspondingly, it is described every time detect rising edge when, by data to be sent be sent to one by one Serial Peripheral Interface (SPI) host equipment it
Afterwards further include:
S041, CPLD read the level signal of the MOSI of Serial Peripheral Interface (SPI) host equipment；
S042, when detecting failing edge every time, receive the data that Serial Peripheral Interface (SPI) is sent, and receive described
Data are saved to receiving register.
Specifically, the CPLD receives the data to be sent of data and CPLD transmission main controller that Serial Peripheral Interface (SPI) is sent
Mode it is identical, and every time handle a bit.That is, working as CPLD main controller is written in transmitter register one
While a bit data are sent to Serial Peripheral Interface (SPI) main equipment, the bit number that Serial Peripheral Interface (SPI) main equipment is sent is received
According to, and receive a bit data are stored in write-in register.When the 8bit data in transmitter register are all sent
When to Serial Peripheral Interface (SPI) main equipment, is written in register and is written into 8bit data.In practical applications, the band sends data
And/or it receives in data and can effectively be identified with protocol information, the protocol information using 0xe7 as data.Described two
Data between a 0xe7 are all valid data, other then invalid, can send and receive the data of different length simultaneously in this way.
S400, after data to be sent are sent, to main controller send IRQ interrupt signal, to drive the main controller
Transmitter register is written into next data to be sent, and the C and step D that repeats the above steps is until detect that the CS signal is
In vain.
Specifically, the data to be sent are sent a byte 8bit data for referring to locking in transmitter register
It is sent.At this point, the CPLD sends IRQ interrupt signal to main controller.Correspondingly, the master cpu responds interrupt requests,
Remove interrupt signal at first in interrupting ISR program, and transmitter register is written in the data to be sent of next byte, while will write
Enter the 8bit data copy of register into memory.Data in transmitting data register are latched by the CPLD again,
Prepare the transmission of next byte.
Illustratively, after the data to be sent are sent, IRQ interrupt signal is sent to main controller, described in driving
Transmitter register is written in next data to be sent by main controller, and the C and step S400 that repeats the above steps is until detect institute
Stating CS signal is to specifically include in vain:
S401, when band send data be sent after, CPLD to main controller send IRQ interrupt signal；
Transmitter register is written in next data to be sent by S402, the driving main controller, and will be written in register
The data copy received is into memory；
S403, the S300- step S402 that repeats the above steps are until detect that the CS signal is invalid.
Specifically, drive the main controller by next band send data write-in transmitter register before can also judge be
No there are next data to be sent, and transmitter register then is written in next data to be sent if there is data to be sent,
If there is no data to be sent, end of transmission.
In another embodiment of the present invention, it is described detect that the CS signal is invalid after further include:
S500, the interruption irq signal being transmitted is sent to main controller, drive the main controller to receive transmission, and stop
Operation to transmitter register and write-in register.
Specifically, the CPLD, which detects CS chip selection signal and draws high, becomes invalid, and expression is this time transmitted.At this point,
The CPLD no longer detects clock signal, and is transmitted to main controller transmission and interrupts IRQ, and main controller responds interrupt requests,
Interrupt signal is removed, end is this time transmitted, and data no longer are written to transmitter register, is not also saving reception data.
Universal serial bus bridging method in order to further illustrate the present invention, below with reference to Serial Peripheral Interface (SPI) main equipment timing
The process that data send and receive data is illustrated with the relational graph of IRQ.
As shown in figure 3, CPLD detects that CS signal is lower effectively in 1 position, drive main controller into transmitter register
A byte data is written and latches；
In 2 position, CPLD detects that CLK signal becomes high rising edge by low, and the data in transmitter register are pressed
The mode that MSB is first sent out sends 1bit, and sends 1bit until 8bit is sent when often detecting a rising edge clock；
Simultaneously during transmission, reads the level height of MOSI and receive 8bit data, and the preservation of 8bit data will be received
To write-in register；
In 3 position, CPLD sends byte transmission to master cpu and completes to interrupt, and irq signal is lower；In master cpu response
Disconnected request, removes interrupt signal in interrupting ISR program at first, and the pending of next 8bit is written and transmits data to transmission deposit
Device, and copy 8bit numerical value in memory to from write-in register；
In 4 position, the operating procedure of 3 positions is repeated；
In 5 position, CPLD, which detects CS chip selection signal and draws high, becomes invalid, and CPLD no longer detects clock signal, and
And it is transmitted to master cpu transmission and interrupts IRQ；Master cpu responds interrupt requests, removes interrupt signal, terminates this time to transmit.
It is worth explanation, when the byte that transmit 2 or more, it is only necessary to repeat the operation of 3 positions.For transmitting data
Length, be not particularly limited here.
The present invention also provides a kind of serial bus systems, as shown in Figure 2 comprising main controller, a programmable logic device
Part CPLD and at least Serial Peripheral Interface (SPI) host equipment, the master controller are connected by universal serial bus with the CPLD,
And the CPLD provides IRQ interrupt signal for the master controller, the CPLD passes through MOSI data line, MISO data line, CLK
Clock line and CS chip select line are connected with the Serial Peripheral Interface (SPI) host equipment.The CPLD stores a plurality of instruction, described
Instruction is suitable for being loaded by processor and being executed any universal serial bus bridging method as above.
The modules of above-mentioned serial bus system have been described in detail in the above-mentioned methods, just no longer old one by one herein
It states.
In embodiment provided by the present invention, it should be understood that disclosed system and method can pass through others
Mode is realized.For example, the apparatus embodiments described above are merely exemplary, for example, the division of the module, only
A kind of logical function partition, there may be another division manner in actual implementation, for example, multiple units or components can combine or
Person is desirably integrated into another system, or some features can be ignored or not executed.Another point, shown or discussed is mutual
Between coupling, direct-coupling or communication connection can be through some interfaces, the INDIRECT COUPLING or communication link of device or unit
It connects, can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated list
Member both can take the form of hardware realization, can also realize in the form of hardware adds SFU software functional unit.
The above-mentioned integrated unit being realized in the form of SFU software functional unit can store and computer-readable deposit at one
In storage media.Above-mentioned SFU software functional unit is stored in a storage medium, including some instructions are used so that a computer
It is each that equipment (can be personal computer, server or the network equipment etc.) or processor (processor) execute the present invention
The part steps of embodiment the method.And storage medium above-mentioned includes: USB flash disk, mobile hard disk, read-only memory (Read-
Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic or disk etc. it is various
It can store the medium of program code.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: it still may be used
To modify the technical solutions described in the foregoing embodiments or equivalent replacement of some of the technical features；
And these are modified or replaceed, technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (9)
1. a kind of universal serial bus bridging method is applied to a programmable logic device (CPLD), which is characterized in that it includes following step
It is rapid:
A, when main controller accesses Serial Peripheral Interface (SPI) host equipment, the CS of the CPLD detection Serial Peripheral Interface (SPI) host equipment
And CLK signal；
B, it is to be checked measure the CS signal it is effective when, CPLD sends IRQ interrupt signal to main controller, to drive the main controller will
Transmitter register is written in data to be sent；
C, when detecting rising edge every time, data to be sent are sent to Serial Peripheral Interface (SPI) host equipment one by one；
It is described every time detect rising edge when, data to be sent are sent to Serial Peripheral Interface (SPI) host equipment one by one and are specifically wrapped
It includes:
C1, the rising edge for detecting CLK signal；
C2, when detecting the rising edge of CLK signal for the first time, the data to be sent in transmitter register are first sent out according to MSB
Mode send a bit；
C3, when detecting the rising edge of CLK signal for the second time, the data to be sent in transmitter register are first sent out according to MSB
Mode send a bit, and so on until transmitter register in data to be sent be sent；
D, after data to be sent are sent, IRQ interrupt signal is sent to main controller, to drive the main controller will be next
Transmitter register is written in data to be sent, and the C and step D that repeats the above steps is until detect that the CS signal is invalid.
2. universal serial bus bridging method according to claim 1, which is characterized in that described to be checked to measure the CS signal effective
When specifically: the level to be checked for measuring the CS signal is low level.
3. universal serial bus bridging method according to claim 1, which is characterized in that the step C, described detecting every time
When rising edge, data to be sent are sent to one by one after Serial Peripheral Interface (SPI) host equipment further include:
D01, CPLD read the level signal of the MOSI of Serial Peripheral Interface (SPI) host equipment；
D02, every time detect failing edge when, receive Serial Peripheral Interface (SPI) send data, and by the data received save
To receiving register.
4. universal serial bus bridging method according to claim 3, which is characterized in that the D is specifically included:
D1, after data to be sent are sent, CPLD to main controller send IRQ interrupt signal；
Transmitter register is written in next data to be sent by D2, the driving main controller, and will be received in write-in register
Data copy into memory；
D3, the C- step D2 that repeats the above steps are until detect that the CS signal is invalid.
5. according to claim 1 or the 4 universal serial bus bridging methods, which is characterized in that described to detect that the CS signal is
After invalid further include:
The interruption irq signal being transmitted is sent to main controller, the main controller is driven to receive transmission, and stops depositing transmission
Device and the operation that register is written.
6. according to any universal serial bus bridging method of claim 3-4, which is characterized in that the length of the data to be sent
For 8 bit.
7. universal serial bus bridging method according to claim 6, which is characterized in that the length of the data received is 8
A bit, and the data to be sent and/or the data received carry protocol information to identify valid data.
8. a kind of serial bus system comprising main controller, a programmable logic device (CPLD) and at least Serial Peripheral Interface (SPI)
Host equipment, which is characterized in that the CPLD stores a plurality of instruction, and described instruction is suitable for being loaded by processor and being executed such as right
It is required that any universal serial bus bridging method of 1-6.
9. serial bus system according to claim 8, which is characterized in that the main controller by universal serial bus with it is described
CPLD is connected, and the CPLD provides IRQ interrupt signal for the main controller, and the CPLD passes through MOSI data line, MISO
Data line, CLK clock line and CS chip select line are connected with the Serial Peripheral Interface (SPI) host equipment.
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| CN109902053B (en) * | 2017-12-07 | 2022-07-05 | 厦门雅迅网络股份有限公司 | SPI communication method based on double controllers, terminal equipment and storage medium |
| CN109581927A (en) * | 2018-12-07 | 2019-04-05 | 庸博（厦门）电气技术有限公司 | The serial communication method and servo-driver of servo-driver |
| CN110334046A (en) * | 2019-07-11 | 2019-10-15 | 南方电网科学研究院有限责任公司 | SPI full-duplex communication method, device and system |
| CN110554984B (en) * | 2019-07-26 | 2023-11-03 | 深圳震有科技股份有限公司 | CPLD-based serial port bridging method and system |
| CN110765058A (en) * | 2019-09-12 | 2020-02-07 | 深圳震有科技股份有限公司 | Method, system, equipment and medium for realizing SPI slave function by GPIO |
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