CN107256458A - The performance yields optimization method and device of a kind of multiprocessor systems on chips - Google Patents
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Abstract
This application discloses the performance yields optimization method and device of a kind of multiprocessor systems on chips.This method recognizes ready task and ready processing core under current scheduled time node first, and then determine the task priority of all ready tasks, and the order according to priority from high to low, the corresponding optimal core of each ready task is determined based on performance yields.Compared with prior art, the present invention is scheduled according to the height of task priority to ready task, so that it is determined that the corresponding optimal core of each task, improves multiprocessor systems on chips performance yields.
Description
Technical field
The application is related to semiconductor applications, more specifically to a kind of performance yields of multiprocessor systems on chips
Optimization method and device.
Background technology
With the continuous reduction of transistor feature size, the process deviation introduced in chip manufacturing proces is also increasingly serious,
Sternness is brought to choose to multiprocessor systems on chips (Multi-Processor System-on-Chip, MPSoC, MPSoC) design
War.Under process deviation influence, the performance parameter (such as frequency, power consumption) of MPSoC press-on-a-chips core is often deviated from after manufacture
Rated value specified by design phase and it should be considered as stochastic variable.Thus, for volume production MPSoC chips, handle core
The performance parameter of core shows as statistical distribution.Accordingly, the parameter such as execution time of task performed by MPSoC is equally provided with generally
Rate feature.The uncertainty of this execution time can not ensure that the execution of program can meet system at various process corners
Real-time is constrained.From the point of view of Statistics, this will disclosure satisfy that system real time in MPSoC chips for substantially reducing batch production
Ratio shared by the chip of constraint, that is, reduce the performance yields of multiprocessor systems on chips.
The content of the invention
In view of this, the application provides a kind of the performance yields optimization method and device of multiprocessor systems on chips, with
Realize the optimization of multiprocessor systems on chips performance yields.
To achieve these goals, it is proposed that scheme it is as follows：
A kind of performance yields optimization method of multiprocessor systems on chips, including：
Step A：Obtain current scheduled time node；
Step B：Recognize multiple ready tasks and multiple ready processing cores under the current scheduled time node；
Step C：Determine the task priority of all ready tasks；
Step D：According to task priority to high to Low order, it is determined that the corresponding optimal processing core of each ready task
Core, the ready task is one-to-one relationship with the optimal processing core.
It is preferred that, it is described according to task priority to high to Low order, it is determined that each ready task is corresponding optimal
Core is handled, is also included afterwards：
Step E：Judge whether all tasks are scheduled, if otherwise updating scheduling time node, circulation execution step A,
Step B, step C and step D；
If so, then exporting task scheduling approach.
It is preferred that, the task priority for determining all ready tasks, including：
Recognize the mission critical in the ready task；
Based on preset formulaCalculate appointing for all ready tasks
Business priority；
Wherein, K is the constant more than 1；CtaskFor a binary variable, whether expression task is mission critical, for
Mission critical, CtaskValue is 1, conversely, value is 0；VlatencyExpression task performs the side of delay on all processing cores
Difference；AlatencyExpression task performs the average of delay on all processing cores.
It is preferred that, it is described according to task priority to high to Low order, it is determined that each ready task is corresponding optimal
Core is handled, including：
Step D1：Determine the limit priority task in all ready tasks；
Step D2：Calculate performance yields of the limit priority task scheduling to all processing cores；
Step D3：It regard the maximum processing core of performance yields as the corresponding optimal processing of the limit priority task
Core；
Step D4：The limit priority task and optimal processing core are rejected from ready task and ready processing core
Core, to update the ready task and the processing core；
Step D5：Circulation performs step D1 to step D4, until completing the scheduling of all ready tasks.
A kind of performance yields optimization device of multiprocessor device on-chip system, including：
Timing node acquiring unit, for obtaining current scheduled time node；
Recognition unit, for recognizing multiple ready tasks and multiple ready processing under the current scheduled time node
Core；
Priority determining unit, the task priority for determining all ready tasks；
Scheduling unit, for according to task priority to high to Low order, it is determined that each ready task is corresponding most
Excellent processing core, the ready task is one-to-one relationship with the optimal processing core.
It is preferred that, in addition to：
Judging unit, for judging whether all tasks are scheduled, if scheduling time node is otherwise updated, with to residue
Task be scheduled, if so, then exporting task scheduling approach.
It is preferred that, the priority determining unit includes：
Mission critical identification module, for recognizing the mission critical in the ready task；
First computing module, for based on preset formula Ptask=(1+KCtask)·Vlatency·AlatencyCalculate all
The task priority of ready task；
Wherein, K is the constant more than 1；CtaskFor a binary variable, whether expression task is mission critical, for
Mission critical, CtaskValue is 1, conversely, value is 0；VlatencyExpression task performs the side of delay on all processing cores
Difference；AlatencyExpression task performs the average of delay on all processing cores.
It is preferred that, the scheduling unit includes：
Limit priority task determining module, for determining the limit priority task in all ready tasks；
Second computing module, for calculating performance non-defective unit of the limit priority task scheduling to all processing cores
Rate；
Handle core and choose module, for regarding the maximum processing core of performance yields as the limit priority task
Corresponding optimal processing core；
Data update module, for rejected from ready task and ready processing core the limit priority task and
Optimal processing core, to update the ready task and the processing core.
Through as shown from the above technical solution, this application discloses a kind of optimization of the performance yields of multiprocessor systems on chips
Method and apparatus.This method recognizes ready task and ready processing core under current scheduled time node first, and then determines
The task priority of all ready tasks, and the order according to priority from high to low, are determined each just based on performance yields
The corresponding optimal core of thread task.Compared with prior art, the present invention is carried out according to the height of task priority to ready task
Scheduling, so that it is determined that the corresponding optimal core of each task, improves multiprocessor systems on chips performance yields.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
Fig. 1 shows a kind of performance yields optimization side of multiprocessor systems on chips disclosed in one embodiment of the invention
The schematic flow sheet of method；
Fig. 2 shows a kind of schematic flow sheet of ready task dispatching method disclosed by the invention；
Fig. 3 shows a kind of performance yields optimization of multiprocessor systems on chips disclosed in another embodiment of the present invention
The structure of device.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.Based on this
Embodiment in invention, the every other reality that those of ordinary skill in the art are obtained under the premise of creative work is not made
Example is applied, the scope of protection of the invention is belonged to.
Show that a kind of performance yields of multiprocessor systems on chips disclosed in one embodiment of the invention is excellent referring to Fig. 1
The schematic flow sheet of change method.
In the present embodiment, this method includes：
Step A：Obtain current scheduled time node.
Step B：Recognize multiple ready tasks and multiple ready processing cores under the current scheduled time node.
The ready task refer to the current scheduled time node task it is all before take over sb.'s job business completed scheduling and
Perform completion.Ready processing core refers to the current scheduled time node processing core in idle condition, appoints without pending
Business.
Step C：Determine the task priority of all ready tasks.
To achieve these goals, the mission critical first in identification mission figure.So-called mission critical refers to these
Business, which is dispatched on different processing cores, to produce large effect to performance yields.Because circuit topological structure is with communicating
Task image can inherently be abstracted into directed acyclic graph, therefore can application circuit statistical timing analysis theory progress task image
Analysis, recognizes mission critical.Statistical timing analysis is carried out to task image to recognize statistics critical path, and it is crucial logical positioned at statistics
Task on road can then regard mission critical as.
On this basis, task priority is represented using equation below：
Ptask=(1+KCtask)·Vlatency·Alatency
In formula, K is the constant more than 1.CtaskFor a binary variable, whether expression task is mission critical.It is right
In mission critical, CtaskValue is 1；Conversely, value is 0.VlatencyExpression task performs the side of delay on all processing cores
Difference.The parameter value is bigger, represents that execution delay variance of the task on different disposal core is bigger, it should priority scheduling.
AlatencyExpression task performs the average of delay on all processing cores.The parameter value is bigger, when representing the execution of task
Between surplus (slack) it is smaller, then the influence for performance yields is bigger, answers priority scheduling.
Step D：According to task priority to high to Low order, each ready task pair is determined based on performance yields
The optimal processing core system answered.
Specifically, showing a kind of schematic flow sheet of ready task dispatching method disclosed by the invention referring to Fig. 2.The party
Method includes：
Step D1：Determine the limit priority task in all ready tasks.
Step D2：Calculate performance yields of the limit priority task scheduling to all processing cores.
Step D3：It regard the maximum processing core of performance yields as the corresponding optimal processing of the limit priority task
Core.
Step D4：The limit priority task and optimal processing core are rejected from ready task and ready processing core
Core, to update the ready task and the processing core.
Step D5：Circulation performs step D1 to step D4, until completing the scheduling of all ready tasks.
Step E：Judge whether all tasks are scheduled, if otherwise updating scheduling time node, circulation execution step A,
Step B, step C and step D, until all tasks have been scheduled, and output scheduling scheme.
As seen from the above embodiment, present embodiment discloses this application discloses this application discloses a kind of multiprocessor piece
The performance yields optimization method of upper system.This method recognizes ready task and ready place under current scheduled time node first
Core is managed, and then determines the task priority of all ready tasks, and the order according to priority from high to low, it is good based on performance
Product rate determines the corresponding optimal core of each ready task.Compared with prior art, the height of the invention according to task priority
Ready task is scheduled, so that it is determined that the corresponding optimal core of each task, improves multiprocessor systems on chips performance
Yields.It should be noted that driver needs the operation to navigator's vehicle based on the operation with the vehicle that navigates in actual applications
It is adjusted, to ensure the security in logistics transportation.Thus in other embodiment disclosed by the invention, navigator's vehicle is also needed
Receive with boat vehicle with boat message (with boat message include it is described with the positional information for the vehicle that navigates, travel condition information and
Vehicle's contour information), to aid in driver to be controlled navigator's vehicle.
A kind of performance yields of multiprocessor systems on chips disclosed in another embodiment of the present invention is shown referring to Fig. 3
Optimize the structure of device.
In the present embodiment, the device includes：Timing node acquiring unit 1, recognition unit 2, priority determining unit 3,
Scheduling unit 4 and judging unit 5.
Wherein, timing node acquiring unit 1 is used to obtain current scheduled time node.
The scheduling time node that recognition unit 2 is obtained based on timing node acquiring unit, is recognized in current scheduled time section
Multiple ready tasks and multiple ready processing cores under point.
It should be noted that the ready task refer to the current scheduled time node task it is all before taken over sb.'s job business
Through completing to dispatch and performing completion.Ready processing core refers to the current scheduled time node processing core in idle condition, does not have
There is pending task.
Priority determining unit 3 is used for the task priority for determining all ready tasks.
Specifically, the priority determining unit 3 includes：The computing module 32 of mission critical identification module 31 and first.
Mission critical identification module 31 is used to recognize the mission critical in the ready task.
So-called mission critical refers to produce performance yields in these task schedulings to different processing cores
Large effect.Because circuit topological structure and communication task figure can inherently be abstracted into directed acyclic graph, therefore can
The theory carry out task map analysis of application circuit statistical timing analysis, recognizes mission critical.Statistical timing analysis is carried out to task image
To recognize statistics critical path, and the task on statistics critical path can then regard mission critical as.
First computing module 32, for based on preset formula Ptask=(1+KCtask)·Vlatency·AlatencyCalculate institute
There is the task priority of ready task.
Wherein, K is the constant more than 1；CtaskFor a binary variable, whether expression task is mission critical, for
Mission critical, CtaskValue is 1, conversely, value is 0；VlatencyExpression task performs the side of delay on all processing cores
Difference；AlatencyExpression task performs the average of delay on all processing cores.
Scheduling unit 4, for, to high to Low order, being determined each just based on performance yields according to task priority
The corresponding optimal processing core of thread task.
Specifically, the scheduling unit 4 includes：Limit priority task determining module 41, the second computing module 42, processing core
Core chooses module 43 and data update module 44.
Wherein, limit priority task determining module 41 is used to determine the limit priority task in all ready tasks.
Second computing module 42 is good for calculating performances of the limit priority task scheduling to all processing cores
Product rate.
Handle core and choose module 43 for being used as the limit priority to appoint the maximum processing core of performance yields
It is engaged in corresponding optimal processing core；
Data update module 43 be used for rejected from ready task and ready processing core the limit priority task with
And optimal processing core, to update the ready task and the processing core.And then, limit priority task determining module 41
From new selection task priority highest task from remaining ready task, until all ready tasks have realized scheduling.
Judging unit 5 is used to judge whether all tasks are scheduled, if scheduling time node is otherwise updated, with to residue
Task be scheduled, if so, then exporting task scheduling approach.
It should be noted that the system embodiment is corresponding with embodiment of the method, its implementation procedure is identical with principle is performed,
Therefore not to repeat here.
Finally, in addition it is also necessary to explanation, herein, such as first and second or the like relational terms be used merely to by
One entity or operation make a distinction with another entity or operation, and not necessarily require or imply these entities or operation
Between there is any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant meaning
Covering including for nonexcludability, so that process, method, article or equipment including a series of key elements not only include that
A little key elements, but also other key elements including being not expressly set out, or also include be this process, method, article or
The intrinsic key element of equipment.In the absence of more restrictions, the key element limited by sentence "including a ...", is not arranged
Except also there is other identical element in the process including the key element, method, article or equipment.
The embodiment of each in this specification is described by the way of progressive, and what each embodiment was stressed is and other
Between the difference of embodiment, each embodiment identical similar portion mutually referring to.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or using the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and principles disclosed herein and features of novelty phase one
The most wide scope caused.
Claims (8)
1. a kind of performance yields optimization method of multiprocessor systems on chips, it is characterised in that including：
Step A：Obtain current scheduled time node；
Step B：Recognize multiple ready tasks and multiple ready processing cores under the current scheduled time node；
Step C：Determine the task priority of all ready tasks；
Step D：According to task priority to high to Low order, determine that each ready task is corresponding based on performance yields
Optimal processing core, the ready task is one-to-one relationship with the optimal processing core.
2. according to the method described in claim 1, it is characterised in that it is described according to task priority to high to Low order,
It is determined that the corresponding optimal processing core of each ready task, also includes afterwards：
Step E：Judge whether all tasks are scheduled, if otherwise updating scheduling time node, circulation performs step A, step
B, step C and step D；
If so, then exporting task scheduling approach.
3. according to the method described in claim 1, it is characterised in that the task priority for determining all ready tasks, bag
Include：
Recognize the mission critical in the ready task；
Based on preset formulaThe calculating all ready tasks of the task is excellent
First level；
Wherein, K is the constant more than 1；CtaskFor a binary variable, whether expression task is mission critical, is appointed for key
Business, CtaskValue is 1, conversely, value is 0；VlatencyExpression task performs the variance of delay on all processing cores；
AlatencyExpression task performs the average of delay on all processing cores.
4. according to the method described in claim 1, it is characterised in that it is described according to task priority to high to Low order,
The corresponding optimal processing core of each ready task is determined based on performance yields, including：
Step D1：Determine the limit priority task in all ready tasks；
Step D2：Calculate performance yields of the limit priority task scheduling to all processing cores；
Step D3：It regard the maximum processing core of performance yields as the corresponding optimal processing core of the limit priority task
Core；
Step D4：The limit priority task and optimal processing core are rejected from ready task and ready processing core,
To update the ready task and the processing core；
Step D5：Circulation performs step D1 to step D4, until completing the scheduling of all ready tasks.
5. a kind of performance yields optimization device of multiprocessor device on-chip system, it is characterised in that including：
Timing node acquiring unit, for obtaining current scheduled time node；
Recognition unit, for recognizing multiple ready tasks and multiple ready processing cores under the current scheduled time node
Core；
Priority determining unit, the task priority for determining all ready tasks；
Scheduling unit, for, to high to Low order, being determined according to task priority based on performance yields each ready
It is engaged in corresponding optimal processing core, the ready task is one-to-one relationship with the optimal processing core.
6. device according to claim 5, it is characterised in that also include：
Judging unit, for judging whether all tasks are scheduled, if scheduling time node is otherwise updated, with to remaining
Business is scheduled, if so, then exporting task scheduling approach.
7. device according to claim 5, it is characterised in that the priority determining unit includes：
Mission critical identification module, for recognizing the mission critical in the ready task；
First computing module, for based on preset formula Ptask=(1+KCtask)·Vlatency·AlatencyCalculate all ready
The task priority of task；
Wherein, K is the constant more than 1；CtaskFor a binary variable, whether expression task is mission critical, is appointed for key
Business, CtaskValue is 1, conversely, value is 0；VlatencyExpression task performs the variance of delay on all processing cores；
AlatencyExpression task performs the average of delay on all processing cores.
8. device according to claim 5, it is characterised in that the scheduling unit includes：
Limit priority task determining module, for determining the limit priority task in all ready tasks；
Second computing module, for calculating performance yields of the limit priority task scheduling to all processing cores；
Handle core and choose module, for regarding the maximum processing core of performance yields as limit priority task correspondence
Optimal processing core；
Data update module, for rejecting the limit priority task and optimal from ready task and ready processing core
Core is handled, to update the ready task and the processing core.
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