CN107204340A - CP trap biasing means - Google Patents
CP trap biasing means Download PDFInfo
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- CN107204340A CN107204340A CN201710140554.5A CN201710140554A CN107204340A CN 107204340 A CN107204340 A CN 107204340A CN 201710140554 A CN201710140554 A CN 201710140554A CN 107204340 A CN107204340 A CN 107204340A
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
A variety of method and systems are described, for reducing the die area and circuit complexity that are used for that storage operation to be performed using one or more NAND strings.In certain embodiments, NAND string can be arranged within p traps, and the p traps are connected to the source electrode side of NAND string by physics ground short circuit.In this case, during storage operation, the p traps can be also applied to by applying to the bias voltage (for example, 2.5V) of the source electrode side of the NAND string.Physical short between the source electrode side and the p traps of the NAND string can be formed during memory die is made, and the source electrode side of the NAND string and the p traps can be prevented to be electrically insulated from each other during the operation of the memory die.
Description
Background technology
Semiconductor memory is widely used in various electronic equipments, such as, mobile phone, digital camera, personal digital assistant,
Medical electronic device, mobile computing device and stationary computing devices.Semiconductor memory can include non-volatile memories
Device or volatile memory.Even if when nonvolatile memory is not connected to power supply (for example, battery), nonvolatile memory
Still allow to store and retain information.The example of nonvolatile memory include flash memory (for example, NAND and NOR-type flash memory) and
Electrically Erasable Read Only Memory (EEPROM).
Flash memory and EEPROM utilize floating transistor.For each floating transistor, floating grid is positioned in floating boom
The channel region top of transistor is simultaneously insulated from.Channel region be positioned in floating transistor source electrode and drain region it
Between.Control gate is positioned in above floating grid and is insulated from.Can be by setting the electric charge of storage on the floating gate
Measure to control the threshold voltage of floating transistor.Come usually using fowler-Nuo get Hai Mu (F-N) tunnel-effects or injection of hot electrons
Control the quantity of electric charge on floating boom.The ability of adjusting threshold voltage allows floating transistor to serve as non-volatile memory device or storage
Device unit.In some cases, can often it be stored by programming and reading multiple threshold voltages or threshold voltage ranges to provide
The more than one data bit (that is, multilayer or multi-state memory cell) of device unit.
NAND flash memory structure generally arranges multiple floating transistors to select gate series with two and be disposed between.Series connection
Floating transistor and selection grid can be referred to as NAND string.In recent years, nand flash memory has been reduced size to subtract
Few every cost.However, because basic production process dimension reduces, occurring in that many design and processes challenges.These challenges include
Increased changeability in the memory cell and transistor characteristic that change with technique, voltage and temperature (PVT).
Brief description of the drawings
Fig. 1 depicts one embodiment of NAND string.
Fig. 2 depicts one embodiment of Fig. 1 NAND string using corresponding circuit diagram.
Fig. 3 A depict one embodiment of memory block, and the memory block includes multiple NAND strings.
Fig. 3 B depict one embodiment of the possible threshold voltage distribution for the memory cell per unit three.
Fig. 3 C depict one embodiment of two NAND strings, and described two NAND strings can be made into larger flash array
A part.
Fig. 4 A depict one embodiment of vertical NAND structures.
Fig. 4 B depict one embodiment along Fig. 4 A line X-X viewgraph of cross-section taken.
Fig. 5 A depict one embodiment of Nonvolatile memory system.
Fig. 5 B depict the one embodiment for reading block.
Fig. 6 A depict one embodiment of a part for memory block.
Fig. 6 B depict another embodiment of a part for memory block.
Fig. 6 C depict the first vertical NAND string associated with selected NAND string during programming operation and with
One embodiment of the second associated vertical NAND string of non-selected NAND string.
Fig. 6 D depict the first vertical NAND string associated with selected NAND string during programming operation and with
Another embodiment of the second associated vertical NAND string of non-selected NAND string.
Fig. 6 E depict the first vertical NAND string associated with selected NAND string during programming operation and with
Another embodiment of the second associated vertical NAND string of non-selected NAND string.
Fig. 6 F depict the first vertical NAND string associated with selected NAND string during read operation and with
One embodiment of the second associated vertical NAND string of non-selected NAND string.
Fig. 6 G depict the first vertical NAND string associated with selected NAND string during erasing operation and with
One embodiment of the second associated vertical NAND string of non-selected NAND string.
Fig. 7 A are the flow charts that description is used to perform one embodiment of the process of storage operation.
Fig. 7 B are the flow charts that description is used to perform another embodiment of the process of storage operation.
Embodiment
Describe for reducing the die area and electricity that are used for that storage operation to be performed using one or more NAND strings
The technology on road.Each in one or more NAND strings can include one associated with one or more memory cells
Or multiple floating transistors.In certain embodiments, NAND string can be arranged in trap (for example, p traps or n traps), and institute
The source electrode side of NAND string can be connected to by physics ground short circuit by stating trap.In this case, in storage operation (for example, reading
Extract operation, programming operation, programming verification operation, erasing operation or erasing verification operation) during be applied to the source side of NAND string
The bias voltage (for example, 2.5V) at end also will be applied to that the trap.Physical short can include the source electrode for being arranged in NAND string
Low resistance conductor (for example, metal wire) between side and trap, so that the resistance between the source electrode side and trap of NAND string
Low resistance path (for example, less than 10 ohm) can be included.Thing between the source electrode side of the NAND string and the trap
The road that is in the wrong can be formed during memory die is made, and can prevent described during the operation of the memory die
The source electrode side and the trap of NAND string are electrically insulated from each other.
In some cases, can be by the way that the source electrode side of NAND string be connected directly into metallic conduction path or one group of gold
Category line and metallic conduction path or described group of metal wire are connected directly to trap formed the source electrode side of NAND string and trap it
Between physical short.In one example, metallic conduction path can include first from the first diffusion (for example, n+ spreads)
Diffused contact, first diffusion is corresponding with the source electrode side of NAND string, and the NAND string is with metal wire (for example, tungsten wire or aluminium
Line) series connection, the metal wire connects with from metal wire to the second diffused contact of the second diffusion (for example, p+ diffusion), and described the
Two diffusions are connected directly to trap (for example, p traps) or are arranged in it.
In one example, during programming operation, the source electrode side of NAND string can be configured to CELSRC biased electricals
Press (for example, 2.5V), and trap can include p traps, due to the physical short between p traps and the source electrode side of NAND string, the p
Trap is arranged to CELSRC bias voltages.
CELSRC bias voltages can include more than 0V positive voltage or earthing potential.Although the source electrode of p traps and NAND string
Side is biased to CELSRC bias voltages, and selected wordline can be configured to selected wordline during programming operation
Voltage (for example, 20V).The source electrode side of p traps and NAND string is set to positive CELSRC bias voltages during programming operation
One benefit is can to reduce the source electrode side of the NAND string floating boom crystalline substance associated with the wordline of grid is selected close to source side
Electric field between body pipe, and if NAND string is prohibited during programming operation, then can improve raceway groove boosting.In addition, can
To be reduced or eliminated from the source electrode side of NAND string to the junction leakage of p traps.
In another example, during erasing operation, the source electrode side of NAND string can be configured to erasing voltage (example
Such as, 20V), and trap can include p traps, and due to the physical short between p traps and the source electrode side of NAND string, the p traps are set
It is set to erasing voltage.In some cases, during erasing operation, wordline can be configured to 0V, and simultaneously erased voltage is applied
It is added to both p traps and the source electrode side of NAND string.
In one embodiment, Nonvolatile memory system can include one or more two-dimentional nonvolatile memory lists
Element array.Memory cell in two dimensional memory arrays can form single memory elementary layer and can be via X-direction
It is selected with the control line (for example, wordline and bit line) of Y-direction.In another embodiment, Nonvolatile memory system can be with
Including one or more monolithic three dimensional memory arrays, wherein two layers or more layer memory cell can be formed single
Without any substrate between above substrate.In some cases, 3 D memory array can include being located at substrate
Top and it is orthogonal with substrate or with substrate substantially orthogonal to (for example, in 2 degree to 5 degree of the normal vector orthogonal with substrate) one
Individual or multiple vertical memory cell row.In one example, Nonvolatile memory system can include with vertical bit line or
Person has the memory array for being arranged to the bit line orthogonal with Semiconductor substrate.Substrate can include silicon substrate.Memory array
Row can include various memory constructions, and the memory construction includes plane NAND structures, vertical nand structure, position cost can
Extend (BiCS) NAND structures, 3D NAND structures or 3D ReRAM structures.
In certain embodiments, Nonvolatile memory system can include being monolithically formed with being disposed in silicon substrate
Nonvolatile memory in one or more physical memory cells arc array layers of the effective coverage of top.Non-volatile memories
System can also include the circuit associated with the operation of memory cell (for example, decoder, state machine, page register or
Person is used for the control circuit of reading or the programming of control memory unit).The circuit associated with the operation of memory cell can
With above substrate or in substrate.
Fig. 1 depicts one embodiment of NAND string 90.Fig. 2 depicts Fig. 1 NAND string using corresponding circuit diagram
One embodiment.As depicted, NAND string 90 is included in first choice grid 120 (that is, drain side selection grid) and second
Four transistors 100,102,104 and 106 connected between selection grid 122 (that is, source side selection grid).Select grid
NAND string 90 is connected to bit line 126 and by the way that suitable voltage is applied to control gate 120CG (that is, via Fig. 2 by 120
Selection line SGD) controlled.In this case, bit line 126 is connected directly to the drain electrode side of NAND string.Select grid 122
NAND string 90 is connected to source electrode line 128 and by the way that suitable voltage is applied to control gate 122CG (that is, via Fig. 2's
Selection line SGS) controlled.In this case, bit line 126 is connected directly to the source electrode side of NAND string 90.
Each in transistor 100,102,104 and 106 includes control gate and floating grid.For example, transistor 100
Including control gate 100CG and floating grid 100FG, transistor 102 includes control gate 102CG and floating grid 102FG, brilliant
Body pipe 104 includes control gate 104CG and floating grid 104FG, and transistor 106 includes control gate 106CG and floating grid
106FG.Control gate 100CG, 102CG, 104CG and 106CG are respectively connecting to wordline WL3, WL2, WL1 and WL0.
Note, although figures 1 and 2 show that four floating transistors in NAND string, but four floating transistors
Use and only provided as example.NAND string can be having less than or more than four floating transistors (or memory cell).Example
Such as, some NAND strings can include 16 memory cells, 32 memory cells, 64 memory cells, 128 memories
Unit etc..Discussion herein is not limited to any certain amount of memory cell in NAND string.One embodiment is using having
The NAND string of 66 memory cells, wherein, 64 memory cells are used for data storage, and two memory cells are claimed
For dummy memory cell, because their not data storages.
Typical architecture using the flash memory system of NAND flash memory structure includes multiple NAND strings in memory block.Memory
Block can include erasure unit.In some cases, the NAND string in memory block can share public trap (for example, p traps).Often
Individual NAND string can select grid (for example, being controlled by selection line SGS) to be connected to common source polar curve by its source side, and pass through
Its drain side selection grid (for example, being controlled by selection line SGD) is connected to its associated bit line.Generally, each bit line is hanging down
The straight top (or on) on the direction of wordline in its associated NAND string extends and is connected to sense amplifier.
In certain embodiments, during programming operation, by being boosted to associated channel region (for example, through
Coupled by wordline from boosted channel region), it can forbid or lock not to be programmed memory element (for example, being previously accomplished to mesh
Mark the memory element of the programming of data mode) and can not be programmed.Non-selected memory element (or non-selected NAND string)
Disabling or locking memory element (or NAND string of disabling) can be referred to as, because it changes in the given programming of programming operation
It is disabling or locking for programming in generation.
Although the technology using NAND-type flash memory can be described herein, technology disclosed herein is also applicable to other
The non-volatile memory apparatus and framework (for example, NOR-type flash memory) of type.Although utilizing floating transistor in addition, there is described herein
Technology, technology described herein is also applicable to or is used together with other memory technologies, including which utilizes electricity
Lotus capture, phase transformation (for example, sulfur family material) or state become material.
Fig. 3 A depict one embodiment of memory block, and the memory block includes multiple NAND strings.As depicted,
Each NAND string includes (Y+1) individual memory cell.Each NAND string is via the drain side controlled by drain side selection signal SGD
Selection grid is connected to the bit line (that is, a bit line in bit line BL0-BLX) in (X+1) bar bit line in drain side.
Each NAND string is connected to source electrode line (source electrode) via the source side selection grid controlled by source side selection signal SGS.One
In individual embodiment, grid is selected by the source side selection signal SGS source sides controlled and is controlled by drain side selection signal SGD
Drain side selection grid can include the transistor without floating grid or the transistor including floating gate structure.
In one embodiment, during programming operation, when program memory cells (such as, nand flash memory cell),
Program voltage can be applied to the control gate of memory cell, and corresponding bit line can be grounded.These programming biasings
Condition can cause electronics via field auxiliary electron tunneling injection into floating grid, thus improve the threshold value electricity of memory cell
Pressure.The program voltage of control gate is applied to during programming operation can be applied for a series of pulses.In some cases, may be used
To increase the amplitude of programming pulse, each continuous impulse is increased with pre- fixed step size.Between programming pulse, can perform one or
Multiple verification operations.During programming operation, boosted by the channel region to program-inhibit memory cell, Ke Yisuo
Determine and forbid having reached the memory cell of their expecting states and can not being programmed.
In one embodiment, by the way that p traps are increased into erasing voltage (for example, 20 volts) time enough section and will be stored
Selected piece of wordline of device unit is grounded source electrode simultaneously and bit line float to wipe memory cell.These erasing offset strips
Part can be such that electronics is transmitted by tunnel oxide from floating boom, so as to reduce the threshold value of the memory cell in selected block
Voltage.In some cases, can be to the independent block in whole memory plane, memory plane or memory cell
Another unit performs erasing operation.
In certain embodiments, during verification operation and/or read operation, selected word line can connect (or biasing) and arrive
Its level specific voltage for each reading and verification operation, to judge that the threshold voltage of particular memory cell is
It is no to have reached this level.After voltage is applied to wordline, can measure the conduction electric current of (or read) memory cell so as to
Judge whether memory cell has conducted enough magnitudes of current in response to being applied to the voltage of wordline.If measuring conduction electricity
Stream is more than some value, then assumes to have connected memory cell and be applied to threshold value electricity of the voltage more than memory cell of wordline
Pressure.If measuring conduction electric current is more than some value, assumes to be not switched on memory cell and be applied to the voltage of wordline
The no more than threshold voltage of memory cell.
In the presence of the method for many conduction electric currents for being used to measure memory cell during reading or verification operation.At one
In example, the conduction electric current of memory cell can be by it in the sense amplifier to dedicated capacitor electric discharge or the speed charged
Degree is measured.In another example, the conduction electric current of selected memory cell allows (or not allowing) to include memory list
The NAND string of member release voltage in respective bit line.The voltage of bit line is (or across the dedicated capacitor two ends in sense amplifier
Voltage) can measure over time, become, to judge the electric charge that specified quantitative whether has been released to bit line.
In some cases, during read operation or read operation, source side selection signal SGS can be configured to spy
Voltage (for example, 7V or 10V) is determined to be applied to the source junction that the voltage of source electrode line (source electrode) is delivered to floating transistor, it is described
The grid of floating transistor is connected to WL0 or the wordline of grid is selected close to source side.
Fig. 3 B depict the possibility of the memory cell (that is, memory cell can store three data) of every unit three
Threshold voltage distribution (or data mode) one embodiment.However, other embodiment can use every memory cell many
In or less than three data (for example, as per memory cell four or more position data).Successful program process (having checking)
At the end of, the threshold voltage of the memory cell in storage page or memory block should be suitably in the memory cell of programming
One or more threshold voltages distribution in or erasing memory cell threshold voltage distribution in.
As depicted, each memory cell can store three data；Accordingly, there exist eight valid data states
S0-S7.In one embodiment, data mode S0 is higher than 0 volt less than 0 volt and data mode S1 to S7.In other realities
Apply in example, eight data modes are above 0 volt, or can implement other arrangements.In one embodiment, threshold voltage point
Cloth S0 is wider than distribution S1 to S7.
Each data mode S0 to S7 corresponds to the unique value of three of storage in a memory cell.In one embodiment
In, S0=111, S1=110, S2=101, S3=100, S4=011, S5=010, S6=001 and S7=000.Can be with
Mapped using other of data to state S0-S7.In one embodiment, all data that will be stored in memory cell
It is stored in identical logical page (LPAGE).In other embodiments, the bits per inch of storage in a memory cell is according to corresponding to not same page.
Therefore, the memory cell of three data is stored by including the data in first page, second page and page three.In some embodiments
In, all memory cells being connected in the memory cell of same word line will store data in the page data of identical three
In.In certain embodiments, different page collection can be grouped into (for example, according to odd number by being connected to the memory cell of wordline
And even bitlines).
In some sample implementations, memory cell will be erased to state S0.From state S0, memory cell can
To be programmed to state S1-S7 any state.Can be by the way that the pulse set of the amplitude with rise be applied into memory list
The control gate of member performs programming.Between the pulses, verification operation collection can be performed, to judge programmed memory list
Whether member has reached its target threshold voltage (for example, using checking level Vv1, Vv2, Vv3, Vv4, Vv5, Vv6 and Vv7).
The memory cell for being programmed into state S1 will be tested, to check whether its threshold voltage has reached Vv1.Will be to quilt
The memory cell for being programmed into state S2 is tested, to check whether its threshold voltage has reached Vv2.Will be to being programmed into
State S3 memory cell is tested, to check whether its threshold voltage has reached Vv3.Will be to being programmed into state S4
Memory cell tested, to check whether its threshold voltage has reached Vv4.By the storage to being programmed into state S5
Device unit is tested, to check whether its threshold voltage has reached Vv5.By the memory cell to being programmed into state S6
Tested, to check whether its threshold voltage has reached Vv6.The memory cell for being programmed into state S7 will be surveyed
Examination, to check whether its threshold voltage has reached Vv7.
When reading the memory cell for three data of being stored with, will reading comparison point Vr1, Vr2, Vr3, Vr4, Vr5,
Perform and repeatedly read at Vr6 and Vr7, to judge which state memory cell is in.If memory cell in response to
Vr1 and connect, then its be in state S0.If memory cell is connected in response to Vr2 but is not responsive to Vr1 and connects,
It is in state S1.If memory cell is connected in response to Vr3 but is not responsive to Vr2 and connects, it is in state S2.
If memory cell is connected in response to Vr4 but is not responsive to Vr3 and connects, it is in state S3.If memory list
Member is connected in response to Vr5 but is not responsive to Vr4 and connects, then it is in state S4.If memory cell is in response to Vr6
Connect but be not responsive to Vr5 and connect, then it is in state S5.If memory cell is connected in response to Vr7 but not rung
It should be connected in Vr6, then it is in state S6.If memory cell is connected in response to Vr7, it is in state S7
In.
Fig. 3 C depict one embodiment of two NAND strings 312 and 314, and described two NAND strings can be made into larger
A part for flash array.As depicted, NAND string 312 and 314 each include four memory cells, n-type diffusion 324 with
And a part for shared p-well 320.The floating grid that each memory cell in NAND string is isolated with by dielectric layer 334 and 330
The correspondence of pole 332.N traps 326 are below p-well 320.Bit line direction (or y directions) is in the up extension in direction of NAND string, and wordline
Direction (or x directions) extends perpendicular to NAND string or bit line direction.Word-line direction can also be referred to as line direction and bit line direction
Column direction can be referred to as.In some cases, the bit line associated with NAND string can be in the direction perpendicular to word-line direction
On extend in the bit line direction at the top (or on) of NAND string.In some cases, N traps 326 can be located at P type substrate
In (not describing).As depicted, NAND string 312 is separated by area of isolation 316 with NAND string 314.Isolated area 316 can be wrapped
Include the insulating materials or dielectric between neighboring NAND strings (not describing).Generally, shallow trench isolation (STI) is used to isolate adjacent
NAND string (for example, using active area STI).In one embodiment, control gate 336 is corresponding with wordline, e.g., Fig. 3 A word
Line WL0-WLY.In some cases, NAND string 312 and NAND string 314 can be arranged within shared p-well 320 or fixed
Position is in the shared top of p-well 320.
In some cases, NAND string can include horizontal NAND structures, and in the structure, NAND string is positioned in flat
Row is within the plane of substrate.In some cases, NAND string can include vertical NAND structures, in the structure, NAND
String is positioned within the plane for being orthogonal to substrate.Vertical NAND structures can include vertical NAND string or invert NAND vertically
String.NAND string can include floating transistor string.Reversion NAND string can include floating transistor string.
Fig. 4 A depict one embodiment of vertical NAND structures.Vertical NAND structures include reversion NAND string, described anti-
Turn NAND string formation in the top of substrate 424 and be oriented such that reversion NAND string is orthogonal with substrate 424.Inverting NAND string can be with
Including NAND string, the NAND string includes reversion floating transistor, and the reversion floating transistor has in reversion floating boom crystal
Tunneling oxide between the floating grid of pipe and the control gate for inverting floating transistor.Floating grid and control gate it
Between tunneling oxide arrangement be allowed for programming and/or wipe reversion floating transistor mechanism (for example, F-N tunnellings make
For transfer mechanism) appear between floating grid and control gate rather than in the raceway groove of floating grid and reversion floating transistor
Between.Reversion NAND string can be arranged within vertical memory hole, and the vertical memory hole is etched through control gate
Material (for example, tungsten, nitride or polysilicon) between grid insulating material (for example, oxide or silica) replaces
Layer.As depicted, control gate material layer includes layer 417 and layer 414-416 and layer of insulator material includes layer between grid
418-420.Layer of insulator material 420 can be arranged above source electrode line 422 (for example, DOPOS doped polycrystalline silicon) of layer between grid, institute
Stating source electrode line layer can be arranged above substrate 424 (for example, silicon substrate).In some cases, the first wordline (WL1) can be with
Corresponding with control gate layer 414, the second wordline (WL0) can be corresponding with control gate layer 415, and source side selection gate line
(SGS) can be corresponding with control gate layer 416.
In one embodiment, within memory hole tunnelling layer material 408 (e.g., including thin-oxide), floating grid
Pole material 410 (for example, polysilicon), dielectric layer 412 (for example, oxide) and channel layer materials 406 (for example, undoped with
Polysilicon) it can be deposited within memory hole and be arranged to form reversion NAND string.As Fig. 4 A are described, tunnel
Layer material 408 is worn to be arranged within memory hole or inside it.Tunnelling layer material 408 can include what multi-layer dielectric was stacked
A part, such as, ONO dielectric stacks, the multi-layer dielectric, which is stacked, includes silica (" O ") and silicon nitride (" N ")
Alternating layer.In some cases, tunnelling layer material 408 can include high-k dielectric material (for example, the high-k dielectric based on hafnium
Or oxidation is proper), the high-k dielectric material has the dielectric constant of the dielectric constant more than silica.In some cases, core
Material layer 404 (for example, oxide) can be formed within memory hole.In other cases, it is convenient to omit core material layer
404.Bit line contact layer 402 can form at the top in memory hole and be connected to or abut directly against channel layer materials 406.
Channel layer materials 406 can be connected to the source electrode line layer 422 at the bottom in memory hole.Therefore, in this case, bit line connects
Contact layer 402 is connected to the reversion NAND string at the top in memory hole, and source line contact layer 422 is connected to the bottom in memory hole
Reversion NAND string at portion.
In one embodiment, bit line contact layer 402 can include the material of the first conduction type (for example, n-type), and source
Line contacts layer 422 can include the material of the second conduction type (for example, p-type) different from the first conduction type.At one
In example, bit line contact layer 402 can include n-type material (for example, n-type polysilicon), and source line contact layer 422 can include
P-type material (for example, p-type).In another example, bit line contact layer 402 can include p-type material, and source electrode line
Contact layer 422 can include n-type material (for example, n-type polysilicon).Therefore, in some cases, reversion NAND string can include
Asymmetric source electrode and drain electrode, the source electrode and drain electrode can be used for utilizing the storage operation (example for inverting NAND string execution
Such as, programming, wipe and read operation) offer electronics supply is (via n-type material) and hole supplies (via p-type material) the two.
Depending on applying to the bias condition for inverting NAND string, storage operation can include n-channel operation and/or p-channel operation.
In one embodiment, it is possible to use core material layer (for example, oxide skin(coating) or other dielectric layers) formation reversion
NAND string, the core material layer is arranged at neighbouring channel layer (for example, undoped polycrystalline silicon channel layer), and the channel layer is pacified
Arrange as adjacent to barrier layer (for example, oxide skin(coating) or other dielectric layers), the barrier layer is arranged at neighbouring floating gate layer
(or electric charge capture layer), the floating gate layer is arranged at neighbouring tunnel layer (for example, thin-oxide), and the tunnel layer is pacified
Come neighbouring control gate layer (for example, tungsten).Tunnel layer can have the thickness of the thickness less than barrier layer.
Fig. 4 B depict one embodiment along Fig. 4 A line X-X viewgraph of cross-section taken.As depicted, invert
NAND string includes the inner core material bed of material 404, and the inner core material bed of material is surrounded by channel layer materials 406, and the channel layer materials are by electricity
Dielectric layer 412 is surrounded, and the dielectric layer is surrounded by floating gate material 410, and the floating gate material is by tunnelling layer material
408 are surrounded, and the tunnelling layer material is surrounded by control gate material layer 417.In one embodiment, Fig. 4 A can describe along figure
The viewgraph of cross-section that 4B line Y-Y is taken.In one embodiment, it is possible to use vertical cylinder shape structure or vertical gradually change
Thin cylindrical structural forms reversion NAND string.In this case, dielectric material 412, the floating grid of NAND string are inverted
Material 410, tunnelling layer material 408 and channel layer materials 406 can include the vertical ring junction for being surrounded with core material layer 404
Structure.In another embodiment, it is possible to use vertical rod structure or vertical rectangular prism structure form reversion NAND string.
Fig. 5 A depict the embodiment of Nonvolatile memory system 596, and the Nonvolatile memory system includes being used for simultaneously
Row read and programming one page (or other units) memory cell (for example, NAND multilevel-cells) read/write circuits.Such as
Described, Nonvolatile memory system 596 includes memory die 598 and controller 550.Memory die 598 includes depositing
Memory array 501 (for example, nand flash memory array), control circuit 510, row decoder 530, column decoder 560 and read/write
Enter circuit 565.In one embodiment, realized in a symmetrical manner on the opposite side of array by various peripheral circuit (examples
Such as, row decoder or column decoder) for the access of memory array 501, so that tie-in line and circuit on every side
Density be halved.Memory array 501 by wordline and via column decoder 560 can pass through position via row decoder 530
Line is addressed.Wordline and bit line are the examples of memory array control line.Read/write circuits 565 include multiple reading blocks
500, the reading block allows memory element page to be read or programmed in parallel.In some cases, controller 550 can be integrated in
In memory die 598.Order and data are via line 520 in controller between main frame and controller 550 and via line 518
Transmitted between 550 and memory die 598.
Controller circuitry 510 coordinates with read/write circuits 565, to perform storage operation to memory array 501.
Circuit 510 is controlled to include state machine 512, on-chip address decoder 514 and power control module 516.State machine 512 is provided and deposited
The chip-scale control of reservoir operation.On-chip address decoder 514 provide the address that is used by main frame with by decoder 530 and 560
Address interface between the hardware address used.Power control module 516 is during storage operation to being supplied to wordline and position
The power and voltage of line are controlled.In one embodiment, power control module 516 includes one or more charge pumps, institute
The voltage bigger than supply voltage can be generated by stating charge pump.
In certain embodiments, one or more parts (either individually or in combination) in addition to memory array 501 can
To be referred to as managing or control circuit.For example, one or more management or control circuit can include control circuit 510, state
In machine 512, decoder 530/560, Power Control 516, reading block 500, read/write circuits 565 and controller 550 etc.
Any one is combined.One or more management circuits or one or more control circuits can perform or be conducive to one or many
Individual memory array operation, including erasing operation, programming operation or read operation.
In certain embodiments, one or more management or control circuits can be used for (e.g., the storage of control memory array
Device array 501) operation.One or more management or control circuits can provide control signal so as to depositing to memory array
Memory array performs read operation and/or write operation.In one example, one or more management or control circuits can be wrapped
Include any of control circuit, state machine, decoder, sense amplifier, read/write circuits and/or controller or combination.One
Individual or multiple control circuits can cause or be conducive to one or more memory array operations, include and stay in memory array
Erasing operation, programming operation or the read operation of upper execution.In one example, one or more control circuits can include
On-chip memory controller, for determining that row address and column address, wordline address and bit line address, memory array enable signal
And/or data latch signal.
In one embodiment, memory array 501 be divided into substantial amounts of memory cell block (such as block 0-1023, or its
His quantity).Such as identical for flash memory system, described piece can be the unit wiped.That is, each block can be comprising together
The minimum number destination memory location of erasing.The unit that other can also be used to wipe.Block is comprising one group via bit line and wordline
The NAND string of access.Generally, in block all NAND strings share one group of common word line.
Each block can be divided into certain amount of page.In one embodiment, page can be the unit of programming.Can also
The unit programmed using other.One or more data pages are commonly stored in row of memory cells.For example, one or more
Data page can be stored in the memory cell for being connected to common word line.In one embodiment, it is connected to common word line
Described group of memory cell is typically programmed simultaneously.Page can store one or more sectors.Sector can include user data and open
Sell data (also referred to as system data).Overhead data generally includes what header information was calculated with oneself warp from the user data of sector
Self-correcting code (ECC).Controller (or miscellaneous part) is calculating ECC when data are programmed into array, and works as from battle array
Row are also checked ECC when reading data.Alternately, ECC and/or other overhead datas can be stored in belonging to it
It is stored in the different page of user data or even in the block different from the user data belonging to it.The sector of user data leads to
It is often 512 bytes, the size of this sector corresponded in disc driver.A large amount of page formation blocks, block is probably from page 8 for example to 32
Page, page 64, between page 128 or more pages.Different size of piece, page and sector can also be used.
Fig. 5 B depict the one embodiment for reading block 500 (the reading block 500 in such as Fig. 5 A).Individually read block
500 can be divided into core (being referred to as reading module 580) and common sparing 590.In one embodiment, exist
Independent reading module 580 for each bit line and a common portion 590 for one group of multiple reading module 580.
In one example, a common portion 590 and eight reading modules 580 will be included by reading block.Reading module in one group
In each read module will be via data/address bus 572 and related common portion communication.
Reading module 580 includes reading circuit 570, and the reading circuit judges that the conductive current in connected bit line is
It is no to be higher or lower than predetermined threshold levels.Read module 580 also include bit line latch 582, institute's bit line latch be used for pair
The bit line connected sets voltage conditions.For example, the predetermined state latched in bit line latch 582 can cause being connected
Bit line is drawn to the state (for example, 1.5V-3V) of specified program-inhibit.
Common portion 590 include processor 592, one group of data latches 594 and described group of data latches 594 with
The I/O interfaces 596 coupled between data/address bus 520.Processor 592 performs calculating.For example, processor 592 can determine storage
Data in the memory element read and by identified data storage in described group of data latches.Described group of number
It can be used for the data bit that storage is determined by processor 592 during read operation according to latch 594, or for being stored in volume
The data bit that journey is imported during operating from data/address bus 520.The data bit imported represents that plan is programmed into memory array
In write-in data, e.g., the figure memory array 501 in 5A.I/O interfaces 596 are provided in data latches 594 and data/address bus
Interface between 520.
During read operation or other memory element read operations, state machine (e.g., the state machine 512 in Fig. 5 A) control
Different control gate voltage supplies are given to the memory element being addressed to.Having stepped through each memory with memory support
During corresponding each the predetermined control gate voltage of state, read module 580 and can be stumbled at one in these voltages and is stopped simultaneously
And output will be provided to processor 592 from reading module 580 via bus 572.Now, processor 592 reads mould by considering
The event of stopping and on the information of the control gate voltage applied from state machine via input line 593 of stumbling of block, it is determined that obtaining
Memory state.Then, the processor calculates the binary coding for memory state, and obtained data bit is deposited
Store up in data latches 594.In another embodiment of core, bit line latch 582 is both used as being used to latch reading
Go out the latch of the output of module 580, bit line latch as described above is used as again.
During programming operation, by data storage to be programmed in described group of data latches 594.In state machine 512
Control under, programming operation include apply to the memory element being addressed control gate a series of program voltage pulses.Often
Individual programming pulse reads back (verification process) to judge whether programmed to the desired memory shape of memory element after being all followed by
State.Processor 592 monitors the memory state that reads back relative to desired memory state.When two state consistencies, processing
Device 592 sets bit line latch 582, so that bit line is pulled to the state of specified program-inhibit voltage.This forbids being coupled to bit line
Memory element be further programmed, there is programming pulse in the control gate of memory element.In other embodiments,
Processor initially loads bit line latch 582 and reading circuit is set to prohibition value during verification process.
Data latch stack 594 includes the stacking of data latches corresponding with reading module.In one embodiment,
Each module 580 that reads has three data latches.Data latches may be implemented as shift register, so that its
The parallel data of middle storage is converted into the serial data for data/address bus 520, and vice versa.It is corresponding with read/write block
All data latches can link together to form block shift register so that by serial transmission come defeated
Enter or output block.Specifically, the storehouse of read/write module is configured, so that in its data latches group
Data are just looked like that they are displacements for whole read/write block sequentially into and out data/address bus by each
A part for register is the same.
In certain embodiments, it is possible to use integrated circuit realizes Nonvolatile memory system, e.g., the figure in 5A is non-volatile
Property storage system 596.Integrated circuit can include on-chip circuit to generate rise voltage, and the rise voltage has than providing
To the bigger intensity of the maximum supply power voltage of integrated circuit.Rise voltage can be used for providing power on integrated circuit
Electronic circuit a part.Rise voltage can be generated using charge pump system on piece.In some cases, charge pump system
System can be used for generating output voltage, and the output voltage is bigger than providing maximum supply power voltage to integrated circuit.At other
In the case of, charge pump system can be used for generating output voltage, and the output voltage is than providing to the minimum power supply of integrated circuit
Voltage is smaller (for example, negative charge pump system can generate the voltage less than ground or VSS).
Fig. 6 A depict one embodiment of a part for memory block.Memory block includes being arranged in bit line 601 and source
Four NAND strings between polar curve 602.First NAND string of four NAND string kinds includes being controlled by drain side selection signal SGD0
Three drain sides selection grid and by source side selection signal SGS0 control three source sides select grid.Transistor
611 include the inter-transistor in three drain side selection grids.During transistor 612 is included in three source side selection grids
Between transistor.Three drain side selection grids can correspond to single drain side selection grid, the single drain side selection grid
The effective transistor length having is three times of one of three drain sides selection grid.Three source side selection grids can
To select grid corresponding to single source side, effective transistor length that the single source side selection grid has is described three
Three times of one of individual source side selection grid.As depicted, source electrode line 602 is connected directly to the source electrode side of the first NAND string
Or the source side of the source side selection grid for the first NAND string.
Fig. 6 B depict another embodiment of a part for memory block.Memory block include be arranged in bit line 603 with
Four NAND strings between source electrode line 604.First NAND string of four NAND string kinds includes being controlled by drain side selection signal SGD0
Three drain sides selection grid of system and the three source sides selection grid controlled by source side selection signal SGS0.Transistor
613 include the inter-transistor in three drain side selection grids.During transistor 614 is included in three source side selection grids
Between transistor.Three drain side selection grids can correspond to single drain side selection grid, the single drain side selection grid
The effective transistor length having is three times of one of three drain sides selection grid.Three source side selection grids can
To select grid corresponding to single source side, effective transistor length that the single source side selection grid has is described three
Three times of one of individual source side selection grid.First NAND string also includes being positioned at three source side selection grids and source electrode line
Extra transistor 616 between 604, and the grid of the extra transistor is connected to signal SGSB.As depicted, source electrode
Line 604 is connected to the source electrode side of the first NAND string or is connected to the source electrode of the extra transistor 616 for the first NAND string
Side.When extra transistor 616 is arranged in conduction state, then source electrode line 604 can be electrically connected to for the first NAND string
Three source sides select grid source side.
Fig. 6 C depict the first vertical NAND string associated with selected NAND string during programming operation and with
One embodiment of the second associated vertical NAND string of non-selected NAND string.As depicted, the first vertical NAND string with
And second vertical NAND string be positioned in the top of p traps 630 and shared p traps 630.First vertical NAND string is connected to the leakage of NAND string
Bit line at the side of pole.During programming operation, reverse layer or conductive path formation is in n+ diffusions 642 and the first vertical NAND string
In minimum transistor raceway groove between, the grid of the minimum transistor is connected to SGSB636.In this case, first
The source electrode side of vertical NAND string spreads 642 and the reverse layer or conductive path that are formed below the first vertical NAND string via n+
And it is electrically connected to CELSRC lines.P traps 630 are biased to ground connection via the p traps contacts 682 directly contacted with p+ diffusions 644.P traps
Contact 682 can include metallic plug, e.g., tungsten plug.In some cases, three drain side selection grids 632 can be corresponded to
Three drain sides selection grid 613 in Fig. 6 B, three sources that three source side selection grids 635 can correspond in Fig. 6 B
Pole side selects grid 614, and grid is connected to the transistor 616 that SGSB transistor can correspond in Fig. 6 B.In programming
During operation, selected wordline 634 can be configured to VPGM, while non-selected wordline (e.g., including non-selected word
Line 633) it is arranged to V and passes through.
Although it should be noted that n+ diffusions 642 are located in p traps 630, applying to the n+ voltages for spreading 642 and not necessarily leading
Cause the bias voltage change of p traps.Although not describing, depleted region can be formed between n+ spreads 642 and p traps 630, this permission
Apply to the n+ voltages for spreading 642 and be different from applying to the voltage of p traps 630.In one example, during programming operation,
CELSRC lines can be configured to 2V, while p traps 630 are arranged to 0V.Therefore, although n+ diffusions 642 are located in p traps 630,
PN junction prevents n+ diffusions 642 are short-circuit to be connected to p traps 630.N+ diffusions 642 are connected to one with the no physics ground short circuit of p traps 630
Rise, because PN junction is electrically separated with p traps 630 by n+ diffusions 642.
Fig. 6 D depict the first vertical nand string associated with selected NAND string during programming operation and with
One embodiment of the second associated vertical nand string of non-selected NAND string.As depicted, the first vertical NAND string with
And second vertical NAND string be positioned in the top of p traps 630 and shared p traps 630.First vertical NAND string is connected to the leakage of NAND string
Bit line at the side of pole.In this case, the source electrode side of the first vertical NAND string is electrically connected to via n+ diffusions 642
CELSRC lines, and p traps 630 are connected to CELSRC lines via p+ 646 physics ground short circuits of diffusion.CELSRC lines (for example, by tungsten,
The metal wire that copper or aluminium are made) p traps contact 683 can be directly contacted, the p traps contact directly contacts p+ diffusions 646.P traps are touched
Point 683 can include metallic plug, e.g., tungsten plug.In one example, CELSRC lines can include metal wire, and described
Metal wire can be connected to p+ diffusions 646 via diffused contact or hard contact, and the hard contact extends to p+ from metal wire
Diffusion 646, and the p+ 646 physics ground short circuits of diffusion are connected to p traps 630.In this case, if CELSRC lines are inclined
2V is put, then due to the physical short between CELSRC lines and p traps 630, p traps 630 will also be biased to 2V.
Fig. 6 E depict the first vertical NAND string associated with selected NAND string during programming operation and with
Another embodiment of the second associated vertical NAND string of non-selected NAND string.As depicted, the first vertical NAND string
And second vertical NAND string be positioned in the top of p traps 630 and shared p traps 630.First vertical NAND string is connected to NAND string
Bit line at drain electrode side.CELSRC lines are connected to p traps 630 via p+ diffusions 646 by physics ground short circuit, and p traps are via n+
Diffusion 642, p+ diffusions 646 and metal connect 645 (for example, tungsten or aluminium for being embedded within p traps 630) and connected by physics ground short circuit
It is connected to the source electrode side of the first vertical NAND string.In this case, CELSRC lines can include metal wire, and metal wire can
P+ diffusions 646 are connected to via diffused contact or to extend to the hard contact of p+ diffusions 646 from metal wire.P+ diffusions 646
P traps 630 and n+ diffusions 642 are connected to by physics ground short circuit via metal connection 645.In this case, if CELSRC
Line is biased to 3V, then p traps 630 and n+ diffusions 642 will also be biased to 3V.
Fig. 6 F depict the first vertical NAND string associated with selected NAND string during read operation and with
One embodiment of the second associated vertical NAND string of non-selected NAND string.During read operation, selected wordline
654 can be configured to VREAD, while non-selected wordline (e.g., including non-selected wordline 653) is arranged to V and passed through.
As depicted, the first vertical NAND string and the second vertical NAND string are positioned in the top of p traps 630 and shared p traps 630.The
One vertical NAND string is connected to the bit line at the drain electrode side of NAND string.During read operation, the source of the first vertical NAND string
Pole side is electrically connected to CELSRC lines via n+ diffusions 642, and p traps 630 spread 646 physics ground short circuits via p+ and are connected to
CELSRC lines.In one example, CELSRC lines can include metal wire, and the metal wire can via diffused contact or
Hard contact is connected to p+ diffusions 646, and the hard contact extends to p+ diffusions 646 from metal wire, and the metal wire can
To be connected to n+ diffusions 642 via diffused contact or hard contact, the hard contact extends to n+ diffusions 642 from metal wire.p
+ diffusion 646 is connected to p traps 630 by physics ground short circuit.In this case, if CELSRC lines are biased to 1V, p traps 630
Also 1V will be biased to.
Fig. 6 G depict the first vertical NAND string associated with selected NAND string during erasing operation and with
One embodiment of the second associated vertical NAND string of non-selected NAND string.As depicted, the first vertical NAND string with
And second vertical NAND string be positioned in the top of p traps 630 and shared p traps 630.First vertical NAND string is connected to the leakage of NAND string
Bit line at the side of pole.During erasing operation, the source electrode side of the first vertical NAND string is electrically connected to via n+ diffusions 642
CELSRC lines, and p traps 630 are connected to CELSRC lines via p+ 646 physics ground short circuits of diffusion.In one example, CELSRC
Line can include metal wire, and the metal wire can be connected to p+ diffusions 646 via diffused contact or hard contact, described
Hard contact extends to p+ diffusions 646 from metal wire, and the p+ spreads 646 physics ground short circuits and is connected to p traps 630.At this
In the case of kind, if CELSRC lines are biased to 16V, p traps 630 will also be biased to 16V.
Fig. 7 A are the flow charts that description is used to perform one embodiment of the process of storage operation.In one embodiment
In, Fig. 7 A process can be performed by Nonvolatile memory system (such as, the Nonvolatile memory system 596 in Fig. 5).
In a step 702, storage operation is initiated.In step 704, operation is wiped based on memory and determines first voltage.
Reservoir operation can include read operation, programming operation, program verification operation or erasing operation.In step 706, in memory
During operation, p traps are set to first voltage.P traps are connected to the source electrode side of NAND string by physics ground short circuit.NAND string is pacified
Come within p traps.In step 708, when the p traps are arranged to the first voltage, storage operation is performed.Memory
Operation can cause the data being stored in the memory cell of NAND string to be read.
Fig. 7 B are the flow charts that description is used to perform another embodiment of the process of storage operation.In one embodiment
In, Fig. 7 B process can be performed by Nonvolatile memory system (such as, the Nonvolatile memory system 596 in Fig. 5).
In step 722, storage operation is initiated.In step 724, operation is wiped based on memory and determines first voltage.
Reservoir operation can include read operation, programming operation, program verification operation or erasing operation.In step 726, in memory
During operation, p traps are set to first voltage.P traps are short-circuited the source electrode side for being connected to NAND string via metallic conduction path.
NAND string is positioned in above p traps.In step 728, when the p traps are arranged to the first voltage, memory is performed
Operation.Storage operation can cause data to be written to the memory cell of NAND string.
One embodiment of disclosed technology includes NAND string, bit line and source electrode line.NAND string includes being positioned in
Multiple memory components between the source electrode side of NAND string and the drain electrode side of NAND string.NAND string is arranged within p traps.
Bit line is connected to the drain electrode side of NAND string.Source electrode line is connected to the source electrode side of NAND string.Source electrode line is connected by physics ground short circuit
It is connected to the source electrode side of NAND string and p traps is connected to by physics ground short circuit.
One embodiment of disclosed technology includes being positioned at the p traps above n traps and NAND string.N traps can be formed in p
Above type substrate.NAND string includes the multiple floating booms being positioned between the source electrode side of NAND string and the drain electrode side of NAND string
Transistor.NAND string is positioned in above p traps.P traps are connected to the source electrode side of NAND string by physics ground short circuit.
One embodiment of disclosed technology, which includes setting p traps, arrives first voltage.P traps are positioned under NAND string
Side.NAND string includes the multiple memory components being positioned between the source electrode side of NAND string and the drain electrode side of NAND string.p
Trap is short-circuited the source electrode side for being connected to NAND string via metallic conduction path.Methods described further comprises：In the p traps quilt
When being set to the first voltage, storage operation is performed using NAND string.
For purpose of this document, it should be noted that the size for each feature described in accompanying drawing be not necessarily by
What ratio was drawn.
For purpose of this document, " embodiment ", " one embodiment ", " some embodiments " or " another are quoted in specification
One embodiment " can be used for describing different embodiments without referring to identical embodiment.
For purpose of this document, connection can be (for example, via another part) connected directly or indirectly.
Under certain situation, when element is referred to as being connected or coupled to another element, the element can be directly connected to other
Element is indirectly connected to other elements via intervenient element.When element is referred to as being connected directly to another yuan
During part, then there is no intervenient element between the element and other elements.
For purpose of this document, term "based" can be read as " being at least partially based on ".
For purpose of this document, in the case of not extra linguistic context, using numerical terms, such as " first " object,
" second " object and " the 3rd object " can not only imply the order of object, and it is different to recognize to can be also used for identifying purpose
Object.
For purpose of this document, " set " of term object can refer to " set " of one or more objects.
Although describing this theme with the language specific to architectural feature and/or method sexual act, it should be appreciated that,
The theme limited in appended claims is not necessarily limited to specific features described above or action.Saying more precisely, above
Described specific features and action are disclosed as the exemplary forms for realizing claim.
Claims (20)
1. a kind of device, including：
NAND string, the NAND string include being positioned in the source electrode side of the NAND string and the NAND string drain electrode side it
Between multiple memory components, the NAND string is arranged within p traps；
Bit line, the bit line is connected to the drain electrode side of the NAND string；And
Source electrode line, the source electrode line is connected to the source electrode side of the NAND string, and the source electrode line is connected by physics ground short circuit
It is connected to the source electrode side of the NAND string and the p traps is connected to by physics ground short circuit.
2. device as claimed in claim 1, further comprises：
Second NAND string, second NAND string is arranged within the p traps, and the source electrode line is connected to by physics ground short circuit
The source electrode side of second NAND string.
3. device as claimed in claim 1, wherein：
During programming operation, the source electrode line is arranged to positive voltage.
4. device as claimed in claim 1, wherein：
During erasing operation, the source electrode line is arranged to erasing voltage.
5. device as claimed in claim 1, wherein：
The multiple memory component includes multiple floating transistors；
The source electrode line includes metal wire；
The source electrode line is connected to the p traps via p traps contact by physics ground short circuit；And
The source electrode line is connected to the source electrode side of the NAND string via diffused contact by physics ground short circuit.
6. device as claimed in claim 1, wherein：
The p traps include p+ diffusion zones, and the source electrode line is connected to the p+ via hard contact by physics ground short circuit
Diffusion zone.
7. device as claimed in claim 1, wherein：
The source electrode side of the NAND string is connected to the p traps by physics ground short circuit, without transistor in the NAND
Between the source electrode side and the p traps of string.
8. device as claimed in claim 1, wherein：
The source electrode side of the NAND string is connected to the p traps by physics ground short circuit, without transistor by the NAND
The source electrode side of string is electrically connected to the p traps.
9. device as claimed in claim 1, wherein：
The NAND string includes vertical NAND string.
10. device as claimed in claim 1, wherein：
The NAND string includes a part for 3 D memory array.
11. device as claimed in claim 1, wherein：
The NAND string is arranged in the memory die including nonvolatile memory, the nonvolatile memory monolithic
Formed in one or more memory cell physical layer levels with the active area being arranged in above silicon substrate likes.
12. a kind of system, including：
P traps, the p traps are positioned in above n traps；And
NAND string, the NAND string include being positioned in the source electrode side of the NAND string and the NAND string drain electrode side it
Between multiple floating transistors, the NAND string is positioned in above the p traps, and the p traps are connected to institute by physics ground short circuit
State the source electrode side of NAND string.
13. system as claimed in claim 12, further comprises：
Second NAND string, second NAND string is positioned in above the p traps, and the p traps are connected to institute by physics ground short circuit
State the source electrode side of the second NAND string.
14. system as claimed in claim 12, wherein：
During programming operation, the p traps are arranged to positive voltage.
15. system as claimed in claim 12, wherein：
The p traps are via p traps contact portion to source electrode line, and the source electrode line is connected to the NAND string via diffused contact
The source electrode side.
16. system as claimed in claim 15, wherein：
The p traps include p+ diffusion zones, and the source electrode line is connected to the p+ via hard contact by physics ground short circuit
Diffusion zone.
17. a kind of method, including：
P traps are set to first voltage, the p traps are positioned in below NAND string, the NAND string is described including being positioned in
Multiple memory components between the source electrode side of NAND string and the drain electrode side of the NAND string, the p traps are led via metal
Power path is short-circuited the source electrode side for being connected to NAND string；And
When the p traps are arranged to the first voltage, storage operation is performed using the NAND string.
18. method as claimed in claim 17, wherein：
The storage operation includes programming operation；And
The first voltage includes positive voltage.
19. method as claimed in claim 17, wherein：
The storage operation includes erasing operation.
20. method as claimed in claim 17, wherein：
The source electrode side of the NAND string is connected to the p traps by physics ground short circuit, without transistor by the NAND
The source electrode side of string is electrically connected with the p traps.
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| Application Number | Priority Date | Filing Date | Title |
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| US201615073634A | 2016-03-17 | 2016-03-17 | |
| US15/073,634 | 2016-03-17 |
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