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CN107195635B - 薄膜晶体管阵列基板及其制备方法 - Google Patents

薄膜晶体管阵列基板及其制备方法 Download PDF

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CN107195635B
CN107195635B CN201710335301.3A CN201710335301A CN107195635B CN 107195635 B CN107195635 B CN 107195635B CN 201710335301 A CN201710335301 A CN 201710335301A CN 107195635 B CN107195635 B CN 107195635B
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宋利旺
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Abstract

本发明提供一种薄膜晶体管阵列基板及其制备方法，方法包括：提供衬底基板，在衬底基板上依次形成栅极、栅极绝缘层、有源层、欧姆接触层、源/漏极及绝缘层；在绝缘层上涂布光阻层；对光阻层进行曝光，使光阻层图案化，在欲形成像素电极的对应位置暴露绝缘层，并且形成分布在暴露的绝缘层周缘的第一光阻区域及分布在第一光阻区域外围的第二光阻区域，第一光阻区域光阻层的厚度小于第二光阻区域光阻层的厚度；通过蚀刻制程移除暴露的绝缘层，形成过孔，暴露出漏极，第一光阻区域对应过孔上方边缘；对光阻层进行灰化处理，去除第一光阻区域，暴露出过孔侧壁，保留部分第二光阻区域；在过孔中形成像素电极，像素电极覆盖过孔侧壁，形成薄膜晶体管阵列基板。

Description

薄膜晶体管阵列基板及其制备方法
技术领域
本发明涉及液晶显示器制备领域，尤其涉及一种薄膜晶体管阵列基板及其制备方法。
背景技术
信息社会，平板显示无处不在，无论是电视、电脑、智能手机等，都离不开液晶显示面板的支撑。人们对显示设备的需求不断增长，因而也推动了液晶显示面板行业的快速发展，液晶面板的产量不断提升，对产品的品质及良率也有了更高的要求，提升产品质、降低不良率、节约成本成为液晶面板行业共同努力的目标。
目前液晶显示面板上常规的制备透明薄膜电极的方法为剥离工艺(Lift off)。例如，现有的薄膜晶体管的制备工艺流程为：参见图1A所示，在衬底基板10上依次形成栅极11、栅极绝缘层12、有源层13、欧姆接触层14、源/漏极15及绝缘层16；参见图1B所示，在所述绝缘层16上形成光阻层17，蚀刻所述绝缘层16，形成过孔18；参见图1C，沉积透明导电薄膜后去除光阻层17及其上沉积的透明导电薄膜，在过孔18中形成像素电极19。
现有的剥离工艺的缺点在于，在剥离制程中采用正常过孔设计，透明导电薄膜(ITO)并不能够完全覆盖过孔，如图1C所示，过孔位置电性连接处漏极的金属部分裸露，后续制程中可能造成金属腐蚀，导致接触电阻增大，形成暗点或暗线，增加产品缺陷，降低产品品质和可靠性。
发明内容
本发明所要解决的技术问题是，提供一种薄膜晶体管阵列基板及其制备方法，其能够使像素电极完全覆盖过孔位置电性连接处的金属，克服金属裸露带来的问题。
为了解决上述问题，本发明提供了一种薄膜晶体管阵列基板的制备方法，包括如下步骤：提供一衬底基板，在衬底基板上依次形成栅极、栅极绝缘层、有源层、欧姆接触层、源/漏极及绝缘层；在所述绝缘层上涂布光阻层；对该光阻层进行曝光，使该光阻层图案化，在欲形成像素电极的对应位置暴露出绝缘层，并且形成分布在暴露的绝缘层周缘的第一光阻区域及分布在第一光阻区域外围的第二光阻区域，所述第一光阻区域的光阻层的厚度小于所述第二光阻区域的光阻层的厚度；通过蚀刻制程移除暴露的绝缘层，形成过孔，暴露出漏极，所述第一光阻区域对应过孔上方边缘；对光阻层进行灰化处理，去除所述第一光阻区域，暴露出所述过孔侧壁，保留部分第二光阻区域；在所述过孔中形成像素电极，所述像素电极覆盖所述过孔侧壁，形成薄膜晶体管阵列基板。
进一步，所述第一光阻区域朝向过孔的边缘与所述过孔的边缘齐平。
进一步，所述第一光阻区域朝向过孔的边缘突出于所述过孔的边缘。
进一步，在图案化光阻层的步骤中，采用灰阶色调光罩图案化所述光阻层。
进一步，在图案化光阻层的步骤中，采用半色调光罩图案化所述光阻层。
本发明还提供一种薄膜晶体管阵列基板，包括衬底基板，在衬底基板上依次形成栅极、栅极绝缘层、有源层、欧姆接触层、源/漏极及绝缘层，所述绝缘层具有一过孔，所述过孔暴露出所述漏极，像素电极设置在所述过孔中，且所述像素电极覆盖所述过孔侧壁。
进一步，所述像素电极延伸至所述过孔边缘且覆盖部分绝缘层表面。
本发明的优点在于，在过孔处设置与其他位置不同厚度的光阻层，减薄过孔处光阻层厚度，干刻形成过孔后，利用氧气灰化光阻层，使得过孔处的光刻胶被去除，暴露出过孔的侧壁，进行后续工艺中可实现ITO全覆盖电气连接处金属。
附图说明
图1A～图1C是现有的薄膜晶体管的制备工艺流程。
图2是本发明薄膜晶体管阵列基板制备方法的步骤示意图；
图3A～图3J是本发明薄膜晶体管阵列基板制备方法的工艺流程图；
图4A及图4B是过孔处的光罩示意图。
具体实施方式
下面结合附图对本发明提供的薄膜晶体管阵列基板及其制备方法的具体实施方式做详细说明。
本发明提供一种薄膜晶体管阵列基板的制备方法，参见图2，所述方法包括如下步骤：步骤S200、提供一衬底基板，在衬底基板上依次形成栅极、栅极绝缘层、有源层、欧姆接触层、源/漏极及绝缘层；步骤S201、在所述绝缘层上涂布光阻层；步骤S202、对该光阻层进行曝光，使该光阻层图案化，在欲形成像素电极的对应位置暴露出绝缘层，并且形成分布在暴露的绝缘层周缘的第一光阻区域及分布在第一光阻区域外围的第二光阻区域，所述第一光阻区域的光阻层的厚度小于所述第二光阻区域的光阻层的厚度；步骤S203、通过蚀刻制程移除暴露的绝缘层，形成过孔，暴露出漏极，所述第一光阻区域对应过孔上方边缘；步骤S204、对光阻层进行灰化处理，去除所述第一光阻区域，暴露出所述过孔侧壁，保留部分第二光阻区域；步骤S205、在所述过孔中形成像素电极，所述像素电极覆盖所述过孔侧壁，形成薄膜晶体管阵列基板。
图3A～图3J是本发明薄膜晶体管阵列基板的制备方法的工艺流程图。
步骤S200，提供一衬底基板，在衬底基板上依次形成栅极、栅极绝缘层、有源层、欧姆接触层、源/漏极及绝缘层。
具体制备过程如下：
如图3A所示，提供一衬底基板300，在衬底基板300上形成第一金属层301。所述衬底基板300可以为透明基板，优选为玻璃基板。进一步，在本具体实施方式中，可采用金属沉积的方法形成第一金属层301。
如图3B所示，采用第一道光罩制程对所述第一金属层301进行图案化处理，并蚀刻去除未被光阻覆盖的第一金属层301，形成栅极302。在本具体实施方式中，形成所述栅极的方法具体是在所述第一金属层301上形成第一光阻层(附图中未标示)，通过第一道光罩制程对所述第一光阻层进行灰阶曝光，使所述第一光阻层图案化，通过蚀刻制程移除未被所述第一光阻层覆盖的第一金属层，去除所述第一光阻层，从而形成栅极302。
参见图3C所示，在所述栅极302及未被所述栅极302覆盖的衬底基板300上依次形成栅极绝缘层303、有源层基层304、欧姆接触层基层305及第二金属层306。在本具体实施方式中，用CVD成膜的方法在所述栅极302及未被所述栅极302覆盖的衬底基板300上覆盖上SiNx作为栅极绝缘层303，继续连续沉积a-Si:H和N+layer分别作为有源层基层304和欧姆接触层基层305，并在所述欧姆接触层基层305上沉积第二金属层306。
参见图3D所示，在所述第二金属层306表面形成半灰阶光罩光阻图形(附图中未标示)，采用第二道光罩制程对所述有源层基层304、欧姆接触层基层305及第二金属层306进行图案化处理，并采用交替采用两次湿法蚀刻及干法蚀刻去除未被所述半灰阶光罩光阻覆盖的区域，形成与所述栅极对应的有源层308、欧姆接触层309及源/漏极310。在本具体实施方式中，在所述第二金属层306表面形成半灰阶光罩光阻图形(HTM光罩光阻图形)，采用第二道光罩制程对所述有源层基层304、欧姆接触层基层305及第二金属层306进行图案化处理，并依次进行第一次湿法蚀刻、第一次干法蚀刻、第二次湿法蚀刻及第二次干法蚀刻去除未被所述半灰阶光罩光阻覆盖的区域，形成与所述栅极对应的有源层308、欧姆接触层309及源/漏极310。
参见图3E所示，在所述源/漏极310上及未被所述源/漏极310覆盖的衬底基板300上形成绝缘层311。在本具体实施方式中，采用CVD方法沉积所述绝缘层311。
步骤S201、参见图3F所示，在所述绝缘层311上涂布光阻层312。所述光阻层312的材料及涂布方法为本领域常规材料及方法，本领域技术人员可从现有技术中获取。
步骤S202、参见图3G，对该光阻层312进行曝光，使该光阻层312图案化，在欲形成像素电极的对应位置暴露出绝缘层311，并且形成分布在暴露的绝缘层311周缘的第一光阻区域313及分布在第一光阻区域313外围的第二光阻区域314。所述第一光阻区域313的光阻层的厚度小于所述第二光阻区域314的光阻层的厚度。在本具体实施方式中，所述第一光阻区域313的范围很小，其主要覆盖后续形成的过孔上方的边缘，以在后续制程中能够被去除，暴露出过孔的侧壁。进一步，在该步骤中，采用灰阶色调光罩(GTM)或者采用半色调光罩(HTM)图案化所述光阻层图案化所述光阻层，其中图4A及图4B显示了在过孔处的光罩设计示意图。
步骤S203、参见图3H，通过蚀刻制程移除暴露的绝缘层311，形成过孔315，暴露出漏极310，所述第一光阻区域313对应过孔315上方边缘。所述第一光阻区域朝向过孔315的边缘与所述过孔315的边缘齐平，或者所述第一光阻区域朝向过孔315的边缘突出于所述过孔315的边缘，如图3H所示情况。
步骤S204、参见图3I，对光阻层进行灰化处理，去除所述第一光阻区域313，暴露出所述过孔315侧壁，保留部分第二光阻区域314。此步骤之后，过孔315被完全暴露，其侧壁也没有被光阻层遮挡。
步骤S205、参见图3J，在所述过孔315中形成像素电极316，所述像素电极316覆盖所述过孔315侧壁，形成薄膜晶体管阵列基板。该步骤的具体过程为：步骤S204之后，沉积透明导电薄膜；去除第二光阻区域314及覆盖在其上的透明导电薄膜，形成像素电极。
参见图3J，本发明还提供一种薄膜晶体管阵列基板。所述薄膜晶体管阵列基板包括衬底基板300，在衬底基板300上依次形成栅极302、栅极绝缘层303、有源层308、欧姆接触层309、源/漏极310及绝缘层311，所述绝缘层311具有一过孔315，所述过孔315暴露出所述漏极，像素电极316设置在所述过孔315中，且所述像素电极316覆盖所述过孔315侧壁。优选地，所述像素电极316延伸至所述过孔315边缘且覆盖部分绝缘层311表面。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (3)

1.一种薄膜晶体管阵列基板的制备方法，其特征在于，包括如下步骤：
提供一衬底基板，在衬底基板上依次形成栅极、栅极绝缘层、有源层、欧姆接触层、源/漏极及绝缘层；
在所述绝缘层上涂布光阻层；
对该光阻层进行曝光，使该光阻层图案化，在欲形成像素电极的对应位置暴露出绝缘层，并且形成分布在暴露的绝缘层周缘的第一光阻区域及分布在第一光阻区域外围的第二光阻区域，所述第一光阻区域的光阻层的厚度小于所述第二光阻区域的光阻层的厚度；
通过蚀刻制程移除暴露的绝缘层，形成过孔，暴露出漏极，所述第一光阻区域对应过孔上方边缘；
对光阻层进行灰化处理，去除所述第一光阻区域，暴露出所述过孔侧壁，保留部分第二光阻区域；
在所述过孔中形成像素电极，所述像素电极覆盖所述过孔侧壁，形成薄膜晶体管阵列基板；其中，
所述第一光阻区域朝向过孔的边缘与所述过孔的边缘齐平，或者，所述第一光阻区域朝向过孔的边缘突出于所述过孔的边缘。
2.根据权利要求1所述的薄膜晶体管阵列基板的制备方法，其特征在于，在图案化光阻层的步骤中，采用灰阶色调光罩图案化所述光阻层。
3.根据权利要求1所述的薄膜晶体管阵列基板的制备方法，其特征在于，在图案化光阻层的步骤中，采用半色调光罩图案化所述光阻层。
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