CN107181488A - A kind of circuit structure for removing clock jitter - Google Patents
A kind of circuit structure for removing clock jitter Download PDFInfo
- Publication number
- CN107181488A CN107181488A CN201710424171.0A CN201710424171A CN107181488A CN 107181488 A CN107181488 A CN 107181488A CN 201710424171 A CN201710424171 A CN 201710424171A CN 107181488 A CN107181488 A CN 107181488A
- Authority
- CN
- China
- Prior art keywords
- clock
- processor
- jitter
- timing chip
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005516 engineering process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000003313 weakening effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/104—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional signal from outside the loop for setting or controlling a parameter in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a kind of circuit structure for removing clock jitter, it is related to voicefrequency circuit technical field.It includes oscillator, processor and clock timing chip, oscillator exports clock, clock is input in processor, processor is divided is output to clock timing chip to after suitable frequency, clock timing chip filters out clock the clock signal stablized, PLL circuit frequency multiplication through clock timing chip internal is input to processor to original frequency, and clock signal now is very significantly improved compared to the signal that oscillator is exported.The present invention can effectively weaken the jitter in clock signal, and the clock signal stablized improves tonequality.
Description
Technical field
The present invention relates to voicefrequency circuit technical field, and in particular to a kind of circuit structure of removal clock jitter.
Background technology
Oscillator produce clock signal all can existence time shake, this is unavoidable, time jitter (jitter)
Refer to that high-speed serial signals edge arrives the deviation at moment and ideal moment, schematic diagram such as Fig. 1, and due to production technology and material
Difference, the degree of time jitter can be different.In voicefrequency circuit, time jitter is very for the influence of sound quality
Important, so needing high-precision clock signal.The shake of clock is increasingly taken seriously in digital circuit, and it not only can
The maximum rate of digital interface and the dynamic range of A/D conversions are limited, and the bit error rate of telecommunication circuit, many audios can be increased
The tonequality of equipment is not high, caused by very big factor is time jitter.Based on this, a kind of circuit knot for removing clock jitter is designed
Structure is particularly necessary.
The content of the invention
In view of the shortcomings of the prior art, the present invention seeks to be to provide a kind of circuit for removing clock jitter
Structure, it is simple in construction, it is reasonable in design, it can effectively weaken the jitter in clock signal, the clock signal stablized, it is ensured that sound
Matter, it is practical reliable, it is easy to promote the use of.
To achieve these goals, the present invention is to realize by the following technical solutions：One kind removes clock jitter
Circuit structure, clock is input to processor by including oscillator, processor and clock timing chip, oscillator output clock
In, clock timing chip is output to after processor frequency dividing to suitable frequency, clock timing chip, which filters out clock, obtains stabilization
Clock signal, the PLL circuit frequency multiplication through clock timing chip internal is input to processor to original frequency, clock now
Signal is very significantly improved compared to the signal that oscillator is exported.
Preferably, described clock timing chip uses clock timing chip CS2300.
Beneficial effects of the present invention：Weaken the jitter in clock signal, reduce the bit error rate of signal transmission, be prevented effectively from
Influence tonequality.
Brief description of the drawings
Describe the present invention in detail with reference to the accompanying drawings and detailed description；
Fig. 1 is the time jitter schematic diagram of background technology；
Fig. 2 is structural representation of the invention.
Embodiment
To be easy to understand the technical means, the inventive features, the objects and the advantages of the present invention, with reference to
Embodiment, is expanded on further the present invention.
Reference picture 2, present embodiment uses following technical scheme：A kind of circuit structure for removing clock jitter,
Clock timing chip including oscillator, processor and for weakening jitter, clock timing chip uses chip CS2300, should
Chip internal contains PLL circuit, oscillator output clock, because the clock come out from oscillator has very big jitter, institute
With the clock not exported using oscillator directly, clock is input in processor, processor frequency dividing arrives defeated after suitable frequency
Go out to clock timing chip, clock timing chip filters out clock the clock signal stablized, through PLL circuit frequency multiplication to originally
Frequency be input to processor, clock signal now is very significantly improved compared to the signal that oscillator is exported.
Present embodiment oscillator is to provide the clock source required for processor, and chip CS2300 is for weakening very
To the device for eliminating jitter, the effect of whole circuit is to obtain the clock for the not containing time jitter letter required for processor
Number.Its specific signal trend is as follows：The clock frequency X (high frequency) exported from oscillator contains very big jitter, to pass through
Clock timing chip is filtered out, in order to reach more preferable effect, it is necessary to which X frequency is reduced, so X is input into processor point
1. and 2. suitable frequency X/N is obtained after frequency, path is as shown in Fig. 2, and clock signal passes through the filter of clock timing chip internal
Except circuit, the signal stablized, then processor is input to by frequency X of the frequency multiplication of phase locked loop before, path as shown in 3.,
The jitter compositions that signal now contains are seldom, reduce clock in the bit error rate of signal transmission, lifting voicefrequency circuit and believe
Number accuracy, improve tonequality, it is practical reliable, with wide market application foreground.
The general principle and principal character and advantages of the present invention of the present invention has been shown and described above.The technology of the industry
Personnel are it should be appreciated that the present invention is not limited to the above embodiments, and the simply explanation described in above-described embodiment and specification is originally
The principle of invention, without departing from the spirit and scope of the present invention, various changes and modifications of the present invention are possible, these changes
Change and improvement all fall within the protetion scope of the claimed invention.The claimed scope of the invention by appended claims and its
Equivalent thereof.
Claims (2)
1. a kind of circuit structure for removing clock jitter, it is characterised in that including oscillator, processor and clock timing core
Piece, oscillator output clock, clock is input in processor, and clock timing is output to after processor frequency dividing to suitable frequency
Chip, clock timing chip filters out clock the clock signal stablized, the PLL circuit frequency multiplication through clock timing chip internal
Processor is input to original frequency.
2. a kind of circuit structure for removing clock jitter according to claim 1, it is characterised in that described clock meter
When chip use clock timing chip CS2300.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710424171.0A CN107181488A (en) | 2017-06-07 | 2017-06-07 | A kind of circuit structure for removing clock jitter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710424171.0A CN107181488A (en) | 2017-06-07 | 2017-06-07 | A kind of circuit structure for removing clock jitter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107181488A true CN107181488A (en) | 2017-09-19 |
Family
ID=59836850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710424171.0A Pending CN107181488A (en) | 2017-06-07 | 2017-06-07 | A kind of circuit structure for removing clock jitter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107181488A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107809241A (en) * | 2017-11-07 | 2018-03-16 | 晶晨半导体(上海)股份有限公司 | A kind of frequency dividing adjusting method of PLL |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105612704A (en) * | 2013-10-02 | 2016-05-25 | 哈利法科学技术研究大学 | Method and devices for time and frequency synchronization using a phase locked loop |
| CN105656477A (en) * | 2015-12-30 | 2016-06-08 | 深圳大学 | Delay-locked loop and method for preventing error locking |
| CN105871371A (en) * | 2016-03-25 | 2016-08-17 | 东南大学 | Three-segment time-to-digital conversion circuit based on phase-locked loop |
| CN106059574A (en) * | 2015-04-17 | 2016-10-26 | 台湾积体电路制造股份有限公司 | Circuit for digitizing phase differences, pll circuit and method for the same |
| CN106664093A (en) * | 2014-07-02 | 2017-05-10 | 泰拉丁公司 | Edge generator-based phase locked loop reference clock generator for automated test system |
-
2017
- 2017-06-07 CN CN201710424171.0A patent/CN107181488A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105612704A (en) * | 2013-10-02 | 2016-05-25 | 哈利法科学技术研究大学 | Method and devices for time and frequency synchronization using a phase locked loop |
| CN106664093A (en) * | 2014-07-02 | 2017-05-10 | 泰拉丁公司 | Edge generator-based phase locked loop reference clock generator for automated test system |
| CN106059574A (en) * | 2015-04-17 | 2016-10-26 | 台湾积体电路制造股份有限公司 | Circuit for digitizing phase differences, pll circuit and method for the same |
| CN105656477A (en) * | 2015-12-30 | 2016-06-08 | 深圳大学 | Delay-locked loop and method for preventing error locking |
| CN105871371A (en) * | 2016-03-25 | 2016-08-17 | 东南大学 | Three-segment time-to-digital conversion circuit based on phase-locked loop |
Non-Patent Citations (1)
| Title |
|---|
| CIRRUS LOGIC: "《CS2300-03 datasheet》", 8 February 2008 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107809241A (en) * | 2017-11-07 | 2018-03-16 | 晶晨半导体(上海)股份有限公司 | A kind of frequency dividing adjusting method of PLL |
| CN107809241B (en) * | 2017-11-07 | 2021-08-06 | 晶晨半导体(上海)股份有限公司 | PLL frequency division adjusting method |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170919 |