CN107180610B

CN107180610B - Display panel and array substrate thereof

Info

Publication number: CN107180610B
Application number: CN201610140171.3A
Authority: CN
Inventors: 严志成
Original assignee: EverDisplay Optronics Shanghai Co Ltd
Current assignee: EverDisplay Optronics Shanghai Co Ltd
Priority date: 2016-03-11
Filing date: 2016-03-11
Publication date: 2020-06-02
Anticipated expiration: 2036-03-11
Also published as: CN107180610A

Abstract

The invention provides a display panel and an array substrate, wherein the array substrate comprises: a pixel array including a plurality of pixel units; n scanning lines extending in a row direction, wherein each of the 2 nd to N-1 th scanning lines is shared by two adjacent rows of pixel units, N is an integer greater than 2, wherein the shared scanning lines provide scanning signals to the two adjacent rows of pixel units sharing the scanning lines, the scanning signals serve as first scanning signals for one row of pixel units under the scanning lines sharing the scanning lines and serve as second scanning signals for one row of pixel units on the scanning lines sharing the scanning lines, and a plurality of data lines extend in a column direction, intersect with and are insulated from the plurality of scanning lines; and a plurality of light emitting signal lines extending in the row direction, each light emitting signal line being located between two adjacent scanning lines. The display panel and the array substrate provided by the invention can improve the resolution of the display panel.

Description

Display panel and array substrate thereof

Technical Field

The invention relates to the technical field of display, in particular to a display panel and an array substrate thereof.

Background

In recent years, the OLED (Organic Light-Emitting Diode) technology has been developed rapidly, and has become a promising technology for replacing the LCD (Liquid Crystal Display) most probably.

In the conventional OLED display panel design, the driving circuit of each pixel needs 2 to 3 scan signals for driving, and therefore, there are usually 2 to 3 scan lines for providing the scan signals in the space corresponding to one pixel. Specifically, referring to fig. 1 and 2, fig. 1 shows a schematic diagram of a pixel of one embodiment of the prior art, and fig. 2 shows a schematic diagram of a pixel driving circuit of another embodiment of the prior art. In fig. 1, a first scan line 110A supplying a first scan signal, a second scan line 110B supplying a second scan signal, and a light emitting signal line 120 supplying a light emitting signal pass through a space of a rectangular pixel 100 in the X direction. In such a pixel design, the pixel 100 has a rectangular shape, and a space through which two scanning lines pass is required in the Y direction. In fig. 1, the size of the pixel 100 is approximately 31.62um 63.24 um. In the pixel driving circuit shown in fig. 2, since the pixel 100 needs to have 3 scanning signals for driving, the pixel 100 needs to have a space through which three scanning lines (110A, 110B, and 110C) pass.

However, as the resolution requirements of display panels increase, the size of the display panel pixels needs to be reduced to address such needs. In the prior art, because 2 to 3 scanning lines are required to pass through in the space of each pixel, it is difficult to further reduce the size of the pixel to improve the resolution of the display panel.

Disclosure of Invention

In order to overcome the defects in the prior art, the present invention provides a display panel and an array substrate thereof, which can effectively reduce the design space and improve the resolution of the display panel.

The invention provides an array substrate, comprising: a pixel array including a plurality of pixel units arranged in a row direction and a column direction; n scanning lines extending in the row direction, wherein each of the 2 nd to N-1 th scanning lines is shared by two adjacent rows of pixel units, N being an integer greater than 2, wherein the shared scanning lines supply scanning signals to the two adjacent rows of pixel units sharing the scanning line, the scanning signals serving as first scanning signals for a row of pixel units below the scanning line sharing the scanning line and serving as second scanning signals for a row of pixel units above the scanning line sharing the scanning line, and a plurality of data lines extending in the column direction, intersecting and insulated from the plurality of scanning lines; and a plurality of light emitting signal lines extending in the row direction, each of the light emitting signal lines being located between two adjacent scanning lines.

Preferably, a data line is disposed between two adjacent columns of pixel units, and each data line is coupled to one column of pixel units.

Preferably, each of the pixel units includes: a first terminal coupled to a scan line under the pixel unit; and a second terminal coupled to the scan line on the pixel unit, each shared scan line being coupled to one of the first terminals and one of the second terminals between two adjacent data lines.

Preferably, two of the second ends coupled to a common scan line are spaced apart by one of the first ends coupled to the scan line.

Preferably, the two second ends coupled to one common scan line are spaced with or without two first ends coupled to the scan line.

Preferably, each of the pixel units further includes: a capacitor, a thin film transistor and a light emitting diode.

Preferably, in each pixel unit, the number of the thin film transistors is 4 to 6.

Preferably, in each pixel unit, the number of the thin film transistors is 6, and the pixel unit includes: a first transistor, a gate of the first transistor coupled with the first terminal, a first pole of the first transistor coupled with the data line; a second transistor having a gate coupled to a first node, a first pole coupled to a second pole of the first transistor; a third transistor having a gate coupled to the first end, a first pole coupled to a second pole of the second transistor, and a second pole coupled to the first node; a fourth transistor, a gate of the fourth transistor being coupled to the light emitting signal line, a first pole of the fourth transistor being coupled to the second pole of the first transistor, and a second pole of the fourth transistor being coupled to a common voltage; a fifth transistor, a gate of the fifth transistor being coupled to the light emitting signal line, a first pole of the fifth transistor being coupled to the second pole of the second transistor, and a second pole of the fifth transistor being coupled to the anode of the light emitting diode; a sixth transistor, a gate of which is coupled to the second terminal, a first pole of which is coupled to a pin voltage, and a second pole of which is coupled to the first node, wherein a cathode of the light emitting diode is grounded, the first node is coupled to the first pole of the capacitor, and the second pole of the capacitor is coupled to the common voltage.

Preferably, the light emitting diode is an organic light emitting diode.

Preferably, the method further comprises the following steps: and a plurality of common power lines extending in a column direction, crossing the plurality of scan lines and insulated therefrom, for supplying a common voltage to the pixel units.

Preferably, the pixel cell has a non-rectangular shape.

According to another aspect of the present invention, there is also provided a display panel including the array substrate as described above.

Compared with the prior art, the scanning signals provided by one scanning line are respectively used as the first scanning signals and the second scanning signals of two rows of pixel units, so that one scanning line is shared by two adjacent rows of pixel units. Because the scanning lines are shared, the number of the scanning lines of the whole display panel is reduced, the design space is effectively reduced, and the resolution of the display panel is improved and the manufacturing cost of the display panel is reduced.

Drawings

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 shows a schematic diagram of a pixel of one embodiment of the prior art.

Fig. 2 shows a schematic diagram of a pixel driving circuit of another embodiment of the prior art.

Fig. 3 is a schematic diagram of a display panel according to an embodiment of the invention.

Fig. 4 is a schematic view of an array substrate according to an embodiment of the present invention.

Fig. 5 is a schematic view of an array substrate according to another embodiment of the present invention.

FIG. 6 is a diagram of a pixel cell according to one embodiment of the invention.

Fig. 7 is a schematic diagram of a pixel driving circuit according to an embodiment of the invention.

Fig. 8 is a waveform diagram of part of signals in the pixel driving circuit shown in fig. 7.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their repetitive description will be omitted.

The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In some instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the invention.

The drawings of the present invention are only for illustrating the relative positional relationship, and the dimensions of some parts are exaggerated in the drawing for easy understanding, and the dimensions in the drawings do not represent the proportional relationship of the actual dimensions.

In order to solve the problem that the resolution of a display panel is difficult to improve by reducing the size of a pixel unit in the prior art, the invention provides the display panel and an array substrate thereof.

The display panel provided by the invention is shown in fig. 3. The display panel may be an OLED display panel. Referring to fig. 3, the OLED display panel includes at least an array substrate 10, a scan driver 20, a data driver 30, and a light emitting signal driver 40 provided in the present invention. Other devices and/or elements may also be included in the OLED display panel. The array substrate 10 has a plurality of pixel units 11. Each pixel unit 11 may be coupled to a scan line (S1 to Sn), a light emitting signal line (EM1 to EMn), and a data line (D1 to Dm).

The plurality of pixel units 11 on the array substrate 10 may display an image to correspond to a first power source (e.g., common power ELVDD) provided from the outside and a second power source (e.g., ground ELVSS) provided from the outside. The plurality of pixel units 11 on the array substrate 10 may also display images corresponding to scan signals supplied from the scan lines S1 to Sn generated by the scan driver 20 and light emission signals supplied from the light emission signal lines EM1 to EMn generated by the light emission signal driver 40 and data signals supplied from the data lines D1 to Dm generated by the data driver 30.

In this embodiment, the scan signal and the light-emitting signal are generated by different drivers, respectively, and in other embodiments, the scan signal and the light-emitting signal may be generated by the same driver. For example, the scan signal and the light emission signal may be generated by the scan driver 20. The scan signal generated by the scan driver 20 may be sequentially supplied to the scan lines (S1 to Sn), and the light emission signal may be sequentially supplied to each of the light emission signal lines (EM1 to EMn). The scan signal and the light emission signal may also be supplied to the scan lines S1 to Sn and the light emission signal lines EM1 to EMn, respectively, out of order.

The data driver 30 may receive input signals, for example, RGB data, and may generate data signals corresponding to the received input signals. The data signals generated in the data driver 30 may be supplied to the pixel unit 11 through the data lines (D1 to Dm) so as to be synchronized with the scan signals. The data signals may also be supplied to the data lines D1 through Dm in a manner asynchronous with the scan signals.

Fig. 4 and 5 respectively show two embodiments of the array substrate provided by the present invention.

Referring first to fig. 4, the array substrate 200 includes a pixel array composed of a plurality of pixel units 210, a plurality of scan lines (S1-S4), a plurality of data lines (D1-D6), and a plurality of light emitting signal lines (EM1-EM 3).

The pixel array includes a plurality of pixel units 210 arranged in an X direction (i.e., a row direction) and a Y direction (i.e., a column direction). The pixel cell 210 preferably has a non-rectangular shape. For example, the pixel unit 210 has an elliptical shape inclined with respect to the Y direction. Preferably, the pixel unit 210 emits light by an organic light emitting technology. Each pixel unit 210 may include a first terminal a coupled to a scan line positioned under the pixel unit 210 and a second terminal B coupled to a scan line positioned on the pixel unit 210. The under-pixel unit 210 described herein may refer to passing through the pixel unit 210 and being located at a lower portion of the pixel unit 210 or being located at a lower side of the pixel unit 210. Similarly, the above-mentioned on the pixel unit 210 may refer to passing through the pixel unit 210 and being located on the upper portion of the pixel unit 210 or on the upper side of the pixel unit 210. Specifically, taking the first pixel unit 210P in the second row as an example, it includes a first terminal a coupled to the scan line S3 located at the lower portion of the pixel unit 210P and a second terminal B coupled to the scan line S2 located at the upper portion of the pixel unit 210P. Specifically, the pixel unit 210 may include a thin film transistor, a capacitor, and a light emitting diode. Other electrical elements may also be included in the pixel cell 210. The thin film transistor, the capacitor and the light emitting diode in the pixel unit 210 constitute a driving circuit of the pixel unit 210. The first terminal a and the second terminal B may be terminals for receiving signals in the driving circuit of the pixel unit 210.

A plurality of scanning lines (S1-S4) extend in the X direction. When the number of the scanning lines is N (N is an integer larger than 2), each scanning line from the 2 nd scanning line to the (N-1) th scanning line is shared by two adjacent rows of pixel units. In the present embodiment, 4 scan lines are schematically shown. Wherein the 2 nd scanning line S2 is shared by the first and second rows of pixel cells. The 3 rd scan S3 is shared by the second and third rows of pixel cells.

Specifically, the shared scanning line supplies a scanning signal to the pixel units of two adjacent rows sharing the scanning line. The scanning signal is used as a first scanning signal of a row of pixel units under the scanning line and sharing the scanning line, and is used as a second scanning signal of a row of pixel units on the scanning line and sharing the scanning line. The under scan line described herein includes the case of being completely under and overlapping the scan line but mostly under the scan line. Similarly, the above-mentioned case of being located on the scan line includes the case of being located completely under and overlapping the scan line but mostly located on the scan line.

For example, the 2 nd common scan line supplies scan signals to the first and second rows of pixel cells of the common scan line S2. The scan line S2 provides the scan signal as the first scan signal for the second row of pixel cells under the scan line S2 on the common scan line S2, and as the second scan signal for the first row of pixel cells on the scan line S2 on the common scan line S2. For another example, the 3 rd common scan line provides scan signals to the second and third rows of pixel cells of the common scan line S3. The scan line S3 provides the scan signal as the first scan signal for the third row of pixel cells under the scan line S3 and the common scan line S3 and as the second scan signal for the second row of pixel cells over the scan line S3 and the common scan line S3. While the scan line S1 and the scan line S4 are not shared, the scan line S1 provides the first scan signal only to the first row of pixel cells, and the scan line S4 provides the second scan signal only to the third row of pixel cells.

Correspondingly, each pixel unit receives a first scanning signal provided by a scanning line positioned above the pixel unit and receives a second scanning signal provided by a scanning line positioned below the pixel unit. For example, the pixel unit 210P receives a first scan signal provided by the scan line S2 through the second terminal B coupled to the scan line S2 located above the pixel unit 210P, and receives a second scan signal provided by the scan line S3 through the first terminal a coupled to the scan line S3 located below the pixel unit 210P.

The scanning lines are shared by the scanning lines and the first ends A and the second ends B of the pixel units in two adjacent rows through coupling, and the scanning lines provide scanning signals for the pixel units in the two adjacent rows, so that the number of the scanning lines required for driving the pixel units is reduced.

A plurality of data lines (D1-D6) extend in the Y direction, intersect with the plurality of scanning lines (S1-S4), and are insulated. And a data line is arranged between two adjacent columns of pixel units. For example, one data line D2 is provided between the first and second columns of pixel cells, and one data line D3 is provided between the second and third columns of pixel cells. Each data line is coupled to a column of pixel cells. For example, data line D1 is coupled to a first column of pixel cells, data line D2 is coupled to a second column of pixel cells, and so on. For clarity, the coupling of the data line and the pixel unit is not shown, but those skilled in the art can appreciate that in a specific implementation, the coupling of the data line and the pixel unit can be realized through a laminated structure of electric elements in the pixel unit or through hole arrangement.

Specifically, each shared scan line is coupled to a first terminal a and a second terminal B between two adjacent data lines. And the scan lines not shared are coupled only to the first terminal a or only to the second terminal B. For example, the 2 nd scan line S2, which is commonly used, is coupled between the data line D1 and the data line D2 with one first terminal a and one second terminal B. The 1 st scan line S1 not shared is coupled only to the second terminal B. In the embodiment shown in fig. 4, two second terminals B coupled to a common scan line are spaced apart by a first terminal a coupled to the scan line. For example, the common scan line S2 couples a plurality of first terminals a and a plurality of second terminals B, and adjacent two second terminals B are spaced by one first terminal a. In other words, the first terminal a and the second terminal B are repeatedly arranged in the form of the first terminal a, the second terminal B, the first terminal a, and the second terminal B on the common scan line.

A plurality of light emitting signal lines (EM1-EM3) extend in the X direction, each light emitting signal line being located between two adjacent scan lines. For example, the light emitting signal line EM1 is located between the scan line S1 and the scan line S2.

As shown in fig. 4, the array substrate 200 provided by the present invention reduces the number of scan lines on the display panel and reduces the manufacturing cost of the array substrate by sharing the scan lines. Compared with the prior art, if the same number of scanning lines exist, the size of the pixel unit 210 can be reduced, more pixel units are formed, and the resolution of the display panel is further improved. Meanwhile, in the present invention, the pixel unit 210 has a non-rectangular shape, so that the size of the pixel unit 210 can be relatively reduced, and the resolution of the display panel can be further improved. Specifically, in the manner provided by the present invention, the size of the pixel cell 210 may be reduced to 17.3um by 34.6 um.

The array substrate 200' shown in fig. 5 is similar in structure to the array substrate 200 shown in fig. 4. Unlike the array substrate 200 shown in fig. 4, in fig. 5, two second ends B coupled to one common scan line are spaced apart by two first ends a coupled to the scan line or are not spaced apart by the first ends a. For example, the two second terminals B coupled to the common scan line S2 are spaced apart by the two first terminals a coupled to the scan line S2, or the first terminals a are not spaced apart. In other words, the first terminal a and the second terminal B are repeatedly arranged in the form of the first terminal a, the second terminal B, and the first terminal a on the common scan line. The arrangement of the first end a and the second end B is not limited to this, for example, the arrangement of the first end a and the second end B on different shared scanning lines may be different. The first end a and the second end B are disposed such that the shape of the pixel unit 210 is changed, and therefore, different arrangements of the first end a and the second end B can be implemented according to the requirement of the display panel in the specific manufacturing process.

The above-mentioned figures 4 and 5 only schematically show two embodiments of the invention, and further variants can be implemented by a person skilled in the art on the basis of the above description.

The structure of the pixel unit and the structure of the pixel unit driving circuit in the embodiment of the invention are described below with reference to fig. 6 to 8.

Fig. 6 shows a schematic diagram of a pixel cell 210 according to an embodiment of the invention. Specifically, in fig. 6, the scan line Sn-1, the scan line Sn, and the light emitting signal line EM pass through the pixel unit 210. The pixel unit 210 shares the scan line Sn-1 with a pixel unit located on the pixel unit 210. The pixel unit 210 shares the scan line Sn with a pixel unit located under the pixel unit 210. In the embodiment shown in fig. 6, the pixel cell 210 has a slanted elliptical shape.

With continued reference to fig. 7, fig. 7 illustrates a pixel driving circuit corresponding to the pixel cell 210 shown in fig. 6. The pixel unit 210 preferably includes a capacitor, a thin film transistor, and a light emitting diode. The light emitting diode is preferably an organic light emitting diode. The number of thin film transistors in each pixel unit is preferably 4 to 6. In the embodiment shown in fig. 7, an embodiment of 6 thin film transistors is shown.

Specifically, the gate of the first transistor T1 is coupled to the first terminal a (the first terminal a is coupled to the scan line Sn-1), and the first pole of the first transistor is coupled to the Data line Data. The gate of the second transistor T2 is coupled to the first node N1, and the first pole of the second transistor is coupled to the second pole of the first transistor T1. The gate of the third transistor T3 is coupled to the first terminal a, the first pole of the third transistor T3 is coupled to the second pole of the second transistor T2, and the second pole of the third transistor T3 is coupled to the first node N1. A gate of the fourth transistor T4 is coupled to the light emitting signal line EM, a first pole of the fourth transistor T4 is coupled to the second pole of the first transistor T1, and a second pole of the fourth transistor T4 is coupled to the common voltage ELVDD. A gate of the fifth transistor T5 is coupled to the light emitting signal line EM, a first pole of the fifth transistor T5 is coupled to the second pole of the second transistor T2, and a second pole of the fifth transistor T5 is coupled to the anode of the light emitting diode 211. The gate of the sixth transistor T6 is coupled to the second terminal B (the second terminal B is coupled to the scan line Sn), the first pole of the sixth transistor T6 is coupled to the pin voltage Vint, and the second pole of the sixth transistor T6 is coupled to the first node N1. The cathode of the light emitting diode 211 is grounded to ELVSS. The first node N1 is coupled to a first pole of the capacitor Cst. The second pole of the capacitor Cst is coupled to the common voltage ELVDD.

Wherein, the first pole and the second pole of the thin film transistor (T1-T6) are respectively referred to as the source and the drain of the thin film transistor (T1-T6). For example, the first electrode of the thin film transistor (T1-T6) is the source electrode, and the second electrode is the drain electrode. The correspondence between the source and drain of the thin film transistor (T1-T6) and the first and second electrodes is determined by the specific situation, but not limited thereto.

Specifically, the common voltage ELVDD is supplied from a common power line. The common power line is preferably parallel to the data line, and crosses and is insulated from the scan line.

The driving process of the light emitting diode 211 will be described with reference to the signal waveform diagrams shown in fig. 7 and 8.

The light emission signal line EM supplies a light emission signal to the pixel unit 210. The scan line Sn-1 provides a first scan signal to the pixel unit 210 (at the same time, the scan signal provided by the scan line Sn-1 also serves as a second scan signal to the pixel unit on the pixel unit 210). The scan line Sn supplies a second scan signal to the pixel unit 210 (at the same time, the scan signal supplied by the scan line Sn also serves as a first scan signal supplied to a pixel unit under the pixel unit 210). The Data lines Data supply Data signals to the pixel unit 210.

In the period of S310 shown in fig. 8, the first scan signal supplied from the scan line Sn-1 is low, the sixth transistor T6 is turned on, and the potential of the first node N1 is initialized to the pin voltage Vint. Since the gate of the second thin film transistor T2 is coupled to the first node N1, the gate voltage Vg of the second thin film transistor T2 is equal to the pin voltage Vint.

In the period of S320, the second scan signal supplied from the scan line Sn is low, and the first and third thin film transistors T1 and T3 coupled to the scan line Sn are turned on. The source and drain electrodes of the second thin film transistor T2 are shorted. At this time, the second thin film transistor T2 corresponds to a diode. Voltage V of Data line Data_dataThe voltage of the first node N1 becomes V by the first thin film transistor T1 and the second thin film transistor T2_dataAnd a threshold voltage V of the second thin film transistor T2_thThe sum of (T2).

In the period of S330, the light emitting signal line EM supplies the light emitting signal low, the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned on, and the light emitting diode 211 starts emitting light. At this time, the gate voltage of the second thin film transistor T2 is the same as the voltage of the first node N1. Since the first node N1 is coupled to the capacitor Cst, the voltage of the first node N1 does not abruptly change. In other words, in the period of S330, the gate voltage of the second thin film transistor T2 is the same as the value of the voltage of the first node N1 in the period of S320 described above. The voltage of the first electrode (e.g., source) of the second thin film transistor T2 is equal to the common voltage ELVDD. A voltage V between the gate and the first electrode of the second thin film transistor T2_gs＝V_data+V_th(T2) -ELVDD. The second pole (e.g., drain) voltage of the second thin film transistor T2 is influenced by the voltage of the light emitting diode 211 (e.g., organic light emitting diode OLED). A voltage V between the first and second poles of the second thin film transistor T2_dsIn the range of ELVSS-ELVDD + Von_(OLED)To 0 volts. Wherein, Von_(OLED)Refers to the voltage passing through the organic light emitting diode OLED211 when the organic light emitting diode OLED211 is turned on.

The above descriptions of fig. 6 to 8 are merely schematic illustrations of implementations of the driving circuit of the pixel unit, and the present invention is not limited thereto. Those skilled in the art can implement more modifications in combination with the content of the description, and detailed descriptions thereof are omitted here.

Compared with the prior art, the scanning signals provided by one scanning line are respectively used as the first scanning signals and the second scanning signals of two rows of pixel units, so that one scanning line is shared by two adjacent rows of pixel units. Because the scanning lines are shared, the number of the scanning lines of the whole display panel is reduced, and the resolution of the display panel is improved and the manufacturing cost of the display panel is reduced.

Exemplary embodiments of the present invention are specifically illustrated and described above. It is to be understood that the invention is not to be limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims.

Claims

1. An array substrate, comprising:

a pixel array including a plurality of pixel units arranged in a row direction and a column direction, each pixel unit including only one light emitting diode;

n scanning lines extending in the row direction, wherein each of the 2 nd to N-1 th scanning lines is shared by two adjacent rows of the pixel units, N is an integer greater than 2,

the shared scanning line supplies, to the pixel units of two adjacent rows sharing the scanning line, a scanning signal as a first scanning signal for the pixel units of a row below the scanning line sharing the scanning line and as a second scanning signal for the pixel units of a row above the scanning line sharing the scanning line,

a plurality of data lines extending in the column direction, intersecting the N scanning lines, and insulated therefrom; and

a plurality of light emitting signal lines extending in the row direction, each of the light emitting signal lines being located between two adjacent scanning lines, wherein each of the pixel units includes:

a first terminal coupled to the scan line under the pixel unit;

a second terminal coupled to the scan line on the pixel unit,

wherein the pixel unit has a non-rectangular shape determined according to the arrangement of the first and second ends of the pixel unit;

two second ends coupled with the scanning lines shared by two adjacent rows of the pixel units are spaced by one first end coupled with the same scanning line; or

Two first ends coupled with the same scanning line or no first ends are arranged between two second ends coupled with the scanning line shared by two adjacent rows of the pixel units.

2. The array substrate of claim 1, wherein one data line is disposed between two adjacent columns of the pixel units, and each data line is coupled to one column of the pixel units.

3. The array substrate of claim 2, wherein each of the scan lines shared by two adjacent rows of the pixel units is coupled to one of the first terminals and one of the second terminals between two adjacent ones of the data lines.

4. The array substrate of claim 3, wherein each of the pixel cells further comprises: a capacitor, a thin film transistor and a light emitting diode.

5. The array substrate of claim 4, wherein the number of the thin film transistors in each pixel unit is 4 to 6.

6. The array substrate of claim 4, wherein the number of the thin film transistors in each of the pixel units is 6, and each of the pixel units comprises:

a first transistor, a gate of the first transistor being coupled to the first terminal, a first pole of the first transistor other than the gate being coupled to the data line;

a second transistor, a gate of the second transistor being coupled to the first node, a first pole of the second transistor other than the gate being coupled to a second pole of the first transistor other than the gate;

a third transistor, a gate of the third transistor being coupled to the first end, a first pole of the third transistor other than the gate being coupled to a second pole of the second transistor other than the gate, the second pole of the third transistor other than the gate being coupled to the first node;

a fourth transistor, a gate of the fourth transistor being coupled to the light emitting signal line, a first pole of the fourth transistor other than the gate being coupled to the second pole of the first transistor, a second pole of the fourth transistor other than the gate being coupled to a common voltage;

a fifth transistor, a gate of which is coupled to the light emitting signal line, a first pole of which except for the gate is coupled to the second pole of the second transistor, and a second pole of which except for the gate is coupled to an anode of the light emitting diode;

a sixth transistor having a gate coupled to the second terminal, a first pole of the sixth transistor other than the gate coupled to a pin voltage, a second pole of the sixth transistor other than the gate coupled to the first node,

wherein a cathode of the light emitting diode is grounded, the first node is coupled to a first pole of the capacitor, and a second pole of the capacitor is coupled to the common voltage.

7. The array substrate of any one of claims 4 to 6, wherein the light emitting diode is an organic light emitting diode.

8. The array substrate of any one of claims 1 to 6, further comprising:

and a plurality of common power lines extending in the column direction, crossing and insulated from the N scan lines, and supplying a common voltage to the pixel units.

9. A display panel comprising the array substrate according to any one of claims 1 to 8.