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CN107017221B - 集成电路组合件 - Google Patents

集成电路组合件 Download PDF

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Publication number
CN107017221B
CN107017221B CN201610909215.4A CN201610909215A CN107017221B CN 107017221 B CN107017221 B CN 107017221B CN 201610909215 A CN201610909215 A CN 201610909215A CN 107017221 B CN107017221 B CN 107017221B
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Prior art keywords
die
ground connection
dap
conductive filler
connection traces
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CN201610909215.4A
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CN107017221A (zh
Inventor
李汉蒙@尤金·李
阿尼斯·福齐·宾·阿卜杜勒·阿齐兹
休安·利姆·伟·芬
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

本申请案涉及一种集成电路组合件。集成电路IC裸片包含顶面及底面、位于所述顶面与所述底面之间的多个分隔开的接地连接迹线；其中所述裸片中的孔暴露所述多个分隔开的接地连接迹线。

Description

集成电路组合件
技术领域
本申请案涉及一种集成电路组合件。
背景技术
集成电路(“IC”)芯片/裸片为了实用性而必须彼此电连接或连接到其它电子组件。由导电金属(例如铜、银或金)制成的引线框通常用于将IC裸片电连接到其它电子组件。将IC裸片连接到引线框的一种流行且灵活的方法是导线结合。结合导线通常由铝、铜或金组成。在高功率应用中，结合导线直径通常在从约15μm到几百μm的范围中。存在两个基本类型的导线结合-球体结合及楔结合。
球体结合通常是利用热量、压力及超声能量的组合来执行。在球体结合中，小的熔融球体凭借通过视为固定及分配导线的毛细管的工具施加高电压电荷而形成在结合导线的端部处。熔融球体放置在芯片的电接触表面上。接触表面通常是铜或铝。接着施加热量、压力及超声能量的组合，其在球体与接触表面之间产生焊缝。球体结合有时候称为第一结合，因为其通常是在将IC裸片导线结合到引线框时制造的第一结合。
在裸片-引线框互连中，通常用于将结合导线的第二端连接到引线框的导线结合的类型称为楔结合或有时候称为第二结合。其是通过将结合导线的端部挤压在引线框或其它金属表面与毛细管工具的尖端之间并同时对连接区域加热而形成。在对裸片附接垫(DAP)执行楔结合(也称作缝合结合)时可导致附接的裸片从DAP中分层。
发明内容
一种集成电路(IC)裸片，其包含位于裸片的顶面与底面之间的多个分隔开的接地连接迹线，其中所述裸片中的孔暴露所述多个分隔开的接地连接迹线。还描述了一种通过由导电材料填充孔且将裸片附接到引线框的组合件及其制造方法，其中没有结合导线附接到裸片附接垫。
附图说明
图1是现有技术裸片及引线框组合件的俯视平面图。
图2是裸片及引线框组合件的俯视平面图。
图3是本文中揭示的新裸片制造过程的初始阶段处的裸片晶片的俯视平面图。
图4是在本文中揭示的新裸片制造过程的另一阶段处安装在晶片环上的裸片晶片的俯视平面图。
图5是图4的裸片晶片及晶片环的俯视平面图，其中每一裸片部分中形成中心孔。
图6是图5的裸片晶片及晶片环在晶片单一化/切块之后的俯视平面图。
图7是引线框的俯视平面图，其中图6的单一化裸片中的一者安装在引线框的裸片附接垫上。
图8是图7的其中具有钻孔的裸片的部分的放大等距视图。
图9是图8的已经用导电材料填充孔之后的放大视图。
图10是图6的裸片及引线框的横截面视图。
图11是制造集成电路组合件的方法的流程图。
图12是消除集成电路封装中的接地导线与信号导线之间的导线偏移的方法的流程图。
具体实施方式
图1是现有技术裸片及引线框组合件的俯视平面图。引线框10具有裸片附接垫(DAP)12及多个引线14。裸片16安装在DAP 12上。裸片16具有顶面18，其包含多个裸片电接触表面22。第一多个结合导线30在其第一端处球体结合到裸片接触表面22且在其第二端处缝合结合到引线14。第二多个结合导线32球体结合到与裸片16内的接地迹线连接的某些裸片接触表面23。此类导线32的相对端缝合结合到DAP 12。
“导线偏移”是指当结合导线并未正确地对准在水平平面中时发生的IC封装制造问题。导线偏移可发生在导线结合过程期间、导线结合后的处置期间或模制期间。导线偏移可通过改变相邻导线及SSN(同步切换噪声)的相互感应而影响电性能。如果导线触碰，那么导线将短路。与导线结合相关联的另一问题是，形成在裸片附接垫(DAP)上的缝合结合可导致安装在DAP上的裸片从其中分层。
申请人已经开发出消除对电连接到接地迹线的结合导线的需要的裸片。图2中说明了包含安装在引线框60的DAP 62上的此裸片66的裸片/引线框组合件。结合导线80将未连接到接地迹线的裸片接触表面72连接到引线64。此类结合导线80仅连接到引线框引线64，而未连接到DAP 62。裸片中的接地迹线通过填充延伸穿过裸片66的孔69的导电填充物材料68电连接到DAP 62。导电材料68暴露在裸片66的底部处。裸片66内的接地迹线(图2中未示出)电接触导电填充物材料68。
下文参考图3到9详细地描述可类似于或相似于裸片66的裸片116及此裸片116产生并安装在引线框上的方法。将裸片中的接地迹线连接到DAP的结合导线的消除降低了导线偏移的风险。连接到DAP的结合导线的这种减少有效地增加了剩余结合导线之间的空间。附接到DAP的结合导线的移除避免了DAP上的导线缝合及由导线缝合引起的裸片/DAP分层的问题。
图3是裸片晶片100在晶片制造后的俯视平面图。
图4是图1的裸片晶片100安装在常规晶片环102上以供处理的俯视平面图。
图5是图4的裸片晶片100及晶片环102的俯视平面图，其中将最终变为裸片的每一晶片部分中形成中心孔104。此类孔104可常规地通过机械或激光钻孔而产生。在一个实例实施例中，孔104延伸穿过晶片100的整个厚度。
图6是图5的裸片晶片100及晶片环102在切块(单一化)之后的俯视平面图。在单一化期间，晶片100沿锯道106单一化以将晶片分离为多个个别裸片116，每一裸片116具有从其中延伸穿过的孔104。
图7是引线框110的俯视平面图，其中图6的单一化裸片116中的一者安装在引线框110的裸片附接垫(DAP)112上。引线框110具有位于DAP 112周围的多个引线114。
图8是图7的裸片116中含有中心孔104的部分的放大等距视图。孔104暴露多个平坦接地迹线122、124、126及128，其在裸片衬底内是以平行、分隔开、堆叠关系布置。
图9是图8的在用导电材料130(例如银环氧树脂或其它导电填充物材料)填充孔104之后的放大视图。
图10是图7的裸片116及DAP 112的横截面视图，其中裸片116中的孔104已经填充有导电填充物材料130。填充物材料130电连接接地迹线122、124、126及128。填充物材料可直接连接到DAP 112或其可由一层其它导电附接材料132(例如导电粘附剂、焊料或其它导电附接材料)连接到DAP。在此实施例中，孔104完全延伸穿过裸片104，即，其延伸穿过裸片的顶面117及底面118。在其它实施例(未示出)中，孔104及填充物130从裸片的底面118向上延伸足够远以暴露并连接全部导电迹线122、124、126、128，但是并未延伸到裸片的顶面117。结合导线142、144将其第一端通过球体结合141、143连接到提供在裸片116的顶面117上的电接触表面，且将其第二端通过缝合结合145、147连接到引线114。没有结合导线附接到DAP 112。
如先前所讨论，图2是可相同于裸片116的裸片66的俯视平面图，裸片66附接到可相同于引线框110的引线框60。
图10是制造集成电路组合件的方法的流程图。所述方法包含如方框301处所示，通过在裸片中形成与IC裸片中的接地连接迹线相交的孔暴露接地连接迹线。
图11是消除集成电路封装中的接地导线与信号导线之间的导线偏移的方法的流程图。所述方法包括如方框401处所示，在裸片中提供多个堆叠接地连接迹线；及如方框402处所示，形成穿过裸片的孔以暴露接地连接迹线。
本文详细地明确揭示了集成电路(IC)裸片的实施例，所述IC裸片包含位于裸片的顶面与底面之间的多个分隔开的接地连接迹线，其中裸片中具有孔，所述孔暴露所述多个分隔开的接地连接迹线。本文中还明确揭示了制造此裸片及其结合引线框的各种使用的方法。本领域技术人员在阅读本发明之后可明白此集成电路裸片及其制造及使用方法的各个替代性实施例。希望所附权利要求书被广泛地解释为涵盖除现有技术限制的实施例之外的此类替代性实施例。

Claims (15)

1.一种集成电路IC裸片，其包括：
顶面及底面；
位于所述顶面与所述底面之间的多个分隔开的接地连接迹线；
其中所述裸片中的孔从所述底面向上延伸足够远以暴露所述多个分隔开的接地连接迹线；以及
填充所述孔且暴露在所述裸片的底部处的导电填充物，以使得所述导电填充物电连接所述多个接地连接迹线；
其中，所述裸片安装在裸片附接垫DAP上，并且所述孔中的所述导电填充物通过在所述裸片的底部处经暴露的所述导电填充物电连接到所述DAP。
2.根据权利要求1所述的IC裸片，其中所述孔延伸穿过所述顶面及所述底面。
3.一种包括集成电路IC裸片的IC封装，
所述IC裸片具有顶面及底面以及位于所述顶面与所述底面之间的多个分隔开的接地连接迹线；
其中所述IC裸片中的孔从所述底面向上延伸足够远以暴露所述接地连接迹线；
所述IC封装进一步包括填充所述孔且暴露在所述裸片的底部处的导电填充物，以使得所述导电填充物电连接所述接地连接迹线；并且
其中所述IC裸片安装在裸片附接垫DAP上，其中所述孔中的所述导电填充物通过在所述IC裸片的底部处经暴露的所述导电填充物电连接到所述DAP。
4.根据权利要求3所述的IC封装，其中所述IC裸片中的所述孔延伸穿过所述IC裸片的所述顶面及所述底面。
5.一种制造集成电路IC组合件的方法，其包括：
通过在IC裸片中制造与所述裸片中的接地连接迹线相交的孔来暴露所述接地连接迹线；
用导电填充物填充所述孔；以及
将所述IC裸片附接到引线框裸片附接垫DAP，使得所述导电填充物暴露在所述IC裸片的底部处以通过在所述IC裸片的底部处经暴露的所述导电填充物电连接到所述DAP；
其中所述暴露接地连接迹线包括将所述孔从所述IC裸片的底面向上延伸足够远以暴露所述接地连接迹线。
6.根据权利要求5所述的方法，其中所述暴露接地连接迹线进一步包括将所述孔延伸穿过所述IC裸片的顶面与所述底面。
7.根据权利要求5所述的方法，其进一步包括用所述引线框的引线而非所述DAP将接触表面导线结合在所述裸片的顶面上。
8.根据权利要求7所述的方法，其进一步包括将所述裸片及引线框囊封在模具化合物中。
9.根据权利要求8所述的方法，其进一步包括将所述引线的经暴露表面部分电镀。
10.根据权利要求7所述的方法，其进一步包括将经囊封的所述引线框与相邻经囊封的所述引线框单一化。
11.一种集成电路IC封装，其包括：
IC裸片，所述IC裸片具有顶面及底面，以及自所述顶面延伸到所述底面的导电材料，所述导电材料占据自所述顶面延伸到所述底面的孔，且暴露在所述IC裸片的底部处，以连接到所述IC裸片中的多个接地连接迹线；以及
引线框，所述引线框包括裸片附接垫和引线组，所述裸片附接垫通过在所述IC裸片的底面处经暴露的所述导电材料电连接到所述导电材料。
12.根据权利要求11所述的IC封装，其进一步包括模具化合物，所述模具化合物囊封所述IC裸片及所述引线框。
13.根据权利要求11所述的IC封装，其中所述孔包括圆柱形。
14.根据权利要求11所述的IC封装，其中所述多个接地连接迹线被布置为彼此平行且分隔开。
15.根据权利要求11所述的IC封装，其中所述导电材料包含银环氧树脂。
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