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CN107017169B - 导电外部连接器结构、半导体器件及形成方法 - Google Patents

导电外部连接器结构、半导体器件及形成方法 Download PDF

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Publication number
CN107017169B
CN107017169B CN201611001301.1A CN201611001301A CN107017169B CN 107017169 B CN107017169 B CN 107017169B CN 201611001301 A CN201611001301 A CN 201611001301A CN 107017169 B CN107017169 B CN 107017169B
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China
Prior art keywords
substrate
forming
electroplating
solder
external electrical
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CN107017169A (zh
Inventor
施孟甫
罗俊彦
黄震麟
陈文明
黄建铭
刘原甫
郑咏全
黄威志
刘承勋
詹前彬
徐玉女
林奇鸿
庞德勋
古进誉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

讨论了外部电连接件和形成这种外部电连接件的方法,一种方法包括在衬底上形成外部电连接结构。形成外部电连接结构包括在第一溶液中的衬底处产生的第一搅拌等级的情况下在衬底上电镀柱。该方法还包括在第二溶液中的衬底处产生的第二搅拌等级的情况下,在外部电连接结构上电镀焊料。在衬底处产生的第二搅拌等级大于在衬底处产生的第一搅拌等级。电镀焊料还包括在外部电连接结构的侧壁上形成外壳。本发明还提供了半导体器件及形成方法。

Description

导电外部连接器结构、半导体器件及形成方法
技术领域
本发明一般地涉及半导体技术领域,更具体地,涉及半导体器件及其形成方法。
背景技术
由于许多电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度的不断提高,半导体工业经历了快速发展。在大多数情况下,这种集成密度的提高源自最小部件尺寸(例如,将半导体工艺节点缩小为亚20nm节点)的反复减小,其允许更多的部件集成在给定的区域内。
在一些情况下,这种改进的集成密度已经导致更小的集成电路管芯。用于在更高密度中布置更小的外部电连接器需求可能导致集成电路管芯的尺寸的减小。然而,更小的外部电连接器和其更高密度会引起先前可能没有遇到的问题。
发明内容
根据本发明的一方面,提供了一种用于形成半导体器件的方法包括:在衬底上形成外部电连接结构,形成所述外部电连接结构包括在第一溶液中的所述衬底处产生的第一搅拌等级的情况下,在所述衬底上电镀柱;以及在第二溶液中的所述衬底处产生的第二搅拌等级的情况下,在所述外部电连接结构上电镀焊料,在所述衬底处产生的所述第二搅拌等级大于在所述衬底处产生的所述第一搅拌等级,电镀所述焊料还包括在所述外部电连接结构的侧壁上形成外壳。
根据本发明的另一方面,提供了一种用于形成半导体器件的方法包括:使用第一电镀系统在衬底上的电镀柱,所述柱为外部电连接结构的至少一部分,所述第一电镀系统包括第一搅拌器,所述第一搅拌器在电镀所述柱期间在第一电镀溶液中以第一频率进行往复运动;以及使用第二电镀系统在所述外部电连接结构上电镀焊料,所述第二电镀系统包括第二搅拌器,所述第二搅拌器在电镀所述焊料期间在第二电镀溶液中以第二频率进行往复运动,所述第二频率大于所述第一频率,电镀所述焊料还包括沿着所述外部电连接结构的侧壁形成外壳。
根据本发明的又一方面,提供了一种用于形成半导体器件的方法包括:在所述衬底上形成凸块下金属(UBM);在所述凸块下金属上形成掩模,穿过所述掩模的开口暴露所述凸块下金属的一部分;在穿过所述掩模的所述开口中的所述凸块下金属上电镀柱,所述柱为外部电连接件的一部分;以及在所述外部电连接件上电镀焊料,电镀所述焊料还包括使所述掩模伸缩以导致介于所述外部电连接件的侧壁和所述掩模之间的间隙,沿着所述外部电连接件的侧壁并且在所述外部电连接件的侧壁和所述掩模之间的间隙中形成外壳。
根据本发明的又一方面,提供了一种半导体器件包括:导电柱,在衬底上方位于导电构件上方;可回流材料,位于所述导电柱上方,其中,所述可回流材料还包括:第一部分,位于所述导电柱的第一表面上方,其中,所述第一表面背背离所述导电构件,其中,所述第一部分具有第一浓度的第一组分;第二部分,所述第二部分定位为邻近于所述导电柱的第二表面但是不完全覆盖所述导电柱的第二表面,其中,所述第二表面从所述第一表面朝向所述衬底延伸,其中,所述第二部分具有第二浓度的所述第一组分,所述第二浓度大于所述第一浓度。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以最佳地理解本发明的各个实施例。应该注意,根据工业中的标准实践,各个部件没有被按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以被任意增加或减少。
图1至图4示出了根据一些实施例的在制造导电外部连接件过程中的中间步骤的截面图。
图5是根据一些实施例的导电外部连接件的制造的流程图。
图6是根据一些实施例的使用电镀系统的简化示图。
图7是根据一些实施例的在图6的电镀系统中屏蔽板的第一实例的截面图。
图8是根据一些实施例的在图6的电镀系统中屏蔽板的第二实例的截面图。
图9是根据一些实施例的在图6的电镀系统中搅拌器的实例的截面图。
图10是根据一些实施例的在图6的电镀系统中包括屏蔽板的实例的阳极模块的分解立体图。
图11是根据一些实施例的在图6的电镀系统中搅拌器的实例的截面图。
图12示出了根据一些实施例的用于电镀的流程图。
具体实施方式
以下公开内容提供了多种不同实施例或实例,以实现本发明的不同特征。下面描述组件和布置的具体实例以简化本发明。当然,这些仅是实例并且不意欲限制本发明。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例,也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。另外,本发明可以在各个实例中重复参考标号和/或字符。这种重复是为了简化和清楚的目的,并且其本身并不表示所讨论的实施例和/或配置之间的关系。
此外,为了便于描述,本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语,以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外,空间关系术语旨在包括器件在使用或操作过程中的不同方位。装置可以以其他方式定位(旋转90度或在其他方位),并且在本文中使用的空间关系描述符可以同样地作相应地解释。
在此所讨论的实施例可以在具体的上下文中讨论,即在诸如集成电路管芯的衬底上形成导电外部连接器,诸如在其上具有焊料的柱,以及形成这种导电连接件的方法。其他实施例预期其他应用,诸如本领域普通技术人员在阅读本发明之后,将容易理解封装件等。应该注意,本文讨论的实施例不必示出可能存在于结构中的每一个元件或部件。例如,诸如当讨论一个元件可能足以表达实施例的各个方面时,可从附图中省略多个部件。此外,本文中讨论的方法实施例可能被论述为以特定顺序实施;然而,可以以任何逻辑顺序实施其他方法实施例。
图1至图4示出的根据本发明一些实施例的在导电外部连接件的制造过程中的中间步骤的截面图,并且图5是根据一些实施例的导电外部连接件的制造的流程图。将会在图1至图4的截面图的上下文中讨论图5的步骤。在接下来示出的上下文的实施例中描述的导电外部连接件是在金属柱上具有焊料的金属柱。其它实施例可以包括不同的柱结构、不同的材料等。
在图1中和在图5的步骤100中,提供了具有通过一个或多个介电层54和56暴露的导电焊盘52的衬底50。在示出的实施例中,衬底50是集成电路管芯,从而其还可以是晶圆的一部分(例如,在分割之前)。衬底50可以包括诸如块状半导体衬底、绝缘体上半导体(SOI)衬底、多层或梯度衬底等的半导体衬底。半导体衬底的半导体可以包括任何半导体材料,例如,诸如硅、锗等元素半导体;化合物或合金半导体等;或它们的组合。半导体衬底还可以是晶圆,例如,其还可以是块状硅晶圆。可以在半导体衬底中和/或上形成诸如晶体管、二极管、电容器、电阻器等的器件,并且可以通过由例如半导体衬底上的一个或多个介电层中的金属化图案所形成的互连结构互连,以形成集成电路管芯的集成电路。
导电焊盘52位于衬底50上。为了提供与集成电路管芯的集成电路的外部连接,导电焊盘52可以形成在衬底50上方并且与在衬底50中的互连结构电接触。导电焊盘52可以位于被称为衬底50(或集成电路管芯)的有源侧上。在一些实施例中,导电焊盘52可以形成在例如衬底50的最上部介电层的表面上。导电焊盘52可以包括薄晶种层与晶种层上方的导电材料。晶种层可以包括通过物理气相沉积(PVD)等所沉积的铜、钛、镍、金、锡等或它们的组合。导电焊盘52的导电材料可以是通过电化学电镀工艺、化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)等或它们的组合所沉积的铝、铜、钨、银、金、锡等或它们的组合。
如图1所示,第一介电层54形成在衬底50上以及在导电焊盘52上方。第一介电层54(例如,钝化层)可以是通过CVD、PVD、ALD、电介质上旋涂工艺等或它们的组合沉积的一种或多种合适的介电材料,诸如氧化硅、氮化硅、诸如掺杂碳氧化物的低k电介质等。通过第一介电层54形成开口以暴露导电焊盘52的一部分。可以通过例如蚀刻、研磨、激光技术等或者它们的组合来形成开口。
如图1所示,然后第二介电层56形成在第一介电层54上以及在导电焊盘52的上方。第二介电层56可以是一种或多种合适的介电材料,例如,诸如聚酰亚胺的聚合物、聚苯并恶唑(PBO)、苯并环丁烯(BCB)等。第二介电层56可以通过诸如电介质上旋涂工艺、层压工艺等或它们的组合的工艺形成。开口形成为通过第二介电层56并且通过第一介电层54中的开口以暴露导电焊盘52的一部分。当第二介电层56是感光物等或它们的组合时,可以通过例如蚀刻、研磨、激光技术形成开口,从而将第二介电层56暴露于光。
然后,凸块底部金属(UBM)沿着穿过第二介电层56的开口的表面,形成在第二介电层56上以及导电焊盘52的暴露部分上。在一些实施例中,UBM是金属层,其中,UBM可以是单层或者包括由不同材料形成的多个子层的复合层,并且可以使用PVD等来沉积该UBM。
在示出的实施例中和在图5的步骤102中,UBM的形成包括至少在导电焊盘52上形成粘合层58。如图1所示,粘合层58沿着穿过第二介电层56的开口的表面形成在第二介电层56上以及导电焊盘52的暴露部分上。在一些实施例中,粘合层58是通过PVD等沉积的钛(Ti)、钨化钛(TiW)等。
此外,在示出的实施例中和在图5的步骤104中,UBM的形成还包括在粘合层58上形成的晶种层60。在一些实施例中,晶种层60是通过PVD等沉积的铜(Cu)等。
然后在图1中和在图5的步骤106中,在UBM上(例如,在晶种层60上)沉积并且图案化光刻胶62作为掩模。光刻胶62可以通过旋涂等形成并且可以暴露于光以用于图案化。光刻胶62的图案对应于形成的导电外部连接件的图案。图案化形成穿过光刻胶62的开口64,以暴露UBM(例如,晶种层60)。
在图2中和在图5的步骤108中,导电外部连接件的柱66电镀在光刻胶62的开口64中的UBM(例如,晶种层60)上。在一些实施例中,柱66是金属柱,其可以是铜(Cu)、铝(Al)、镍(Ni)、金(Au)、银(Ag)、钯(Pd)等或它们的组合。关于图6至图12进一步详细地讨论步骤108的电镀工艺的附加细节。
此外,在图2中和在图5的步骤110中,可选地,导电外部连接件的阻挡层68电镀在光刻胶62的开口64中的柱66上。在一些实施例中,阻挡层68是金属层,例如,从而可以降低或抑制在焊料和柱66之间的形成金属间化合物(IMC)的反应。在一些实施例中,诸如当柱66是铜时,阻挡层68是镍(Ni)等。关于图6至图12进一步详细地讨论步骤110的电镀工艺的附加细节。在一些实施例中阻挡层68可以被省略。
此外,在图2中和在图5的步骤112中,导电外部连接件的焊料70电镀在光刻胶62的开口64中的阻挡层68上。在一些实施例中,焊料70是诸如具有包括锡和银等的组合物的含锡焊料。焊料70可以是无铅焊料材料。在一些实施例中,焊料70具有锡和银的组合物,其中,锡是在焊料组合物的大约97.7%至大约98.5%的范围内,并且银在焊料组合物的大约1.5%至大约2.3%的范围内。在一些实施例中,诸如因为不同元素的不同电镀速度,贯穿焊料70的整个厚度焊料70的组合物可以改变。
根据一些实施例,通过电镀焊料70,如将参照图6至图12进一步详细讨论的,沿阻挡层68和/或柱66的侧壁形成的外壳72。外壳72可以是含锡材料。在一些实施例中,外壳72具有锡和银的组合物,其中,锡在外壳组合物的大约97.7%至大约98.5%的范围内,并且银在外壳组合物的大约1.5%至大约2.3%的范围内。在一些实施例中,诸如当柱66是铜时,诸如因为银可以以更高的速率电镀至柱66的侧壁,所以外壳72的组合物比焊料70的组合物可以具有略高比率的银。
在图3中和在步骤114中,去除光刻胶62。可以通过使用诸如氧等离子体灰化等的任何可接受的灰化或剥离工艺去除光刻胶62。
此外,在图3中和在步骤116中,蚀刻UBM(例如,晶种层60和粘合层58)以去除UBM未位于柱66之下的部分。在去除光刻胶62后,将会暴露晶种层60未位于柱66之下的部分。使用合适的蚀刻工艺蚀刻晶种层60的暴露部分和粘合层58的对应的下面部分。可以使用对于晶种层60和粘合层58的材料具有选择性的湿蚀刻,诸如盐酸(HCl)的蚀刻。
如图3中示出的,阻挡层68和柱66的侧壁可以具有从UBM(例如,晶种层60)的顶面至阻挡层68的顶面的第一尺寸D1(例如,高度)。此外,外壳72从阻挡层68的顶面并且沿着阻挡层68和柱66的侧壁延伸第二尺寸D2。第二尺寸D2可以在第一尺寸D1的大约50%至大约100%的范围内,诸如在第一尺寸D1的大约5%至大约10%的范围内。外壳72从阻挡层68的顶面延伸在阻挡层68和柱66之间的界面下方的一定距离。在一些实施例中,第一尺寸D1是大约40μm至大约70μm的范围内,并且第二尺寸D2是大约1μm至大约15μm的范围内。
在一些实施例中,UBM(例如,晶种层60)和柱66的至少部分具有例如铜的相同材料。在这些实施例中,去除UBM的暴露部分的蚀刻工艺也可以蚀刻在外壳72下面的柱66的暴露部分。柱66的蚀刻可以导致柱66在外壳72下方的底切部分74(通过虚线表示)被去除。在蚀刻期间,外壳72能够保护柱66免受蚀刻,其中,外壳72覆盖柱66。因此,柱66的下部可以具有第三尺寸D3(例如,宽度),从而该第三尺寸D3小于柱66的上部的第四尺寸D4(例如,宽度)。在其它实施例中,在UBM的蚀刻期间不蚀刻柱66。在一些实施例中,第三尺寸D3在大约38μm至大约68μm的范围内,并且第四尺寸D4在大约40μm至大约70μm的范围内。
如在图3中进一步示出的,外壳72沿着阻挡层68和/或柱66的侧壁可以具有第五尺寸D5(例如,厚度)。第六尺寸D6从外部导体互连件的第一侧的外壳72的外表面至外部导体互连件的相对侧的第二侧外壳72的另一个外表面。第七尺寸D7是焊料70的高度,其贯穿整个焊料70可以是基本上均匀的。第五尺寸D5可以小于(诸如基本上小于)第七尺寸D7。例如,第五尺寸D5可以在第七尺寸D7的1%至7%的范围内。在一些实施例中,第五尺寸D5等于或小于大约1μm;第六尺寸D6是大约25μm至大约90μm的范围内,并且第七尺寸D7在大约10μm至大约28μm的范围内。
在图4中和在图5的步骤118中,焊料70回流以形成回流焊料76。可以在能够充分融化焊料70的任何温度下执行回流,诸如,例如,等于或大于240℃。在焊料70回流步骤期间融化时,该焊料70的表面张力可能导致回流焊料76的外部表面是圆形的。在一些实施例中,外壳72在回流工艺期间可以回流并且在阻挡层68和/或柱66的侧壁上仍然保留该外壳72。在一些实施例中,其中,焊料70和外壳72具有锡和银的组合物,其中每一个的银比率由于回流工艺而降低。例如,银可以更容易地扩散到阻挡层68和/或柱66中。当焊料70和外壳72在回流之前具有大约97.7%至大约98.5%的锡和大约1.5%至大约2.3%的银的组合物时,在回流后,回流的焊料76和外壳72可以具有大约97.8%至大约98.6%的锡和大约1.4%至大约2.2%的银的组合物。在另一个实施例中,回流过程可能会导致在回流的焊料76和外壳72中形成金属间化合物(IMC)。IMC可以是通过在焊料70和外壳72的材料和阻挡层68和/或柱66的材料之间发生反应所形成的材料。例如,当外壳72是锡-银,柱66是铜,并且阻挡层68是镍时,在外壳72中的IMC可以是锡-铜合金和/或锡-镍合金。外壳72中的IMC可以具有从柱66的侧壁的厚度,该厚度等于或大于大约第五尺寸D5的一半。
第八尺寸D8是回流焊料76的最大高度。第五尺寸D5可以小于(诸如基本上小于)第八尺寸D8。例如,第五尺寸D5可以在第八尺寸D8的大约1%至大约5%的范围内中。在一些实施例中,第八尺寸D8在约15μm至约40μm的范围内。
虽然没有具体地示出,但是图4的结构可以进一步接合至如其它集成电路管芯、封装衬底等的其它封装组件。其它封装组件可以包括接合焊盘,其中回流焊料76通过使回流焊料76回流而附接至该结合焊盘。在阻挡层68(或当省略阻挡层68时的柱66)和其它封装组件的接合焊盘之间的尺寸可以大于(诸如基本上大于)外壳72的第五尺寸D5。
图6是根据一些实施例的使用电镀系统的简化示图。在一些实施例和一些电镀步骤中,电镀系统可以是EBARA Model UFP-A(EBARA的UFP-A型号)(来自EBARA Corporationheadquartered in Tokyo,Japan)。在其它实施例中和/或在其它电镀步骤中,电镀系统可以是NEXX Model Stratus 300(NEXX模型层300型号)(TEL NEXX,Inc.headquartered inthe United States)。
电镀系统包括储液槽200、阳极202、衬底保持器204、屏蔽板208,以及搅拌器220。在操作中,电镀溶液230位于储液槽200内,并且衬底保持器204(具有衬底50)和阳极202浸入电镀溶液230中。此外,在阳极202和衬底保持器204之间耦合电源206,使得电流可以通过电镀溶液230在阳极202和衬底50之间流动,从而导致材料镀在衬底50上。屏蔽板208在储液槽200中设置在阳极202和衬底保持器204之间并且屏蔽板208可以屏蔽外来电场以允许在基板50上的电镀更均匀。搅拌器220可以搅拌电镀溶液230,以随着电镀溶液230通过电镀工艺被耗尽,至少部分地将电镀溶液230混合为组合物更均匀。在这个实例中,通过使搅拌器220在垂直于电镀溶液230的顶面的方向222上(例如,在Z方向上)或者在平行于电镀溶液230的顶面并且与在阳极202和衬底保持器204之间的流动的电流交叉的方向224上(例如,在X方向上)往复运动可以引起搅拌器220的搅动。第九尺寸D9在阳极202和衬底保持器204之间。第十尺寸D10在衬底保持器204和搅拌器220之间。第十一尺寸D11在屏蔽板208和搅拌器220之间。第十二尺寸D12在屏蔽板208和阳极202之间。如随后将会讨论的,这些尺寸在电镀步骤之间可以保持相同或相似或者可以在电镀步骤之间改变。
电镀系统进一步包括循环单元,其包括具有来自于储液槽200的出口234和到达储液槽200的入口236。在电镀工艺期间,循环单元可以使储液槽200中的电镀溶液230循环,从而至少部分的混合电镀溶液230。电镀系统也包括具有到达储液槽200的入口240的补充液体池238和具有来自于储液槽200的出口234的废弃溶液液体池242。补充液体池238可以包括电镀溶液230的新鲜的、未耗尽的溶液源。废弃溶液液体池242可以包括用作的、废弃的电镀溶液230。废弃溶液液体池242可以通过出口244从储液槽200去除电镀溶液230,并且补充液体池238可以通过入口240将新的电镀溶液230添加至储液槽200。
图7至图9示出的诸如EBARA Model UFP-A的电镀系统的附加细节。图7和图8示出了分别沿着图6中的截面A-A的屏蔽板208a和208b的不同实例。屏蔽板208a和208b可以是诸如聚氯乙烯等的介电材料。屏蔽板208a和208b分别地具有开口250a和250b。开口250a和250b中的每个的直径小于衬底保持器204上的衬底50的直径。图9示出了沿着图6中的截面B-B的搅拌器220a的实例。搅拌器220a可以是涂覆有特氟隆等的诸如钛的金属。如示出的搅拌器220a是具有垂直缝隙260a(例如,沿着Z方向延伸)的矩形。在一些实施例中,搅拌器220a在方向224上振动。
图10和图11示出了诸如NEXX Model Stratus 300的另一电镀系统的附加细节。图10示出了包括屏蔽板208c的阳极模块的分解立体图。阳极模块以沿着Y方向的顺序包括屏蔽板208c、外部隔膜支撑件262、隔膜264、内部隔膜支撑件266、阳极保护罩(boot)268、阳极202和阳极周围的夹圈270、张紧器272、O形环274,以及阳极引杆276。阳极模块还包括在模块的顶部处的输入块278。图11示出了沿着图6中的截面B-B的搅拌器220b的实例。搅拌器220b可以是涂有特氟隆等的诸如钛的金属。如示出的搅拌器220b是具有水平缝隙260n(例如,沿着X方向延伸)的矩形。在一些实施例中,搅拌器220b在方向222上振动。
图12示出了根据一些实施例的用于电镀的工艺流程。首先将讨论图12的通用工艺,并且之后将讨论作为图5的108、110以及112的每个步骤所实施的图12的通用工艺的实施方式。此外,在图6的电镀系统的上下文中将讨论图12的操作。
在步骤300中,在衬底保持器204上的衬底50浸入具有期望储液槽布置的储液槽200中的电镀溶液230中。在步骤302中,启动搅拌以实现在衬底保持器204上的衬底50处产生的期望的搅拌等级和/或状态(condition)。在一些实施例中,通过搅拌器220在方向222和/或224上和/或与储液槽布置相结合的往复运动导致在衬底50处产生的搅拌等级和/或状态。
在步骤304中,接通电源206以供电给阳极202和衬底保持器204。在步骤306中,通过电流流经电镀溶液230导致期望材料被电镀在衬底50上。一旦通过电镀材料达到期望结构,在步骤308中关闭电源206并且在步骤310中关闭搅拌。此外,在步骤312中,从电镀溶液230中移除衬底50。
在图5的第一实施方式的实施例中,通常用于电镀步骤108、110以及112的一个或多个电镀系统具有相同的或相似的布置或配置。对于所有的电镀步骤108、110以及112可以使用相同的电镀系统,或者对于每个电镀步骤108、110以及112可以使用不同的电镀系统。在第一实施方式的实施例中,EBARA Model UFP-A用于电镀步骤108、110以及112中的每个步骤。例如,在第一实施方式的实施例中,如图6所示,可以在步骤108、110以及112中每个步骤期间使用如下电镀系统的尺寸:第九尺寸D9可以是大约90mm;第十尺寸D10可以在大约19mm至大约20mm的范围内,诸如大约19mm;第十一尺寸D11可以是在大约19mm至大约20mm的范围内,诸如大约19mm;第十二尺寸D12可以在大约50mm至大约52mm的范围内,诸如大约52mm。
通常在第一实施方式的实施例中,在电镀步骤112期间在衬底50处产生的期望的搅拌等级和/或状态大于在电镀步骤108和/或110期间的衬底50处产生的期望的搅拌等级和/或状态。通常在第一实施方式的实施例中,通过具有在步骤112期间比在步骤108和/或110期间增加搅拌器220的往复运动的频率导致在电镀步骤112期间更大的搅拌等级和/或状态。在一些其它的实施例中,通过具有在步骤112期间比在步骤108和/或110期间具有或不具有增加的频率情况下来增加搅拌器220的往复运动的幅度会导致在电镀步骤112期间更大的搅拌等级和/或状态。
根据图5的步骤108,衬底50浸入(步骤300)至在储液槽20中的电镀溶液230以电镀柱66。根据一些实施例,当柱66成为铜柱时,在步骤108中,可以将具有铜添加剂(诸如来自Enthone公司)的硫酸铜(II)(CuSO4)的铜基溶液(诸如来自BASF SE)用作电镀溶液230。打开搅动器(步骤302),并且例如在衬底50处产生期望的搅拌等级为低搅拌等级,其中,可以通过打开搅拌器220以在方向224中以等于或小于每分钟300转(RPM)的频率往复运动来实现该低搅拌等级。在搅拌器220的方向224中往复运动的幅度可以在大约50mm至大约100mm的范围内,诸如大约80mm。在这些情况下,如在图2至图4中示出的,接通电源206(步骤304)并且在衬底50上电镀铜(步骤306)以形成铜柱66。如本领域普通技术人员容易理解的,可以使用其它材料、溶液以及参数。一旦电镀期望材料(步骤306)并且断开电源和搅动器(步骤308和310),对于图5的步骤108,从电镀溶液230移除衬底50。
根据图5的可选步骤110,衬底50然后浸入在储液槽200内的电镀溶液230中,其中,该储液槽可以不同于步骤108的电镀工艺中使用的储液槽(但是可以是相同或相似的构造),以在柱66上电镀阻挡层68。根据一些实施例,当阻挡层68将为镍层时,在步骤110中可以使用基于氨基磺酸镍的镍溶液作为电镀溶液230。打开搅动器(步骤302),并且例如在衬底50处产生所需搅拌等级为低搅拌等级,可以通过打开搅拌器220以在方向224上以等于或小于每分钟300转(RPM)的频率的往复运动来实现该低搅拌等级。在搅拌器220的方向224上的往复运动的幅度可以在大约50mm至大约100mm的范围内,诸如大约80mm。用于步骤110的搅拌状态可以与步骤108中使用的搅拌状态相同,并且因此,在步骤110和108中,在衬底50处所产生搅拌等级可以是相同的。在这些情况下,如在图2至图4中示出的,接通电源206(步骤304)并且在柱66上电镀镍(步骤306)以形成镍的阻挡层68。如本领域普通技术人员容易理解的,可以使用其它材料、溶液以及参数。一旦电镀期望材料(步骤306)并且关闭电源和搅动器(步骤308和310),在图5的步骤110中,从电镀溶液230中移除衬底50。在其它的实施例中,省略步骤110并且因此省略阻挡层68。根据图5的步骤112,衬底50然后浸入(步骤300)储液槽200内的电镀溶液230中,其可以是不同于(但是可以是相同或相似的构造)步骤108和/或110的电镀工艺中使用的储液槽,以在阻挡层68(或当省略阻挡层68时的柱66)上电镀焊料70。根据一些实施例,当焊料70将具有锡-银组合物时,可以使用具有来自MitsubishiMaterials Corporation(三菱材料株式会社)的202系列添加剂的锡/银溶液。打开搅动器(步骤302),并且例如在衬底50处产生期望的搅拌等级为高搅拌等级,可以通过打开搅拌器220以在方向224上以等于或大于400RPM的频率往复运动来实现该高搅拌等级。在搅拌器220的方向224上的往复运动的幅度可以在大约50mm至大约100mm的范围内,诸如大约80mm。在步骤112中的衬底50处产生的搅拌等级大于在步骤108和110中的衬底50处的产生的搅拌等级。在这些情况下,如在图2至图4中示出的,接通电源206(步骤304)并且在阻挡层68和/或柱66上电镀焊料70和外壳72(步骤306)。如本领域普通技术人员容易理解的,可以使用其它材料、溶液以及参数。一旦电镀期望材料(步骤306)并且关闭电源和搅动器(步骤308和310),在图5的步骤110中,从电镀溶液230中移除衬底50。
在图5的第二实施方式的实施例中,通常用于电镀步骤112的电镀系统具有与用于电镀步骤108和/或110的一个或多个电镀系统不同的布置或配置。对于所有的电镀步骤108和110可以使用同一个电镀系统,并且对于电镀步骤112可以使用不同的电镀系统。对于电镀步骤108、110以及112中的每个电镀步骤可以使用不同的电镀系统。在第二实施方式的实施例中,EBARA Model UFP-A用于电镀步骤108和110中的每个步骤,并且NEXX ModelStratus 300用于电镀步骤112。例如,在第二实施方式的实施例中,如在图6中示出的,在每个步骤108和110期间可以使用如下电镀系统的尺寸:第九尺寸D9可以是大约90mm;第十尺寸D10可以在大约19mm至大约20mm的范围内,诸如大约19mm;第十一尺寸D11可以在大约19mm至大约20mm的范围内,诸如大约19mm;第十二尺寸D12可以在大约50mm至大约52mm的范围内,诸如大约52mm。此外,例如,在第二实施方式的实施例中,如在图6中示出的,可以在步骤112期间使用如下电镀系统的尺寸:第九尺寸D9可以是大约41mm;第十尺寸D10可以在从大约4mm至大约6mm的范围内,诸如大约5mm;第十一尺寸D11可以在大约13mm至大约23mm的范围内,诸如大约18mm;第十二尺寸D12可以在大约13mm至大约23mm的范围内,诸如大约18mm。
通常在第二实施方式的实施例中,在电镀步骤112期间的衬底50处产生的期望的搅拌等级和/或状态大于在电镀步骤108和/或110期间的衬底50处产生的期望的搅拌等级和/或状态。通常在第二实施方式的实施例中,通过在步骤112期间与在步骤108和/或110期间具有更靠近衬底50的搅拌器220和/或在不同方向上的往复运动导致在电镀步骤112期间的更大的搅拌等级和/或状态。
根据图5的步骤108,衬底50浸入(步骤300)储液槽20内的电镀溶液230中以电镀柱66。步骤108中储液槽200可以具有如以上描述的相对于该第二实施方式的实施例的步骤108的布置和构造。根据一些实施例,当柱66将为铜柱时,可以在步骤108中使用具有铜添加剂(诸如来自Enthone,Inc.)的基于硫酸铜(II)(CuSO4)的铜溶液(诸如来自BASF SE)作为电镀溶液230。打开搅动器(步骤302),并且例如在衬底50处产生的期望的搅拌等级为低搅拌等级,其中,可以通过打开搅拌器220以在方向224上(平行于电镀溶液230的顶面并且在X方向上与溶液230中的电流的流动交叉)以诸如大约240RPM至大约420RPM的范围内的频率(并且更具体地,诸如以大约350RPM)进行往复运动来实现该低搅拌等级。在搅拌器220的方向224上的往复运动的幅度可以在大约290mm至大约310mm的范围内,诸如大约300mm。在这些情况下,如在图2至图4中示出的,接通电源206(步骤304)并且在衬底50上电镀铜(步骤306)以形成铜的柱66。如本领域普通技术人员容易理解的,可以使用其它材料、溶液以及参数。一旦电镀期望材料(步骤306)并且关闭电源和搅动器(步骤308和310),在图5的步骤108中,从电镀溶液230移除衬底50。
根据图5的可选步骤110,衬底50然后浸入储液槽200内的电镀溶液230中,其可以是与(但是可以是相同或相似的构造)步骤08的电镀工艺中使用的储液槽不同的储液槽,以在柱66上电镀阻挡层68。在步骤110中储液槽200可以具有如以上描述的相对于第二实施方式的实施例的步骤110的布置和构造。根据一些实施例,当阻挡层68要为镍层时,可以在步骤110中使用基于氨基磺酸镍的镍溶液作为电镀溶液230。打开搅动器(步骤302),并且例如在衬底50处产生期望的搅拌等级为低搅拌等级,可以通过打开搅拌器220以在方向224上(平行于电镀溶液230的顶面并且在X方向中与溶液230中的电流的流动交叉)以诸如在大约240RPM至大约420RPM范围内的频率(更具体地,诸如大约300RPM)进行往复运动来实现该低搅拌等级。在搅拌器220的方向224上的往复运动的幅度可以在大约290mm至大约310mm的范围内,诸如大约300mm。用于步骤110的搅拌状态可以与步骤108中使用的搅拌状态相同,并且因此,在步骤110和108中,在衬底50处的产生搅拌等级可以是相同的。在这些情况下,如在图2至图4中示出的,接通电源206(步骤304)并且在柱66上电镀镍(步骤306)以形成镍的阻挡层68。如本领域普通技术人员容易理解的,可以使用其它材料、溶液以及参数。一旦电镀期望材料(步骤306)并且关闭电源和搅动器(步骤308和310),在图5的步骤110中,从电镀溶液230中移除衬底50。在其它的实施例中,省略步骤110并且因此,省略了阻挡层68。
根据图5的步骤112,衬底50然后浸入(步骤300)储液槽200内的电镀溶液230中,该储液槽可以是与步骤108和/或110的电镀工艺中使用的储液槽不同的储液槽(并具有不同的构造),以在阻挡层68(或者当省略阻挡层68时的柱66)上电镀焊料70。在步骤112中,储液槽200可以具有如上面描述的相对于第二实施方式的实施例的步骤112的布置和构造。用于步骤112的储液槽200的尺寸D9、D10、D11以及D12分别地小于用于步骤108和/或110的储液槽200的尺寸D9、D10、D11以及D12。根据一些实施例,当焊料70变成具有锡-银组合物时,可以使用具有的202系列添加剂(来自Mitsubishi Materials Corporation)的锡/银溶液作为电镀溶液230。打开搅动器(步骤302),并且例如在衬底50处产生期望的搅拌等级为高搅拌等级,其中,可以通过打开搅拌器220以在方向222上(在方向上垂直于电镀溶液230的顶面)以诸如在大约240RPM至大约420RPM范围内的频率(更具体地,诸如以大约300RPM)进行往复运动来实现搅拌等级。用于步骤112的搅拌器220在储液槽200中往复运动的方向224与用于步骤108和/或110的搅拌器220在储液槽200中的往复运动的方向222不同。在步骤118、110以及112中的往复运动的频率可以是相同的。搅拌器220在方向224上的往复运动的幅度可以在大约50mm至大约200mm的范围内,诸如大约150mm。在步骤118、110以及112中的往复运动的幅度可以是相同的。用于步骤112的搅拌状态与在步骤108和/或110中使用情况所导致的搅拌相比可以导致在衬底50处产生更大的搅拌。在这些情况下,如在图2至图4中示出的,接通电源206(步骤304)并且在阻挡层68和/或柱66上电镀焊料70和外壳72(步骤306)。如本领域普通技术人员容易理解的,可以使用其它材料、溶液以及参数。一旦电镀期望材料(步骤306)并且关闭电源和搅动器(步骤308和310),在图5的步骤110中,就从电镀溶液230移除衬底50。
尽管上面在不同实施方式的实施例中进行讨论,但是其它实施例预期使用诸如上述特征的组合相对于步骤108和/或110在步骤112期间在衬底50处产生的增加搅拌等级,例如,增加的往复运动的频率、提高的往复运动的幅度、组件的更接近、以及不同的往复运动的方向、或者可以影响增加搅拌等级的其他参数或因素中的两个或多个的任意组合。
通过在步骤112中增加在衬底50处所产生的搅拌等级,在步骤112期间使用的光刻胶62可以伸缩或弯曲以在光刻胶62和柱66和/或阻挡层68之间产生间隙,从而在电镀(步骤306)期间允许外壳72的形成。可以通过在步骤112中的电镀期间的驻留时间(dwell time)来实现外壳72沿着侧壁延伸的期望的第二尺寸D2。例如,小的驻留时间可以导致小的尺寸D2,并且诸如120秒的较长的驻留时间可以导致尺寸D2,其中,该尺寸D2接近尺寸D1。在诸如图5的步骤116的蚀刻晶种层60和粘合层58的随后的蚀刻步骤期间,
外壳72可以保护阻挡层68和/或柱66,以在随后的蚀刻步骤期间防止(诸如图5的蚀刻晶种层60和粘合层58的步骤116)防止电镀的焊料70的表面免于被蚀刻掉。因此,例如,在随后的回流工艺期间,在焊料70下方的表面可以保留支撑焊料70,并且焊料70在柱66的侧壁上不易发生向下塌陷。在一些实施例中,这可以允许用于包括具有焊料的柱的外部导电连接器的更高的密度布局。此外,外壳72可以保护柱66和/或阻挡层68以避免由于随后的工艺所导致的氧化。而且,外壳72可以保护介于柱66和阻挡层68之间的界面以避免在界面中可以以其他方式渗透的水分。因此,外壳72可以增加结构的稳定性。
实施例为一种方法。该方法包括在衬底上形成外部电连接结构。形成外部电连接结构包括在第一溶液中的衬底处产生第一搅拌等级的情况下,在衬底上电镀柱。该方法还包括在第二溶液中的衬底处产生第二搅拌等级的情况下,在外部电连接结构上电镀焊料。在衬底处产生的第二搅拌等级大于在衬底处产生的第一搅拌等级。电镀焊料还包括在外部电连接结构的侧壁上形成外壳。
在实施例中,形成所述外部电连接结构还包括在第三溶液中的所述衬底处的所述第一搅拌等级的情况下,所述柱上电镀阻挡层。
在实施例中,在所述阻挡层的侧壁上以及所述柱的侧壁上形成所述外壳。
在实施例中,在第一电镀系统中执行电镀所述柱,所述第一电镀系统包括第一搅拌器,电镀所述柱包括在所述第一溶液中使所述第一搅拌器进行往复运动以导致在所述衬底处产生的所述第一搅拌等级,并且在第二电镀系统中执行电镀所述焊料,所述第二电镀系统包括第二搅拌器,电镀所述焊料包括在所述第二溶液中使所述第二搅拌器进行往复运动以导致在所述衬底处产生的所述第二搅拌等级。
在实施例中,所述第一搅拌器以第一频率进行往复运动,并且所述第二搅拌器以大于所述第一频率的第二频率进行往复运动。
在实施例中,所述第一搅拌器在电镀所述柱期间,位于距离所述衬底的第一距离处,并且所述第二搅拌器在电镀所述柱期间位于距离所述衬底的第二距离处,所述第二距离等于所述第一距离。
在实施例中,所述第一搅拌器在电镀所述柱期间位于距离所述衬底的第一距离处,并且所述第二搅拌器在电镀所述柱期间位于距离所述衬底的第二距离处,所述第二距离小于所述第一距离。
在实施例中,所述第一搅拌器以第一频率进行往复运动,并且所述第二搅拌器以等于所述第一频率的第二频率进行往复运动。
在实施例中,所述第一搅拌器相对于所述衬底沿着第一方向进行往复运动,并且所述第二搅拌器相对于所述衬底沿着第二方向进行往复运动,所述第二方向不同于所述第一方向。
在实施例中,所述第一搅拌器相对于所述衬底沿着第一方向进行往复运动,并且所述第二搅拌器相对于所述衬底沿着第二方向进行往复运动,所述第二方向垂直于所述第一方向。
在实施例中,用于形成半导体器件的方法还包括回流所述焊料,在所述回流后,所述外壳保留在所述外部电连接结构的侧壁上。
在实施例中,在所述回流后,所述外壳包括金属间化合物(IMC)。
在实施例中,用于形成半导体器件的方法还包括:在所述衬底上形成凸块下金属(UBM),在所述衬底上的所述凸块下金属上电镀所述柱;以及在电镀所述焊料后,蚀刻所述凸块下金属的一部分,而所述外壳位于所述外部电连接结构的侧壁上。
在实施例中,所述蚀刻还蚀刻所述柱的一部分,所述柱的邻近所述衬底的第一宽度小于所述衬底的远离所述柱的第二宽度。其它实施例是一种方法。使用第一电镀系统在衬底上电镀柱。柱为外部电连接结构的至少一部分。第一电镀系统包括第一搅拌器,并且第一搅拌器在电镀柱期间在第一电镀溶液中以第一频率进行往复运动。使用第二电镀系统电镀在外部电连接结构上的焊料。第二电镀系统包括第二搅拌器,并且第二搅拌器在电镀焊料期间在第二电镀溶液中以第二频率进行往复运动。第二频率大于第一频率。电镀焊料还沿着外部电连接结构的侧壁形成外壳。
在实施例中,所述第一频率等于或者小于300转每分钟(RPM),并且所述第二频率等于或大于400RPM。
在实施例中,用于形成半导体器件的方法还包括:在所述衬底上形成凸块下金属(UBM),在所述衬底上的所述凸块下金属上电镀所述柱;在电镀所述柱后,蚀刻所述凸块下金属的一部分,而所述外壳位于所述外部电连接结构的侧壁上;以及在蚀刻后,回流所述焊料,所述外壳在所述回流后保留在所述外部电连接结构的侧壁上。
其它实施例是一种半导体器件。一种半导体器件包括:导电柱,导电柱位于衬底上方的导电构件的上方;可回流材料,可回流材料位于导电柱上方,其中,可回流材料还包括:第一部分,第一部分位于导电柱的第一表面上方,其中,第一表面背对着导电构件,其中,第一部分具有第一组分的第一浓度;第二部分,第二部分位于邻近于但是不完全覆盖导电柱的第二表面,其中,第二表面从第一表面朝向衬底延伸,其中,第二部分具有大于第一浓度的第一组分的第二浓度。
在实施例中,电镀所述焊料包括使用大于在电镀所述柱的所述衬底处产生的第二搅拌等级的在所述衬底处产生的第一搅拌等级,在所述衬底处生成的所述第一搅拌等级导致所述掩模伸缩。
其它实施例为一种方法。在衬底上形成凸块下金属(UBM)。在UBM上形成掩模,穿过掩模的开口暴露部分的UBM。在穿过掩模的开口中的UBM上电镀柱,并且柱为外部电连接件的一部分。在外部电连接件上电镀焊料。电镀焊料还包括使得掩模伸缩以导致介于掩模和外部电连接件的侧壁之间的间隙。沿着外部电连接件的侧壁并且在掩模和外部电连接件的侧壁之间的间隙中形成外壳。
在实施例中,所述第一组分是银。
在实施例中,所述导电柱在通过所述可回流材料覆盖的第一点处具有第一宽度和在通过所述可回流材料未覆盖的第二点处具有小于所述第一宽度的第二宽度,其中,所述第一宽度平行于所述衬底的主表面。
上述内容概括了几个实施例的特征使得本领域技术人员可更好地理解本发明的各个方面。本领域技术人员应该理解,可以很容易地使用本发明作为基础来设计或更改其他的处理和结构以用于达到与本发明所介绍实施例相同的目的和/或实现相同优点。本领域技术人员也应该意识到,这些等效结构并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。

Claims (19)

1.一种用于形成半导体器件的方法,包括:
在衬底上形成外部电连接结构,形成所述外部电连接结构包括在第一溶液中的所述衬底处产生的第一搅拌等级的情况下,在所述衬底上的掩模中电镀柱;在第二溶液中的所述衬底处产生的第二搅拌等级的情况下,在所述外部电连接结构上电镀焊料,在所述衬底处产生的所述第二搅拌等级大于在所述衬底处产生的所述第一搅拌等级;
其中,电镀所述焊料还包括使所述掩模伸缩以形成介于所述外部电连接件的侧壁和所述掩模之间的间隙,并在所述间隙中形成外壳。
2.根据权利要求1所述的用于形成半导体器件的方法,其中,形成所述外部电连接结构还包括在第三溶液中的所述衬底处的所述第一搅拌等级的情况下,所述柱上电镀阻挡层。
3.根据权利要求2所述的用于形成半导体器件的方法,其中,在所述阻挡层的侧壁上以及所述柱的侧壁上形成所述外壳。
4.根据权利要求1所述的用于形成半导体器件的方法,其中,在第一电镀系统中执行电镀所述柱,所述第一电镀系统包括第一搅拌器,电镀所述柱包括在所述第一溶液中使所述第一搅拌器进行往复运动以导致在所述衬底处产生的所述第一搅拌等级,并且在第二电镀系统中执行电镀所述焊料,所述第二电镀系统包括第二搅拌器,电镀所述焊料包括在所述第二溶液中使所述第二搅拌器进行往复运动以导致在所述衬底处产生的所述第二搅拌等级。
5.根据权利要求4所述的用于形成半导体器件的方法,其中,所述第一搅拌器以第一频率进行往复运动,并且所述第二搅拌器以大于所述第一频率的第二频率进行往复运动。
6.根据权利要求5所述的用于形成半导体器件的方法,其中,所述第一搅拌器在电镀所述柱期间,位于距离所述衬底的第一距离处,并且所述第二搅拌器在电镀所述柱期间位于距离所述衬底的第二距离处,所述第二距离等于所述第一距离。
7.根据权利要求4所述的用于形成半导体器件的方法,其中,所述第一搅拌器在电镀所述柱期间位于距离所述衬底的第一距离处,并且所述第二搅拌器在电镀所述柱期间位于距离所述衬底的第二距离处,所述第二距离小于所述第一距离。
8.根据权利要求7所述的用于形成半导体器件的方法,其中,所述第一搅拌器以第一频率进行往复运动,并且所述第二搅拌器以等于所述第一频率的第二频率进行往复运动。
9.根据权利要求7所述的用于形成半导体器件的方法,其中,所述第一搅拌器相对于所述衬底沿着第一方向进行往复运动,并且所述第二搅拌器相对于所述衬底沿着第二方向进行往复运动,所述第二方向不同于所述第一方向。
10.根据权利要求7所述的用于形成半导体器件的方法,其中,所述第一搅拌器相对于所述衬底沿着第一方向进行往复运动,并且所述第二搅拌器相对于所述衬底沿着第二方向进行往复运动,所述第二方向垂直于所述第一方向。
11.根据权利要求1所述的用于形成半导体器件的方法,还包括回流所述焊料,在所述回流后,所述外壳保留在所述外部电连接结构的侧壁上。
12.根据权利要求11所述的用于形成半导体器件的方法,其中,在所述回流后,所述外壳包括金属间化合物(IMC)。
13.根据权利要求1所述的用于形成半导体器件的方法,还包括:
在所述衬底上形成凸块下金属(UBM),在所述衬底上的所述凸块下金属上电镀所述柱;以及
在电镀所述焊料后,蚀刻所述凸块下金属的一部分,而所述外壳位于所述外部电连接结构的侧壁上。
14.根据权利要求13所述的用于形成半导体器件的方法,其中,所述蚀刻还蚀刻所述柱的一部分,所述柱的邻近所述衬底的第一宽度小于所述衬底的远离所述柱的第二宽度。
15.一种用于形成半导体器件的方法,包括:
使用第一电镀系统在衬底上的掩模中电镀柱,所述柱为外部电连接结构的至少一部分,所述第一电镀系统包括第一搅拌器,所述第一搅拌器在电镀所述柱期间在第一电镀溶液中以第一频率进行往复运动;
使用第二电镀系统在所述外部电连接结构上电镀焊料,所述第二电镀系统包括第二搅拌器,所述第二搅拌器在电镀所述焊料期间在第二电镀溶液中以第二频率进行往复运动,所述第二频率大于所述第一频率,电镀所述焊料还包括沿着所述外部电连接结构的侧壁形成外壳;
其中,电镀所述焊料还包括使所述掩模伸缩以形成介于所述外部电连接件的侧壁和所述掩模之间的间隙,并在所述间隙中形成外壳。
16.根据权利要求15所述的用于形成半导体器件的方法,其中,所述第一频率等于或者小于300转每分钟(RPM),并且所述第二频率等于或大于400转每分钟(RPM)。
17.根据权利要求15所述的用于形成半导体器件的方法,还包括:
在所述衬底上形成凸块下金属(UBM),在所述衬底上的所述凸块下金属上电镀所述柱;
在电镀所述柱后,蚀刻所述凸块下金属的一部分,而所述外壳位于所述外部电连接结构的侧壁上;以及
在蚀刻后,回流所述焊料,所述外壳在所述回流后保留在所述外部电连接结构的侧壁上。
18.一种用于形成半导体器件的方法,包括:
在衬底上形成凸块下金属(UBM);
在所述凸块下金属上形成掩模,穿过所述掩模的开口暴露所述凸块下金属的一部分;
在穿过所述掩模的所述开口中的所述凸块下金属上电镀柱,所述柱为外部电连接件的一部分;以及
在所述外部电连接件上电镀焊料,电镀所述焊料还包括使所述掩模伸缩以导致介于所述外部电连接件的侧壁和所述掩模之间的间隙,沿着所述外部电连接件的侧壁并且在所述外部电连接件的侧壁和所述掩模之间的间隙中形成外壳。
19.根据权利要求18所述的用于形成半导体器件的方法,其中,电镀所述焊料包括使用大于在电镀所述柱的所述衬底处产生的第二搅拌等级的在所述衬底处产生的第一搅拌等级,在所述衬底处生成的所述第一搅拌等级导致所述掩模伸缩。
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10062626B2 (en) * 2016-07-26 2018-08-28 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US10403591B2 (en) * 2017-10-31 2019-09-03 Xilinx, Inc. Chip package assembly with enhanced interconnects and method for fabricating the same
JP7430481B2 (ja) * 2018-05-31 2024-02-13 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
CN109729639B (zh) * 2018-12-24 2020-11-20 奥特斯科技(重庆)有限公司 在无芯基板上包括柱体的部件承载件
CN113053866B (zh) * 2020-03-30 2024-11-15 台湾积体电路制造股份有限公司 半导体器件及其制造方法
US11901307B2 (en) 2020-03-30 2024-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including electromagnetic interference (EMI) shielding and method of manufacture
CN114855244A (zh) * 2021-02-04 2022-08-05 盛美半导体设备(上海)股份有限公司 电镀装置及电镀方法
TWI842490B (zh) * 2023-04-24 2024-05-11 友達光電股份有限公司 發光元件基板及顯示裝置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1391261A (zh) * 2001-06-12 2003-01-15 卓联科技有限公司 下层块金属的阻挡层盖
CN1873939A (zh) * 2002-02-07 2006-12-06 日本电气株式会社 半导体器件的制造方法
KR20090082691A (ko) * 2008-01-28 2009-07-31 완-링 유 반도체 디바이스용 금속 범프 및 실을 형성하는 방법
CN101950728A (zh) * 2009-07-08 2011-01-19 台湾积体电路制造股份有限公司 金属柱凸块结构及其形成方法
CN102270610A (zh) * 2010-06-02 2011-12-07 台湾积体电路制造股份有限公司 集成电路装置及封装组件

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE214719C (zh)
DD214719A1 (de) 1983-04-08 1984-10-17 Seghers A Mikroelektronik Veb Verfahren zur herstellung bondfaehiger schichten fuer halbleiterbauelemente
US7547623B2 (en) * 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
US7393439B2 (en) 2003-06-06 2008-07-01 Semitool, Inc. Integrated microfeature workpiece processing tools with registration systems for paddle reactors
TWI254995B (en) * 2004-01-30 2006-05-11 Phoenix Prec Technology Corp Presolder structure formed on semiconductor package substrate and method for fabricating the same
TWI267155B (en) 2005-08-23 2006-11-21 Advanced Semiconductor Eng Bumping process and structure thereof
US20080041727A1 (en) 2006-08-18 2008-02-21 Semitool, Inc. Method and system for depositing alloy composition
US20080116077A1 (en) * 2006-11-21 2008-05-22 M/A-Com, Inc. System and method for solder bump plating
US8177944B2 (en) 2007-12-04 2012-05-15 Ebara Corporation Plating apparatus and plating method
US8492891B2 (en) * 2010-04-22 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with electrolytic metal sidewall protection
US8232193B2 (en) 2010-07-08 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming Cu pillar capped by barrier layer
US8405199B2 (en) * 2010-07-08 2013-03-26 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pillar for semiconductor substrate and method of manufacture
JP5658582B2 (ja) 2011-01-31 2015-01-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US9472521B2 (en) 2012-05-30 2016-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Scheme for connector site spacing and resulting structures
US9484291B1 (en) * 2013-05-28 2016-11-01 Amkor Technology Inc. Robust pillar structure for semicondcutor device contacts
KR101563911B1 (ko) * 2013-10-24 2015-10-28 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US9735123B2 (en) 2014-03-13 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device structure and manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1391261A (zh) * 2001-06-12 2003-01-15 卓联科技有限公司 下层块金属的阻挡层盖
CN1873939A (zh) * 2002-02-07 2006-12-06 日本电气株式会社 半导体器件的制造方法
KR20090082691A (ko) * 2008-01-28 2009-07-31 완-링 유 반도체 디바이스용 금속 범프 및 실을 형성하는 방법
CN101950728A (zh) * 2009-07-08 2011-01-19 台湾积体电路制造股份有限公司 金属柱凸块结构及其形成方法
CN102270610A (zh) * 2010-06-02 2011-12-07 台湾积体电路制造股份有限公司 集成电路装置及封装组件

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