CN106997878A - The silicon capacitor and its manufacture method of double-decker - Google Patents
The silicon capacitor and its manufacture method of double-decker Download PDFInfo
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- CN106997878A CN106997878A CN201710208021.6A CN201710208021A CN106997878A CN 106997878 A CN106997878 A CN 106997878A CN 201710208021 A CN201710208021 A CN 201710208021A CN 106997878 A CN106997878 A CN 106997878A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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Abstract
The present invention relates to a kind of silicon capacitor of double-decker and its manufacture method, including P type substrate, it is characterized in that：Multiple silicon grooves are formed in the P type substrate upper surface, in the surface doping N-type impurity knot formation N-type conductive layer of the upper surface of P type substrate and silicon groove, first layer dielectric layer, first layer polycrystalline, second layer dielectric layer and second layer polycrystalline are set gradually on N-type conductive layer, insulating medium layer is set on second layer polycrystalline, first contact hole, the second contact hole and the 3rd contact hole are set on insulating medium layer, the bottom of first contact hole and N-type conductive layers make contact, the bottom of second contact hole is contacted with first layer polycrystalline, and the bottom of the 3rd contact hole is contacted with second layer polycrystalline；The first external electrode metal is set at first contact hole and the 3rd contact hole, the second external electrode metal is set at the 3rd contact hole.The present invention forms two-layer nano silicon groove electric capacity using medium and overlapping be deposited in silicon groove of doped polycrystalline in situ, and manufacturing process is simple.
Description
Technical field
The present invention relates to a kind of silicon capacitor of double-decker and its manufacture method, especially a kind of raising silicon capacitor
The manufacture method of capacitance, belongs to technical field of semiconductors.
Background technology
Silicon capacitor is to utilize semiconductor silicon material and CMOS fabrication technology, in silicon channel capacitor made from silicon substrate.Silicon
Capacitor is because of its small volume, and stability is good and other plurality of advantages are just increasingly taken seriously.Silicon capacitor is using extensive
CMOS ic manufacturing technologies integrated millions of small nanometer silicon groove electric capacity on a silicon substrate.Compared to traditional electrolysis
Capacitor, multilayer ceramic capacitor, thin film capacitor, tantalum capacitor, manufacturing technology content highest.
Current silicon capacitor has application in national defence, communication, medical treatment, smart card, automobile and petroleum exploration field.Due to
Silicon capacitor working frequency is up to more than 60GHz He semiconductor product high reliability, and silicon capacitor has been supplied in radar and logical
Letter field, while silicon capacitor heatproof is up to 250 DEG C, is particularly suitable for using in the presence of a harsh environment, such as under automobile engine cover and oil
The inferior extreme environment of deep-well is explored, silicon capacitor volume is extra small in addition and thickness ultrathin, vertical with IC to encapsulate three-dimensional, subtracts
The small area of printed circuit board.But silicon electric capacity also Challenge, current silicon capacitor integrated millions of on a silicon substrate
Small nanometer silicon groove electric capacity, monolayer silicon groove capacitance is small, and capacitance density is not generally high, and which has limited answering for silicon capacitor
With field so that silicon capacitor can only be in special dimension application.
The content of the invention
The purpose of the present invention be overcome the deficiencies in the prior art there is provided a kind of silicon capacitor of double-decker and its
Manufacture method, using nanometer double layer capacity, improves capacitance density, increases capacitance.
The technical scheme provided according to the present invention, the silicon capacitor of the double-decker, including P type substrate, it is characterized in that：
Multiple silicon grooves are formed in the P type substrate upper surface, surface direction extends silicon groove downwards from the upper table of P type substrate；In the P
The upper surface of type substrate and the surface doping N-type impurity knot formation N-type conductive layer of silicon groove, are used as the inside electricity of the first layer capacitance
Pole, set gradually on the N-type conductive layer of P type substrate and silicon groove first layer dielectric layer, first layer polycrystalline, second layer dielectric layer and
Second layer polycrystalline, first layer polycrystalline is used as the first layer capacitance and the public internal electrode of the second layer capacitance, second layer polycrystalline conduct
The internal electrode of second layer capacitance；Insulating medium layer is set on the second layer polycrystalline, and insulating medium layer covers lower section
First layer dielectric layer, first layer polycrystalline, second layer dielectric layer and second layer polycrystalline；First is set to connect on the insulating medium layer
Contact hole, the second contact hole and the 3rd contact hole, bottom and the N-type conductive layers make contact, the bottom of the second contact hole of the first contact hole
Contacted with first layer polycrystalline, the bottom of the 3rd contact hole is contacted with second layer polycrystalline；Contacted in first contact hole and the 3rd
The first external electrode metal is set at hole, the second external electrode metal is set at the 3rd contact hole, and the first external electrode metal and N-type are led
Electric layer and the contact of second layer polycrystalline, the second external electrode metal and the contact of first layer polycrystalline, the first external electrode metal and the second dispatch from foreign news agency
It is isolated between the metal of pole by insulating medium layer.
Further, the thickness of the first layer dielectric layer and second layer dielectric layer is 20nm ~ 100nm.
Further, the first layer polycrystalline thickness be 500nm ~ 600nm, second layer polycrystalline thickness be 700nm ~
800nm。
The manufacture method of the silicon capacitor of the double-decker, it is characterized in that, comprise the following steps：
（1）P type substrate is provided, multiple silicon grooves are etched in the upper surface of P type substrate, silicon groove from the upper table of P type substrate downwards
Surface direction extends；
（2）Doping and the knot of N-type impurity are carried out in the upper surface of P type substrate and silicon groove, N-type conductive layer is obtained；
（3）First layer dielectric layer, first layer polycrystalline, the second layer are grown successively in the N-type conductive layer surface of P type substrate and silicon groove to be situated between
Matter layer and second layer polycrystalline；
（4）Second layer polycrystalline, second layer dielectric layer, first layer polycrystalline are sequentially etched, be connected with second layer dielectric layer is obtained
A kind of connecting hole and second of connecting hole being connected with P type substrate；
（5）Deposit one layer of insulating medium layer；
（6）Insulating medium layer is performed etching to form the first contact hole, the second contact hole and the 3rd contact hole, the first contact hole position
In second of connection hole, the second contact hole is located at the first connection hole；The bottom of first contact hole and N-type conductive layer
Contact, the bottom of the second contact hole is contacted with first layer polycrystalline, and the bottom of the 3rd contact hole is contacted with second layer polycrystalline；
（7）In the enterprising row metal sputtering of insulating dielectric layer layer, metal level is obtained；Photoetching is carried out to metal level, retains first and contacts
The first external electrode metal and the second external electrode metal at hole, the second contact hole and the 3rd contact hole；The first external electrode gold
Category and N-type conductive layer and second layer polycrystalline are contacted, the second external electrode metal and the contact of first layer polycrystalline, the first external electrode metal and
It is isolated between the second external electrode metal by insulating medium layer.
Further, the step（1）In first P type substrate upper surface deposit 600nm SiO2Mask, selectivity
Ground is sheltered and etch mask, and multiple silicon grooves are gone out in the upper surface photoetching of P type substrate and plasma etching, and silicon groove depth is 30 ~
100um, silicon well width is 2-3um；Float the SiO removed in P type substrate entirely using BOE again2Mask.
Further, the step（2）In pass through POCl3Doping and the knot of N-type impurity are carried out, N-type conductive layer is obtained；
Thickness 50nm ~ 80nm SiO can be produced during being doped with knot2, float the SiO for removing and being formed entirely using BOE2。
Further, the step（3）In, the thickness of first layer dielectric layer and second layer dielectric layer is 20nm ~ 100nm；
The first layer polycrystalline thickness is 500nm ~ 600nm, and second layer polycrystalline thickness is 700nm ~ 800nm.
Further, the step（4）Detailed process be：
A, second layer polycrystalline is performed etching, until etching into second layer dielectric layer；
B, continuation etching of second layer dielectric layer, obtain the first connecting hole；
C, first layer polycrystalline is performed etching, until etching into P type substrate upper surface, obtain second of connecting hole.
Further, the thickness of the insulating medium layer is 600nm.
Further, a width of 1um ~ 2um in aperture of first contact hole, the second contact hole and the 3rd contact hole.
The present invention has advantages below：The present invention goes out depth using ripe semiconductor fabrication, deep trouth plasma etching
Silicon groove, medium and overlapping be deposited in silicon groove of doped polycrystalline in situ form million two-layer nano silicon groove electric capacity, million bilayers
Nanometer silicon groove electric capacity is integrated into a silicon capacitor, and manufacturing process is simple.
Brief description of the drawings
Fig. 1~Fig. 4 is the manufacturing process flow profile of the silicon capacitor of double-decker of the present invention.Wherein：
Fig. 1 is the sectional view after the formation silicon groove in substrate.
Fig. 2 is to obtain the alternate double-deck sectional view of the right later layer polycrystalline of one layer of medium.
Fig. 3 is contact hole profile.
Fig. 4 is the profile of obtained silicon capacitor.
Description of reference numerals；1-P types substrate, 2- silicon groove, 3- first layers dielectric layer, 4- first layers polycrystalline, the 5- second layers are situated between
Matter layer, 6- second layers polycrystalline, 7- insulating medium layers, the contact holes of 8- first, 9- the first external electrodes metal, the contact holes of 10- second,
The contact holes of 11- the 3rd, 12- the second external electrodes metal, 13- the first connecting hole, second of connecting hole of 14-.
Embodiment
With reference to specific accompanying drawing, the invention will be further described.
As shown in figure 4, the silicon capacitor of double-decker of the present invention includes P type substrate 1, in the upper surface shape of P type substrate 1
Into multiple silicon grooves 2, from the upper table of P type substrate 1, surface direction extends silicon groove 2 downwards；In the upper surface of the P type substrate 1 and
The surface doping N-type impurity knot formation N-type conductive layer of silicon groove 2, as the internal electrode of the first layer capacitance, in the He of P type substrate 1
First layer dielectric layer 3, first layer polycrystalline 4, second layer dielectric layer 5 and second layer polycrystalline are set gradually on the N-type conductive layer of silicon groove 2
6, first layer polycrystalline 4 is used as second layer electricity as the first layer capacitance and the public internal electrode of the second layer capacitance, second layer polycrystalline 6
The internal electrode of appearance；The first layer dielectric layer 3 and second layer dielectric layer 5 pass through thermal oxide growth SiO2, LPCVD deposit SiO2、
LPCVD deposits SiN or the mode of ALD deposition medium is obtained, and the thickness of first layer dielectric layer 3 and second layer dielectric layer 5 is
20nm~100nm；The first layer polycrystalline 4 and second layer polycrystalline 6 are obtained by LPCVD deposits, and the thickness of first layer polycrystalline 4 is
500nm ~ 600nm, the thickness of second layer polycrystalline 6 is 700nm ~ 800nm；Insulating medium layer is set on the second layer polycrystalline 6
7, insulating medium layer 7 covers first layer dielectric layer 3, first layer polycrystalline 4, second layer dielectric layer 5 and the second layer polycrystalline of lower section
6；First contact hole 8, the second contact hole 10 and the 3rd contact hole 11 are set on the insulating medium layer 7, the first contact hole 8
Bottom and N-type conductive layers make contact, the bottom of the second contact hole 10 are contacted with first layer polycrystalline 4, the bottom of the 3rd contact hole 11 and
Second layer polycrystalline 6 is contacted；The first external electrode metal 9 is set at the contact hole 11 of the first contact hole 8 and the 3rd, connect the 3rd
The second external electrode metal 12 is set at contact hole 11, and the first external electrode metal 9 and N-type conductive layer and second layer polycrystalline 6 are contacted, second
External electrode metal 12 and first layer polycrystalline 4 are contacted, by dielectric between the first external electrode metal 9 and the second external electrode metal 12
Layer 7 is isolated.
Embodiment one：A kind of manufacture method of the silicon capacitor of double-decker, comprises the following steps：
（1）As shown in Figure 1 there is provided P type substrate 1,600nm SiO is deposited in the upper surface of P type substrate 12Mask, optionally
Shelter and etch mask, multiple silicon grooves 2 are gone out in the upper surface photoetching of P type substrate 1 and plasma etching, silicon groove 2 is from P type substrate 1
Upper table downwards surface direction extend, the depth of silicon groove 2 be 30um, the width of silicon groove 2 be 2um；Using BOE（Boffered
Oxide Etch）Full drift removes the SiO in P type substrate 12Mask；
（2）Pass through POCl on the surface of the upper surface of P type substrate 1 and silicon groove 23Doping and the knot of N-type impurity are carried out, N is obtained
Type conductive layer；Thickness 50nm SiO can be produced during being doped with knot2, floated entirely using BOE and remove what is formed
SiO2；
（3）As shown in Fig. 2 the N-type conductive layer surface in P type substrate 1 and silicon groove 2 grows first layer dielectric layer 3, first layer successively
Polycrystalline 4, second layer dielectric layer 5 and second layer polycrystalline 6；The first layer dielectric layer 3 and second layer dielectric layer 5 are given birth to by thermal oxide
Long SiO2, LPCVD deposit SiO2, LPCVD deposit SiN or ALD deposition medium formed, thickness is 20nm；The first layer polycrystalline
4 and second layer polycrystalline 6 can be obtained by LPCVD deposits, the thickness of first layer polycrystalline 4 is 500nm, the thickness of second layer polycrystalline 6
Spend for 700nm；
（4）Photoresist is coated on second layer polycrystalline 6, passes through Cl2Plasma is carried out to second layer polycrystalline 6 with HBr mixed gas
Etching, until retaining photoresist after etching into second layer dielectric layer 5, etching；
（5）Pass through CF4And CHF3Photoresist is removed after mixed gas plasma etching second layer dielectric layer 5, etching, first is obtained
Plant connecting hole 13；
（6）Again photoresist, photoetching and etching of first layer polycrystalline 4 are coated, passes through Cl2It is straight with HBr mixed gas plasma etchings
To the upper surface of P type substrate 1 is etched into, second of connecting hole 14 is obtained, removal photoresist has been etched；
（7）One layer of insulating medium layer 7 is deposited, thickness is 600nm；
（8）Photoetching is carried out to insulating medium layer 7 and etching forms the first contact hole 8, the second contact hole 10 and the 3rd contact hole 11,
The wide 1um in aperture；First contact hole 8 is located at second of connecting hole 14, and the second contact hole 10 is located at the first connecting hole 13
Place；The bottom of first contact hole 8 and N-type conductive layers make contact, the bottom of the second contact hole 10 are contacted with first layer polycrystalline 4,
The bottom of 3rd contact hole 11 is contacted with second layer polycrystalline 6；
（9）In the enterprising row metal sputtering of insulating dielectric layer layer 7, thickness is 3um, obtains metal level；Photoetching is carried out to metal level, protected
Stay the first external electrode metal 9 and the second external electrode metal at the first contact hole 8, the second contact hole 10 and the 3rd contact hole 11
12, photoresist is removed after etching.
Embodiment two：A kind of manufacture method of the silicon capacitor of double-decker, comprises the following steps：
（1）As shown in Figure 1 there is provided P type substrate 1,600nm SiO is deposited in the upper surface of P type substrate 12Mask, optionally
Shelter and etch mask, multiple silicon grooves 2 are gone out in the upper surface photoetching of P type substrate 1 and plasma etching, silicon groove 2 is from P type substrate 1
Upper table downwards surface direction extend, the depth of silicon groove 2 be 100um, the width of silicon groove 2 be 3um；Using BOE（Boffered
Oxide Etch）Full drift removes the SiO in P type substrate 12Mask；
（2）Pass through POCl on the surface of the upper surface of P type substrate 1 and silicon groove 23Doping and the knot of N-type impurity are carried out, N is obtained
Type conductive layer；Thickness 80nm SiO can be produced during being doped with knot2, floated entirely using BOE and remove what is formed
SiO2；
（3）As shown in Fig. 2 the N-type conductive layer surface in P type substrate 1 and silicon groove 2 grows first layer dielectric layer 3, first layer successively
Polycrystalline 4, second layer dielectric layer 5 and second layer polycrystalline 6；The first layer dielectric layer 3 and second layer dielectric layer 5 are given birth to by thermal oxide
Long SiO2, LPCVD deposit SiO2, LPCVD deposit SiN or ALD deposition medium formed, thickness is 100nm；The first layer is more
Crystalline substance 4 and second layer polycrystalline 6 can be obtained by LPCVD deposits, and the thickness of first layer polycrystalline 4 is 600nm, second layer polycrystalline 6
Thickness is 800nm；
（4）Photoresist is coated on second layer polycrystalline 6, passes through Cl2Plasma is carried out to second layer polycrystalline 6 with HBr mixed gas
Etching, until retaining photoresist after etching into second layer dielectric layer 5, etching；
（5）Pass through CF4And CHF3Photoresist is removed after mixed gas plasma etching second layer dielectric layer 5, etching, first is obtained
Plant connecting hole 13；
（6）Again photoresist, photoetching and etching of first layer polycrystalline 4 are coated, passes through Cl2It is straight with HBr mixed gas plasma etchings
To the upper surface of P type substrate 1 is etched into, second of connecting hole 14 is obtained, removal photoresist has been etched；
（7）One layer of insulating medium layer 7 is deposited, thickness is 600nm；
（8）Photoetching is carried out to insulating medium layer 7 and etching forms the first contact hole 8, the second contact hole 10 and the 3rd contact hole 11,
The wide 2um in aperture；First contact hole 8 is located at second of connecting hole 14, and the second contact hole 10 is located at the first connecting hole 13
Place；The bottom of first contact hole 8 and N-type conductive layers make contact, the bottom of the second contact hole 10 are contacted with first layer polycrystalline 4,
The bottom of 3rd contact hole 11 is contacted with second layer polycrystalline 6；
（9）In the enterprising row metal sputtering of insulating dielectric layer layer 7, thickness is 3um, obtains metal level；Photoetching is carried out to metal level, protected
Stay the first external electrode metal 9 and the second external electrode metal at the first contact hole 8, the second contact hole 10 and the 3rd contact hole 11
12, photoresist is removed after etching.
Embodiment three：A kind of manufacture method of the silicon capacitor of double-decker, comprises the following steps：
（1）As shown in Figure 1 there is provided P type substrate 1,600nm SiO is deposited in the upper surface of P type substrate 12Mask, optionally
Shelter and etch mask, multiple silicon grooves 2 are gone out in the upper surface photoetching of P type substrate 1 and plasma etching, silicon groove 2 is from P type substrate 1
Upper table downwards surface direction extend, the depth of silicon groove 2 be 50um, the width of silicon groove 2 be 2.5um；Using BOE（Boffered
Oxide Etch）Full drift removes the SiO in P type substrate 12Mask；
（2）Pass through POCl on the surface of the upper surface of P type substrate 1 and silicon groove 23Doping and the knot of N-type impurity are carried out, N is obtained
Type conductive layer；Thickness 60nm SiO can be produced during being doped with knot2, floated entirely using BOE and remove what is formed
SiO2；
（3）As shown in Fig. 2 the N-type conductive layer surface in P type substrate 1 and silicon groove 2 grows first layer dielectric layer 3, first layer successively
Polycrystalline 4, second layer dielectric layer 5 and second layer polycrystalline 6；The first layer dielectric layer 3 and second layer dielectric layer 5 are given birth to by thermal oxide
Long SiO2, LPCVD deposit SiO2, LPCVD deposit SiN or ALD deposition medium formed, thickness is 50nm；The first layer polycrystalline
4 and second layer polycrystalline 6 can be obtained by LPCVD deposits, the thickness of first layer polycrystalline 4 is 550nm, the thickness of second layer polycrystalline 6
Spend for 750nm；
（4）Photoresist is coated on second layer polycrystalline 6, passes through Cl2Plasma is carried out to second layer polycrystalline 6 with HBr mixed gas
Etching, until retaining photoresist after etching into second layer dielectric layer 5, etching；
（5）Pass through CF4And CHF3Photoresist is removed after mixed gas plasma etching second layer dielectric layer 5, etching, first is obtained
Plant connecting hole 13；
（6）Again photoresist, photoetching and etching of first layer polycrystalline 4 are coated, passes through Cl2It is straight with HBr mixed gas plasma etchings
To the upper surface of P type substrate 1 is etched into, second of connecting hole 14 is obtained, removal photoresist has been etched；
（7）One layer of insulating medium layer 7 is deposited, thickness is 600nm；
（8）Photoetching is carried out to insulating medium layer 7 and etching forms the first contact hole 8, the second contact hole 10 and the 3rd contact hole 11,
The wide 1.um in aperture；First contact hole 8 is located at second of connecting hole 14, and the second contact hole 10 is located at the first connecting hole 13
Place；The bottom of first contact hole 8 and N-type conductive layers make contact, the bottom of the second contact hole 10 are contacted with first layer polycrystalline 4,
The bottom of 3rd contact hole 11 is contacted with second layer polycrystalline 6；
（9）In the enterprising row metal sputtering of insulating dielectric layer layer 7, thickness is 3um, obtains metal level；Photoetching is carried out to metal level, protected
Stay the first external electrode metal 9 and the second external electrode metal at the first contact hole 8, the second contact hole 10 and the 3rd contact hole 11
12, photoresist is removed after etching.
Silicon capacitor of the present invention has small size high capacitance, long lifespan, highly reliable, heatproof high, can be applied to vapour
The stabilities of a system such as car, Aero-Space, medical treatment, electronic product require to use under high and adverse circumstances.
As long as internal multi-layered electrode Twi-lithography of the invention and etching, reduce manufacturing cost.Additionally, due to can manufacture
More than two layers of multi-layered electrode, capacitance is increased.This product utilizes ripe semiconductor technology, high-precision, highly reliable, body
The small, long lifespan of product, heatproof are high, can be widely used in Aero-Space, exploration, medical treatment and general electronic products field.
Claims (10)
1. a kind of silicon capacitor of double-decker, including P type substrate（1）, it is characterized in that：In the P type substrate（1）Upper surface shape
Into multiple silicon grooves（2）, silicon groove（2）From P type substrate（1）Upper table downwards surface direction extend；In the P type substrate（1）'s
Upper surface and silicon groove（2）Surface doping N-type impurity knot formation N-type conductive layer, as the internal electrode of the first layer capacitance,
P type substrate（1）With silicon groove（2）N-type conductive layer on set gradually first layer dielectric layer（3）, first layer polycrystalline（4）, the second layer
Dielectric layer（5）With second layer polycrystalline（6）, first layer polycrystalline（4）It is used as the first layer capacitance and the public internal electricity of the second layer capacitance
Pole, second layer polycrystalline（6）It is used as the internal electrode of the second layer capacitance；In the second layer polycrystalline（6）Upper setting insulating medium layer
（7）, insulating medium layer（7）Cover the first layer dielectric layer of lower section（3）, first layer polycrystalline（4）, second layer dielectric layer（5）With
Second layer polycrystalline（6）；In the insulating medium layer（7）The first contact hole of upper setting（8）, the second contact hole（10）With the 3rd contact
Hole（11）, the first contact hole（8）Bottom and N-type conductive layers make contact, the second contact hole（10）Bottom and first layer polycrystalline（4）
Contact, the 3rd contact hole（11）Bottom and second layer polycrystalline（6）Contact；In first contact hole（8）With the 3rd contact hole
（11）Place sets the first external electrode metal（9）, in the 3rd contact hole（11）Place sets the second external electrode metal（12）, the first dispatch from foreign news agency
Pole metal（9）With N-type conductive layer and second layer polycrystalline（6）Contact, the second external electrode metal（12）With first layer polycrystalline（4）Connect
Touch, the first external electrode metal（9）With the second external electrode metal（12）Between by insulating medium layer（7）It is isolated.
2. the silicon capacitor of double-decker as claimed in claim 1, it is characterized in that：The first layer dielectric layer（3）With second
Layer dielectric layer（5）Thickness be 20nm ~ 100nm.
3. the silicon capacitor of double-decker as claimed in claim 1, it is characterized in that：The first layer polycrystalline（4）Thickness be
500nm ~ 600nm, second layer polycrystalline（6）Thickness be 700nm ~ 800nm.
4. a kind of manufacture method of the silicon capacitor of double-decker, it is characterized in that, comprise the following steps：
（1）P type substrate is provided（1）, in P type substrate（1）Upper surface etch multiple silicon grooves（2）, silicon groove（2）From P type substrate
（1）Upper table downwards surface direction extend；
（2）In P type substrate（1）Upper surface and silicon groove（2）Doping and the knot of N-type impurity are carried out, N-type conductive layer is obtained；
（3）In P type substrate（1）With silicon groove（2）N-type conductive layer surface grow first layer dielectric layer successively（3）, first layer polycrystalline
（4）, second layer dielectric layer（5）With second layer polycrystalline（6）；
（4）It is sequentially etched second layer polycrystalline（6）, second layer dielectric layer（5）, first layer polycrystalline（4）, obtain and second layer dielectric layer
（5）The first connecting hole of connection（13）With with P type substrate（1）Second of connecting hole of connection（14）；
（5）Deposit one layer of insulating medium layer（7）；
（6）To insulating medium layer（7）Perform etching to form the first contact hole（8）, the second contact hole（10）With the 3rd contact hole
（11）, the first contact hole（8）Positioned at second of connecting hole（14）Place, the second contact hole（10）Positioned at the first connecting hole（13）
Place；First contact hole（8）Bottom and N-type conductive layers make contact, the second contact hole（10）Bottom and first layer polycrystalline（4）
Contact, the 3rd contact hole（11）Bottom and second layer polycrystalline（6）Contact；
（7）In insulating dielectric layer layer（7）Enterprising row metal sputtering, obtains metal level；Photoetching is carried out to metal level, retains first and connects
Contact hole（8）, the second contact hole（10）With the 3rd contact hole（11）The first external electrode metal at place（9）With the second external electrode metal
（12）；The first external electrode metal（9）With N-type conductive layer and second layer polycrystalline（6）Contact, the second external electrode metal（12）With
First layer polycrystalline（4）Contact, the first external electrode metal（9）With the second external electrode metal（12）Between by insulating medium layer（7）Phase
Isolation.
5. the manufacture method of the silicon capacitor of double-decker as claimed in claim 4, it is characterized in that：The step（1）Middle head
First in P type substrate（1）Upper surface deposit 600nm SiO2Mask, is optionally sheltered and etch mask, in P type substrate（1）
Upper surface photoetching and plasma etching go out multiple silicon grooves（2）, silicon groove（2）Depth is 30 ~ 100um, silicon groove（2）Width is 2-
3um；Removal P type substrate is floated using BOE entirely again（1）On SiO2Mask.
6. the manufacture method of the silicon capacitor of double-decker as claimed in claim 4, it is characterized in that：The step（2）In lead to
Cross POCl3Doping and the knot of N-type impurity are carried out, N-type conductive layer is obtained；Thickness can be produced during being doped with knot
Spend 50nm ~ 80nm SiO2, float the SiO for removing and being formed entirely using BOE2。
7. the manufacture method of the silicon capacitor of double-decker as claimed in claim 4, it is characterized in that：The step（3）In, the
One layer of dielectric layer（3）With second layer dielectric layer（5）Thickness be 20nm ~ 100nm；The first layer polycrystalline（4）Thickness be
500nm ~ 600nm, second layer polycrystalline（6）Thickness be 700nm ~ 800nm.
8. the manufacture method of the silicon capacitor of double-decker as claimed in claim 4, it is characterized in that：The step（4）Tool
Body process is：
A, to second layer polycrystalline（6）Perform etching, until etching into second layer dielectric layer（5）；
B, continuation etching of second layer dielectric layer（5）, obtain the first connecting hole（13）；
C, to first layer polycrystalline（4）Perform etching, until etching into P type substrate（1）Upper surface, obtains second of connecting hole
（14）.
9. the manufacture method of the silicon capacitor of double-decker as claimed in claim 4, it is characterized in that：The insulating medium layer
（7）Thickness be 600nm.
10. the manufacture method of the silicon capacitor of double-decker as claimed in claim 4, it is characterized in that：First contact hole
（8）, the second contact hole（10）With the 3rd contact hole（11）The a width of 1um ~ 2um in aperture.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710208021.6A CN106997878A (en) | 2017-03-31 | 2017-03-31 | The silicon capacitor and its manufacture method of double-decker |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710208021.6A CN106997878A (en) | 2017-03-31 | 2017-03-31 | The silicon capacitor and its manufacture method of double-decker |
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| CN106997878A true CN106997878A (en) | 2017-08-01 |
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| CN201710208021.6A Pending CN106997878A (en) | 2017-03-31 | 2017-03-31 | The silicon capacitor and its manufacture method of double-decker |
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