CN106960141A - Coding, coding/decoding method and the device of virtual machine instructions, virtual machine protection system - Google Patents
Coding, coding/decoding method and the device of virtual machine instructions, virtual machine protection system Download PDFInfo
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- G06F21/10—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM]
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- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
- G06F21/53—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow by executing in a restricted environment, e.g. sandbox or secure virtual machine
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Abstract
The invention discloses a kind of coding of virtual machine instructions, coding/decoding method and device, virtual machine protection system.Wherein, the coding method includes：When treating compiler and being compiled, for the virtual machine instructions of the program to be compiled, the command encoding formats of the virtual machine instructions are changed at random；The rear end output order of compiler is generated according to random amended command encoding formats.
Description
Technical field
The present invention relates to software security field, in particular to a kind of coding of virtual machine instructions, coding/decoding method and
Device, virtual machine protection system.
Background technology
The coded format of current its instruction of most of dummy machine systems is all fixed, and the safety issue that it brings is also non-
Chang Mingxian, first fixed instruction encoding bring great convenience to reverse reduction virtual machine interpreter, secondly once
The reverse instruction set restored in a Virtual Machine bytecodes file just goes for all Virtual Machine bytecodes files.
Regarding to the issue above, current virtual machine instructions coding strengthened scheme typically has：
(1) different byte code files command encoding formats are different, and this kind of mode determines it at the time of each generation instruction
Command encoding formats, in same byte code files generating process, all the time using one and same coding mode, and it is different
The instruction generating process of file uses different coded systems.(2) coded format linear transformation, this kind of mode it is virtual
Machine bytecode is during generation, to ensure that interpreter can be correctly decoded instruction, usually using linear transformation mode,
The coded format of namely present instruction is the linear transformation of the coded format of a upper instruction.Virtual machine rendering engine is held
When row arrives arbitrary instruction, according to the position of present instruction, the coded format of present instruction is derived using linear transformation,
So as to correctly decode out command content.But such scheme has the following disadvantages：Different files in scheme (1)
The different mode of command encoding formats, although the instruction encoding across file can be solved the problems, such as, but for when previous
The instruction protection of Virtual Machine bytecodes file is but completely without effect.As long as conversed analysis person determines that virtual machine instructions are concentrated
The coded format of each instruction can just analyze whole byte code files.Coded format linear transformation in scheme (2),
Security is added a bit, but is due to that coded format is linear transformation, as long as so being tied according to known several conversion
Really, it is possible to extrapolate the process of linear transformation.
The content of the invention
One side according to embodiments of the present invention there is provided a kind of coding method of virtual machine instructions, including：Right
When program to be compiled is compiled, for the virtual machine instructions of the program to be compiled, the virtual machine is changed at random and is referred to
The command encoding formats of order.
Another aspect according to embodiments of the present invention, additionally providing a kind of coding/decoding method of virtual machine instructions includes：Adding
When carrying the virtual machine instructions of program to be compiled, the configured information of the virtual machine instructions is obtained, wherein, it is described to indicate letter
Cease the command encoding formats of the virtual machine instructions for indicating to change at random；According to indicated by the configured information
Command encoding formats are decoded to the virtual machine instructions.
Another aspect according to embodiments of the present invention, additionally provides a kind of code device of virtual machine instructions, including：Repair
Change module, for when treating compiler and being compiled, for the virtual machine instructions of the program to be compiled, at random
Change the command encoding formats of the virtual machine instructions；Directive generation module, for being compiled according to random amended instruction
Code form generates the rear end output order of compiler.
Another aspect according to embodiments of the present invention, additionally provides a kind of decoding apparatus of virtual machine instructions, including：Obtain
Modulus block, for when loading the virtual machine instructions of program to be compiled, obtaining the configured information of the virtual machine instructions,
Wherein, the configured information is for the command encoding formats for the virtual machine instructions for indicating to change at random；Decoder module,
For being decoded according to the command encoding formats indicated by the configured information to the virtual machine instructions.
Another aspect according to embodiments of the present invention, additionally provides a kind of virtual machine protection system, including：Compiler,
For when treating compiler and being compiled, for the virtual machine instructions of the program to be compiled, random modification is described
The command encoding formats of virtual machine instructions；And the rear end of compiler is generated according to random amended command encoding formats
Output order；Virtual machine rendering engine, for loading and performing the rear end output order.
In embodiments of the present invention, using when treating compiler and being compiled, the finger of random modification virtual machine instructions
The technical scheme of coded format is made, the software protection of instruction aspect is realized, improves protection precision, simultaneously because referring to
Make what coded format was randomly generated, enhance decompiling difficulty, improve the security of software, and then solve phase
Code protection can not be carried out in the technology of pass in instruction aspect and because coded format linear transformation causes code to be easy to anti-volume
The technical problem translated.
Brief description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, this hair
Bright schematic description and description is used to explain the present invention, does not constitute inappropriate limitation of the present invention.In accompanying drawing
In：
Fig. 1 is a kind of structural representation of terminal according to the embodiment of the present application；
Fig. 2 is a kind of schematic flow sheet of the coding method of optional virtual machine instructions according to the embodiment of the present application；
Fig. 3 is according to a kind of chaotic principle schematic of optional instruction operation code of the embodiment of the present application；
Fig. 4 is according to a kind of chaotic principle schematic of optional register of the embodiment of the present application；
Fig. 5 is a kind of structured flowchart of the code device of optional virtual machine instructions according to the embodiment of the present application；
Fig. 6 is a kind of another structured flowchart of the code device of optional virtual machine instructions according to the embodiment of the present application；
Fig. 7 is a kind of schematic flow sheet of the coding/decoding method of virtual machine instructions according to the embodiment of the present application；
Fig. 8 is a kind of structured flowchart of the decoding apparatus of virtual machine instructions according to the embodiment of the present application；
Fig. 9 is a kind of structural representation of virtual machine protection system according to the embodiment of the present application；
Figure 10 is the knot that compiler (VMP Compi ler) is protected according to a kind of optional virtual machine of the embodiment of the present application
Structure schematic diagram；
Figure 11 is a kind of workflow schematic diagram of optional virtual machine rendering engine according to the embodiment of the present application；
Figure 12 is a kind of realization principle schematic diagram of optional virtual machine protection system according to the embodiment of the present application；
Figure 13 is a kind of configuration diagram of optional virtual memory model according to the embodiment of the present application；
Figure 14 is a kind of structured flowchart of terminal according to the embodiment of the present application.
Embodiment
In order that those skilled in the art more fully understand the present invention program, below in conjunction with the embodiment of the present invention
Accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment
The only embodiment of a present invention part, rather than whole embodiments.Based on the embodiment in the present invention, ability
The every other embodiment that domain those of ordinary skill is obtained under the premise of creative work is not made, should all belong to
The scope of protection of the invention.
It should be noted that term " first " in description and claims of this specification and above-mentioned accompanying drawing, "
Two " etc. be for distinguishing similar object, without for describing specific order or precedence.It should be appreciated that this
The data that sample is used can be exchanged in the appropriate case, so as to embodiments of the invention described herein can with except
Here the order beyond those for illustrating or describing is implemented.In addition, term " comprising " and " having " and they
Any deformation, it is intended that covering is non-exclusive to be included, for example, containing process, the side of series of steps or unit
Method, system, product or equipment are not necessarily limited to those steps clearly listed or unit, but may include unclear
It is that ground is listed or for the intrinsic other steps of these processes, method, product or equipment or unit.
Before the embodiment of the present application is described in detail, the technical term that may relate in the embodiment of the present application is first introduced：
1.VMP:Full name virtual machine protect, virtual machine protection；
2.bc：Full name byte code, bytecode represents the virtual machine instructions of generation, it is different from Native Code
(code run directly in physical machine)；
3.Guest:Client computer, runs the virtual machine of byte code instruction；
4.Host:Host, runs the physical machine of client computer, is different from client computer；
5.opcode:Instruction operation code, for indicating command operating type；
6.LLVM:Full name lowlevel virtual machine, a compiler framework increased income；
7.IR:Full name Intermediate representation, intermediate representation, compiler is carried out for source program
The internal representation generated after scanning, represents the semanteme and syntactic structure of source program；
8. the virtual machine based on stack：A kind of implementation of process level virtual machine, input when instruction is performed for computing
Operand and output operand are stored in stack；
9. the virtual machine based on register：A kind of implementation of process level virtual machine, for computing when instruction is performed
Input operand and output operand are deposited in a register；
10.RISC：Reduced instruction set computer, a kind of cpu design pattern, species and addressing of this instruction set to instruction
Mode etc. has done simplification.
Embodiment 1
According to the embodiment of the present application, a kind of embodiment of the method for the coding of virtual machine instructions is additionally provided, it is necessary to explanation
It is that can be held the step of the flow of accompanying drawing is illustrated in the computer system of such as one group computer executable instructions
OK, and, although show logical order in flow charts, but in some cases, can be with different from herein
Order perform shown or described step.
The embodiment of the method that the embodiment of the present application 1 is provided can be in mobile terminal, terminal or similar fortune
Calculate in device and perform.Exemplified by running on computer terminals, Fig. 1 is a kind of virtual machine instructions of the embodiment of the present application
Coding method terminal hardware block diagram.As shown in figure 1, terminal 10 can include one
(processor 102 can include but is not limited to Micro-processor MCV to individual or multiple (one is only shown in figure) processor 102
Or PLD FPGA etc. processing unit), the memory 104 for data storage and for communicating
The transmitting device 106 of function.It will appreciated by the skilled person that the structure shown in Fig. 1 is only signal, its
The structure to above-mentioned electronic installation does not cause to limit.For example, terminal 10 may also include than shown in Fig. 1 more
Many either less components or with the configuration different from shown in Fig. 1.
Memory 104 can be used for virtual in the software program and module of storage application software, such as embodiment of the present invention
Corresponding programmed instruction/the module of coding method of machine instruction, processor 102 is stored in memory 104 by operation
Software program and module, so as to perform various function application and data processing, that is, realize above-mentioned application program
Leak detection method.Memory 104 may include high speed random access memory, may also include nonvolatile memory, such as one
Individual or multiple magnetic storage devices, flash memory or other non-volatile solid state memories.In some instances, deposit
Reservoir 104 can further comprise the memory remotely located relative to processor 102, and these remote memories can lead to
Network connection is crossed to terminal 10.The example of above-mentioned network includes but is not limited to internet, intranet, office
Domain net, mobile radio communication and combinations thereof.
Transmitting device 106 is used to data are received or sent via a network.Above-mentioned network instantiation may include
The wireless network that the communication providerses of terminal 10 are provided.In an example, transmitting device 106 includes one
Network adapter (Network Interface Controller, NIC), it can pass through base station and other network equipments
It is connected to be communicated with internet.In an example, transmitting device 106 can be radio frequency (Radio
Frequency, RF) module, it is used to wirelessly be communicated with internet.
Under above-mentioned running environment, this application provides the method for the coding of virtual machine instructions as shown in Figure 2.Fig. 2
It is the flow chart of the method for the coding of virtual machine instructions according to the embodiment of the present application 1.As shown in Fig. 2 this method bag
Include step S202-S204：
Step S202, when treating compiler and being compiled, for the virtual machine instructions of above-mentioned program to be compiled, with
Machine maintenance changes the command encoding formats of above-mentioned virtual machine instructions；
Alternatively, the command encoding formats of above-mentioned virtual machine instructions are changed at random to be accomplished by the following way：(1)
The value of command code in above-mentioned virtual machine instructions is generated at random；(2) generate at random in above-mentioned virtual machine instructions in operand
Register index number.It is of course also possible to which employing mode (1) and mode (2) change above-mentioned virtual machine instructions simultaneously
Command encoding formats, i.e., for above-mentioned virtual machine instructions, at the same change virtual machine instructions in command code value and
Register index number in operand.
For ease of understanding, mode (1) and mode (2) are now illustrated：
On mode (1), also known as instruction operation code (opcode) is chaotic：
Same virtual machine instructions are in the virtual machine instructions not generated in the same time of VMP compilers (Compiler)
Opcode is not fixed, i.e. mapping relations between opcode and instruction encoding can be random chaotic.
As shown in figure 3, with the operation of virtual machine, at some moment, it is instructed with its opcode corresponding relation such as
In Fig. 3 shown in the mapping relations of top, i.e. each instruction (LOAD, STORE, CALL) and opcode value
(i.e. in Fig. 3 upper figure 1,2, N) be one-to-one, i.e., LOAD is corresponding with 1, and STORE is corresponding with 2,
CALL is corresponding with N；And when triggering opcode confusions when running, it will for the mapping table of opcode values
Shuffled at random, its mapping relations after shuffling (mapping relations after shuffling at random referring to mapping relations below Fig. 3,
Mapping relations i.e. between each instruction and instruction operation code are chaotic, i.e., STORE is corresponding with 1, CALL and 2 pair
Should) it can ensure sufficiently random, it is impossible to according to the result after extrapolating before of shuffling at random.
On mode (2), also known as register is chaotic：
Same virtual machine instructions VMP Compiler not in the same time generation virtual machine instructions in its register coding simultaneously
Do not fix, the mapping relations between register and instruction encoding can be random chaotic.Register confusion Principle of Process with
Opcode is chaotic consistent, and what simply this mode was chaotic is register section in instruction encoding, i.e., register address is indexed.
As shown in figure 4, when virtual machine is run, at some moment, register address is indexed and deposit during it is instructed
Corresponding relation between device is as shown in top mapping relations in Fig. 4, and when trigger register is chaotic, register address
The corresponding relation between register is indexed as shown in lower section mapping relations in Fig. 4, i.e. register and register in instruction
Mapping relations between allocation index are chaotic.
Step S204, the rear end output order of compiler is generated according to random amended command encoding formats.
Alternatively, after the command encoding formats of above-mentioned virtual machine instructions are changed at random, for convenience of decoding, in addition it is also necessary to
The command encoding formats of random amended above-mentioned virtual machine instructions are synchronized to virtual machine rendering engine, specifically,
When above-mentioned virtual machine rendering engine loads above-mentioned rear end output order, it will be used to indicate random amended above-mentioned virtual machine
The configured information of the command encoding formats of instruction is carried in above-mentioned rear end output order, and by above-mentioned rear end output order
Send to above-mentioned virtual machine rendering engine.
Using the scheme in the present embodiment and its alternative embodiment, the randomization of bytecode coding is realized, even if cracker
Command encoding formats in the byte code files of a version have inversely been restored, for new byte code files still not
The result inversely reduced can be used, it is necessary to again reverse.In bytecode register and during coding mapping dynamic operation not yet
It is fixed, also increase huge trouble for cracker's analyzer logic, and reduction virtual machine interpreter.Deposit
The random of device mapping relations is also resulted in, and the mode of dump virtual machine state informations is come the side of analysis program during for operation
Method, its dump run time behaviour is also substantially unavailable.
It should be noted that for foregoing each method embodiment, in order to be briefly described, therefore it is all expressed as to one it is
The combination of actions of row, but those skilled in the art should know, the present invention is not limited by described sequence of movement
System, because according to the present invention, some steps can be carried out sequentially or simultaneously using other.Secondly, art technology
Personnel should also know that embodiment described in this description belongs to preferred embodiment, involved action and module
Not necessarily necessary to the present invention.
Through the above description of the embodiments, those skilled in the art can be understood that according to above-mentioned implementation
The method of example can add the mode of required general hardware platform to realize by software, naturally it is also possible to by hardware, but
The former is more preferably embodiment in many cases.Based on it is such understand, technical scheme substantially or
Say that the part contributed to prior art can be embodied in the form of software product, the computer software product is deposited
Storage is in a storage medium (such as ROM/RAM, magnetic disc, CD), including some instructions are to cause a station terminal
Equipment (can be mobile phone, computer, server, or network equipment etc.) is performed described in each embodiment of the invention
Method.
Embodiment 2
According to the embodiment of the present application, a kind of device for being used to implement the coding method of above-mentioned virtual machine instructions is additionally provided,
The device can be run on described in embodiment 1 on terminal, alternatively, in the present embodiment, above-mentioned calculating
Machine terminal can also replace with the terminal devices such as mobile terminal.Fig. 5 is a kind of optional void according to the embodiment of the present application
The structured flowchart of the code device of plan machine instruction.As shown in figure 5, the device includes：Modified module 50 and instruction are generated
Module 52, wherein：
Modified module 50, for when treating compiler and being compiled, referring to for the virtual machine of above-mentioned program to be compiled
Order, changes the command encoding formats of above-mentioned virtual machine instructions at random；Alternatively, modified module 50, in the following manner
The command encoding formats of random modification virtual machine instructions：Generate the value of command code in above-mentioned virtual machine instructions at random, and/
Or, the register index number in generating the operands of above-mentioned virtual machine instructions at random.The process of implementing may refer to reality
The description in example 1 is applied, here is omitted.
Directive generation module 52, is connected to modified module 50, is compiled according to random amended command encoding formats generation
The rear end output order of device
Alternatively, in order to which the virtual machine instructions for ensureing the command encoding formats that have modified at random can be correctly decoded, such as
Shown in Fig. 6, said apparatus can also include following processing module：Synchronization module 54, is connected to directive generation module 52,
For the command encoding formats of random amended above-mentioned virtual machine instructions to be synchronized into virtual machine rendering engine.Alternatively,
The synchronization module 54, is additionally operable to that, when above-mentioned virtual machine rendering engine loads above-mentioned rear end output order, use will be carried
Sent in the rear end output order of the configured information for the command encoding formats for indicating random amended above-mentioned virtual machine instructions
To above-mentioned virtual machine rendering engine.
It should be noted that modules involved in above-described embodiment can be by hardware or software to realize,
For the former, implemented below form, but not limited to this can be shown as：Modified module 50 and directive generation module 52
In same processor；Or, modified module 50 and directive generation module 52 are located at first processor and the respectively
In two processors.
Embodiment 3
According to the embodiment of the present application, a kind of coding/decoding method of virtual machine instructions, the coding/decoding method and embodiment are additionally provided
1 is corresponding with the encoding scheme in 2, and it can also be applied to described in embodiment 1 on terminal, alternatively,
In the present embodiment, above computer terminal can also replace with the terminal devices such as mobile terminal.As shown in fig. 7, should
Method includes：
Step S702, when loading the virtual machine instructions of program to be compiled, obtains the configured information of above-mentioned virtual machine instructions,
Wherein, above-mentioned configured information is used to indicate to change the command encoding formats of above-mentioned virtual machine instructions at random；Alternatively, with
The command encoding formats for the above-mentioned virtual machine instructions that machine maintenance changes refer to：Command code in the above-mentioned virtual machine instructions generated at random
Value and/or the above-mentioned virtual machine instructions that generate at random in register index number in operand.In an optional implementation
In example, above-mentioned configured information can be obtained from above-mentioned virtual machine instructions.
Step S704, as indicated above the command encoding formats indicated by information above-mentioned virtual machine instructions are decoded.
Because the decoding scheme in the present embodiment and the scheme in embodiment 1 are similar, therefore, for the present embodiment
In optional embodiment related to embodiment 1 or identical scheme may refer to description in embodiment 1, herein not
Repeat again.
Embodiment 4
According to the embodiment of the present application, a kind of device for being used to implement the coding/decoding method of above-mentioned virtual machine instructions is additionally provided,
The device can be run on described in embodiment 1 on terminal, alternatively, in the present embodiment, above-mentioned calculating
Machine terminal can also replace with the terminal devices such as mobile terminal.Fig. 8 is to be referred to according to a kind of virtual machine of the embodiment of the present application
The structured flowchart of the decoding apparatus of order.As shown in figure 8, the device includes：Acquisition module 80 and decoder module 82,
Wherein：
Acquisition module 80, for when loading the virtual machine instructions of program to be compiled, obtaining the finger of above-mentioned virtual machine instructions
Show information, wherein, above-mentioned configured information is for the command encoding formats for the above-mentioned virtual machine instructions for indicating to change at random；
Alternatively, the command encoding formats for the above-mentioned virtual machine instructions changed at random refer to：The above-mentioned virtual machine generated at random refers to
Register index number in order in the value of command code and/or the above-mentioned virtual machine instructions generated at random in operand.
Alternatively, acquisition module 80, which obtains the mode of above-mentioned configured information, a variety of, for example, can refer to from above-mentioned virtual machine
Above-mentioned configured information is obtained in order, i.e., carries above-mentioned configured information in above-mentioned virtual machine instructions.
In one alternate embodiment, the manifestation mode of above-mentioned configured information has a variety of, for example, can utilize both sides' agreement
Good mark and the mapping relations of command encoding formats, i.e., above-mentioned configured information are mark；It can also be instruction coding lattice
Formula is in itself.The manifestation mode of above-mentioned configured information specifically can be flexibly selected according to actual conditions.
Decoder module 82, is connected to acquisition module 80, for the command encoding formats indicated by information as indicated above
Above-mentioned virtual machine instructions are decoded.
It should be noted that modules involved in above-described embodiment can be by hardware or software to realize,
For the former, implemented below form, but not limited to this can be shown as：Acquisition module 80 and decoder module 82 are located at
In same processor；Or, acquisition module 80 and decoder module 82 are located at first processor and second processing device respectively
In.
Further, since the decoding scheme in the present embodiment is similar with the scheme in embodiment 1-2, therefore, for
Optional embodiment related to embodiment 1 or identical scheme may refer to the description in embodiment 1 in the present embodiment,
Here is omitted.
Embodiment 5
According to the embodiment of the present application, additionally providing one kind is used to implement above-mentioned virtual machine protection system, as shown in figure 9,
The system includes：
Compiler 90, for when treating compiler and being compiled, for the virtual machine instructions of above-mentioned program to be compiled,
The command encoding formats of above-mentioned virtual machine instructions are changed at random；And generated according to random amended command encoding formats
The rear end output order of compiler；Alternatively, above-mentioned compiler 90, is grasped for generating at random in above-mentioned virtual machine instructions
Make the value of code；And/or register index number in above-mentioned virtual machine instructions in operand is generated at random.
Alternatively, above-mentioned compiler 90, is additionally operable to the command encoding formats of random amended above-mentioned virtual machine instructions
It is synchronized to above-mentioned virtual machine rendering engine.
Virtual machine rendering engine 92, for loading and performing above-mentioned rear end output order.
Wherein, can be virtual machine protection compiler (VMP compiler), below in conjunction with one for compiler 90
Individual alternative embodiment is described in detail.
Figure 10 shows that virtual machine protects the framework of compiler, it should be understood that, framework is only shown in Figure 10
Virtual machine protects an example of compiler in the embodiment of the present application, i.e., the framework of compiler 90 can in the embodiment of the present application
To include but is not limited to the structure in framework shown in Figure 10.As shown in Figure 10：
It is LLVM front ends (Frontend) 100 on the left of Figure 10, supports left side in various programming languages, such as Figure 10
Shown C front ends (front end for supporting C/C++ language), formula translation (Formula Translation, referred to as
Fortran) front end (front end for supporting Fortran language), Ada language etc..It is LLVM IR 102 in the middle of Figure 10,
Intermediate representation language for supporting LLVM；It is LLVM rear ends 104 on the right side of Figure 10, the LLVM project supports are existing
A variety of rear ends (Backend), including x86 rear ends and PowerPC rear ends etc..VMP Compiler in the embodiment of the present application
A kind of new rear end VMPRISC rear ends are added on this basis, and are realized and referred to from LLVM IR to VMPRISC
Make the generating process of collection.It should be noted that compiler 90 and the virtual machine of LLVM projects in the embodiment of the present application
Although protecting compiler more similar in structure, its function of implementing is different, for example, this Shen
Compiler 90 that please be in embodiment can be to the register section in the instruction operation code and operand in virtual machine instructions
Random assignment is carried out, so that call instruction command code and the mapping relations instructed are chaotic at random, and the deposit in operand
Mapping relations between device part and instruction are chaotic at random.
It should be noted that the structure of compiler 90 is referred to structure shown in Figure 10 in the present embodiment, for example, compiling
Translate device 90 can also include compiler front-end, IR ends, compiler back-end, wherein it is possible to by compiler back-end come
The chaotic process of virtual machine instructions coded format is realized, a processing module or list can also be further added by compiler back-end
Member realizes the chaotic process of command encoding formats, but not limited to this.
In one alternate embodiment, virtual machine rendering engine is as the significant components in VMP defence program instruments, its
Workflow is as shown in figure 11, including：
Step S1102, instruction fetch process obtains the Virtual Machine bytecodes content that current virtual machine PC registers are pointed to；
Step S1104, solves code instruction, according to the Virtual Machine bytecodes content of reading, decodes virtual machine instructions structure；
Step S1106, call instruction analog function, according to instruction decoding result, calls the processing procedure of command adapted thereto,
The operation of dummy instruction；
Step S1108, mobile PC, by one instruction of PC steppings, that is, PC=PC+4；
Step S1110, judges halt condition, and S1102 is gone to step if halt condition is unsatisfactory for, is otherwise terminated.
For the check system of the virtual machine instructions in above-described embodiment and its alternative embodiment, its realization principle such as Figure 12
It is shown：The check system of virtual machine instructions is roughly divided into two processes when being verified to instruction：
(1) bytecode generating process, corresponding to module VMP Compiler
There is provided by protection code (program code of i.e. above-mentioned program to be compiled) in c language source codes form, pass through VMP
Compiler ultimately generates Virtual Machine bytecodes file (i.e. bc files).It should be noted that the performance shape of source code
Formula is not limited only to C language, can also be Fortran language, Ada language etc..
(2) bytecode explains implementation procedure, corresponding to module VMP SDK, wherein, Main Basiss are empty in VMP SDK
Plan machine rendering engine completes the implementation procedure of bytecode.
Wherein, the General Logic in Figure 12 refers to the code that will not be protected by VMP, because its security is than relatively low,
So not being that software needs core logic (the kernel program .h.c i.e. in figure) to be protected.Its act on be responsible for initialization and
Call VMP SDK.At present because the start-up course of the program of various systems is all inconsistent, VMP SDK are not for difference
System does different initialization process, so needing General Logic code to initialize and call VMP SDK.For example,
The entrance of Android program is that in java codes, and the entrance of iOS programs is in Object-C, these
Code is exactly General Logic, is responsible for initialization and calls VMP SDK.
Called when needing and calling the function by protection code by VMP SDK by protection code, VMP SDK loadings
And perform Virtual Machine bytecodes file.
Wherein, it can be realized for virtual machine involved in above-described embodiment and its preferred embodiment by following framework,
But not limited to this：
1) virtual cpu framework：
1.32 risc instruction sets, memory address and register are 32.
2. instruction encoding storage format is little endian mode.
3. instruction addressing mode is immediate and register addressing, the access for internal memory must pass through load/store
Instruction is completed；
2) memory architecture
When main frame (Host) on the left of Figure 13 represents operation by defence program, client (guest) generation on right side
The VM of table operation.
Host calls VM by VMP SDK, and details is realized because VMP SDK encapsulate VM, so Host can be with
Accomplish that platform is unrelated, you can with compatible all mainstream operation systems and CPU at present.
Guest is with sandbox mode operation, and with oneself independent memory address space, guest memory headrooms are divided into
Following part：
1) the invalid address space started with 0x0；
2) Virtual Machine bytecodes region, for depositing the virtual machine instructions for needing to run；
3) heap region, meets dynamic memory distribution demand when virtual machine code is performed；
4) stack region, the temporary space such as temporary variable and return address storage distribution need when meeting virtual machine code operation
Ask.
It should be noted that compiler and virtual machine rendering engine involved in above-described embodiment and its alternative embodiment
It can be realized in the form of software or hardware, for the latter, can show as realizing that compiler and virtual machine are explained
Computer or processor of the function of engine etc., but not limited to this.
Embodiment 6
Embodiments herein can provide a kind of terminal, the terminal can be terminal group in
Any one computer terminal.The terminal can be the terminal in embodiment 1.Alternatively, at this
In embodiment, above computer terminal can also replace with the terminal devices such as mobile terminal.
Alternatively, in the present embodiment, above computer terminal can be located in multiple network equipments of computer network
At least one network equipment.
Alternatively, Figure 14 is a kind of structured flowchart of terminal according to the embodiment of the present application.As shown in figure 14,
The terminal 14 can include：One or more (one is only shown in figure) processors, memory, Yi Jichuan
Defeated device.The server of the terminal and network side passes through network connection.
Wherein, memory can be used for storage software program and module, such as the virtual machine instructions in the embodiment of the present application
Method of calibration and the corresponding programmed instruction/module of device, processor by operation be stored in the software program in memory with
And module, so as to perform various function application and data processing, that is, realize the method for calibration of above-mentioned virtual machine instructions.
Memory may include high speed random access memory, can also include nonvolatile memory, and such as one or more magnetic is deposited
Storage device, flash memory or other non-volatile solid state memories.In some instances, memory can further comprise
The memory remotely located relative to processor, these remote memories can pass through network connection to terminal A.It is above-mentioned
The example of network includes but is not limited to internet, intranet, LAN, mobile radio communication and combinations thereof.
In the present embodiment, above computer terminal can perform the journey of following steps in the coding methods of virtual machine instructions
Sequence code：When treating compiler and being compiled, for the virtual machine instructions of above-mentioned program to be compiled, random modification
The command encoding formats of above-mentioned virtual machine instructions；The rear end of compiler is generated according to random amended command encoding formats
Output order.
Processor in above computer terminal can call the information and application program of memory storage by transmitting device,
To perform following step：The value of command code in the virtual machine instructions is generated at random；And/or, the void is generated at random
Register index number in the operand of plan machine instruction.
Optionally, above-mentioned processor can also carry out the program code of following steps：Will be random amended described virtual
The command encoding formats of machine instruction are synchronized to virtual machine rendering engine.
Optionally, above-mentioned processor can also carry out the program code of following steps：Add in the virtual machine rendering engine
When carrying the rear end output order, by the command encoding formats for indicating the random amended virtual machine instructions
Configured information is carried in the rear end output order, and the rear end output order is sent to virtual machine explanation
Engine.
Using the embodiment of the present application, solve and can not be carried out in correlation technique in instruction aspect code protection and due to compiling
Code form linear transformation causes code to be easy to the technical problem of decompiling.
It will appreciated by the skilled person that the structure shown in Figure 14 is only signal, terminal can also be
Smart mobile phone (such as Android phone, iOS mobile phones), panel computer, palm PC and mobile internet device
The terminal device such as (Mobile Internet Devices, MID), PAD.Figure 14 its not to above-mentioned electronic installation
Structure cause limit.For example, terminal 14 may also include the component more or less than shown in Figure 14
(such as network interface, display device), or with the configuration different from shown in Figure 14.
One of ordinary skill in the art will appreciate that all or part of step in the various methods of above-described embodiment is can be with
Completed by program come the device-dependent hardware of command terminal, the program can be stored in a computer-readable storage medium
In matter, storage medium can include：Flash disk, read-only storage (Read-Only Memory, ROM), deposit at random
Take device (Random Access Memory, RAM), disk or CD etc..
Embodiment 7
Embodiments herein can provide a kind of terminal for being used to realize the coding/decoding method of virtual machine instructions, should
Terminal can be any one computer terminal in terminal group.The terminal can be
Terminal in embodiment 1 or 6.Alternatively, in the present embodiment, above computer terminal can also replace with movement
The terminal devices such as terminal.
Terminal in the present embodiment can perform the program code of following steps in the coding/decoding methods of virtual machine instructions：
When loading the virtual machine instructions of program to be compiled, the configured information of the virtual machine instructions is obtained, wherein, it is described to refer to
Show information for the command encoding formats for the virtual machine instructions for indicating to change at random；It is signified according to the configured information
The command encoding formats shown are decoded to the virtual machine instructions.
Terminal in the present embodiment can also include：One or more processors, memory and transmission dress
Put.
Processor in above computer terminal can call the information and application program of memory storage by transmitting device,
With the correlation step for the coding/decoding method for performing virtual machine instructions, the correlation step is referring to described in embodiment 3, herein not
Repeat again.
Embodiment 8
Embodiments herein additionally provides a kind of storage medium.Alternatively, in the present embodiment, above-mentioned storage medium
It can be used for preserving the program code performed by the coding method for the virtual machine instructions that above-described embodiment one is provided.
Alternatively, in the present embodiment, above-mentioned storage medium can be located in computer network Computer terminal group
In any one terminal, or in any one mobile terminal in mobile terminal group.
Alternatively, in the present embodiment, storage medium is arranged to the program code that storage is used to perform following steps：
When treating compiler and being compiled, for the virtual machine instructions of the program to be compiled, change described virtual at random
The command encoding formats of machine instruction；The rear end output order of compiler is generated according to random amended command encoding formats.
Embodiment 9
Embodiments herein additionally provides another storage medium.Alternatively, in the present embodiment, above-mentioned storage is situated between
Matter can be used for preserving the program code performed by the coding/decoding method for the virtual machine instructions that above-described embodiment 3 is provided.
Alternatively, in the present embodiment, above-mentioned storage medium can be located in computer network Computer terminal group
In any one terminal, or in any one mobile terminal in mobile terminal group.
Alternatively, in the present embodiment, storage medium is arranged to the program code that storage is used to perform following steps：
When loading the virtual machine instructions of program to be compiled, the configured information of above-mentioned virtual machine instructions is obtained, wherein, above-mentioned finger
Show information for the command encoding formats for the above-mentioned virtual machine instructions for indicating to change at random；Information is signified as indicated above
The command encoding formats shown are decoded to above-mentioned virtual machine instructions.
The embodiments of the present invention are for illustration only, and the quality of embodiment is not represented.
In the above embodiment of the present invention, the description to each embodiment all emphasizes particularly on different fields, and does not have in some embodiment
The part of detailed description, may refer to the associated description of other embodiment.
In several embodiments provided herein, it should be understood that disclosed client, others can be passed through
Mode is realized.Wherein, device embodiment described above is only schematical, such as division of described unit,
It is only a kind of division of logic function, there can be other dividing mode when actually realizing, such as multiple units or component
Another system can be combined or be desirably integrated into, or some features can be ignored, or do not perform.It is another, institute
Display or the coupling each other discussed or direct-coupling or communication connection can be by some interfaces, unit or mould
The INDIRECT COUPLING of block or communication connection, can be electrical or other forms.
The unit illustrated as separating component can be or may not be it is physically separate, it is aobvious as unit
The part shown can be or may not be physical location, you can with positioned at a place, or can also be distributed to
On multiple NEs.Some or all of unit therein can be selected to realize the present embodiment according to the actual needs
The purpose of scheme.
In addition, each functional unit in each embodiment of the invention can be integrated in a processing unit, can also
That unit is individually physically present, can also two or more units it is integrated in a unit.It is above-mentioned integrated
Unit can both be realized in the form of hardware, it would however also be possible to employ the form of SFU software functional unit is realized.
If the integrated unit realized using in the form of SFU software functional unit and as independent production marketing or in use,
It can be stored in a computer read/write memory medium.Understood based on such, technical scheme essence
On all or part of the part that is contributed in other words to prior art or the technical scheme can be with software product
Form is embodied, and the computer software product is stored in a storage medium, including some instructions are to cause one
Platform computer equipment (can be personal computer, server or network equipment etc.) performs each embodiment institute of the invention
State all or part of step of method.And foregoing storage medium includes：USB flash disk, read-only storage (ROM, Read-Only
Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disc or CD
Etc. it is various can be with the medium of store program codes.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improve and moistened
Decorations also should be regarded as protection scope of the present invention.
Claims (20)
1. a kind of coding method of virtual machine instructions, it is characterised in that including：
When treating compiler and being compiled, for the virtual machine instructions of the program to be compiled, random modification
The command encoding formats of the virtual machine instructions；
The rear end output order of compiler is generated according to random amended command encoding formats.
2. according to the method described in claim 1, it is characterised in that change the instruction encoding of the virtual machine instructions at random
Form, including：
The value of command code in the virtual machine instructions is generated at random.
3. method according to claim 1 or 2, it is characterised in that change the instruction of the virtual machine instructions at random
Coded format includes：
The register index number in the operand of the virtual machine instructions is generated at random.
4. according to the method described in claim 1, it is characterised in that change the instruction encoding of the virtual machine instructions at random
After form, methods described also includes：
The command encoding formats of the random amended virtual machine instructions are synchronized to virtual machine rendering engine.
5. method according to claim 4, it is characterised in that by the finger of the random amended virtual machine instructions
Coded format is made to be synchronized to virtual machine rendering engine, including：
When the virtual machine rendering engine loads the rear end output order, it will be used to indicating random amended
The configured information of the command encoding formats of the virtual machine instructions is carried in the rear end output order, and by institute
Rear end output order is stated to send to the virtual machine rendering engine.
6. a kind of coding/decoding method of virtual machine instructions, it is characterised in that including：
When loading the virtual machine instructions of program to be compiled, the configured information of the virtual machine instructions is obtained, wherein,
The configured information is for the command encoding formats for the virtual machine instructions for indicating to change at random；
The virtual machine instructions are decoded according to the command encoding formats indicated by the configured information.
7. method according to claim 6, it is characterised in that the instruction for the virtual machine instructions changed at random is compiled
Code form refers to：
The value of command code and/or the virtual machine generated at random refer in the virtual machine instructions generated at random
Register index number in order in operand.
8. method according to claim 7, it is characterised in that obtain the configured information of the virtual machine instructions, bag
Include：
The configured information is obtained from the virtual machine instructions.
9. a kind of code device of virtual machine instructions, it is characterised in that including：
Modified module, for when treating compiler and being compiled, for the virtual machine of the program to be compiled
Instruction, changes the command encoding formats of the virtual machine instructions at random；
Directive generation module, the rear end for generating compiler according to random amended command encoding formats is exported
Instruction.
10. device according to claim 9, it is characterised in that the modified module, for generating the void at random
The value of command code in the instruction of plan machine.
11. the device according to claim 9 or 10, it is characterised in that the modified module, is additionally operable to random generation
Register index number in the operand of the virtual machine instructions.
12. device according to claim 9, it is characterised in that described device also includes：Synchronization module, for inciting somebody to action
The command encoding formats of the random amended virtual machine instructions are synchronized to virtual machine rendering engine.
13. device according to claim 12, it is characterised in that the synchronization module, is additionally operable in the virtual machine
When rendering engine loads the rear end output order, it will carry for indicating the random amended virtual machine
The rear end output order of the configured information of the command encoding formats of instruction is sent to the virtual machine rendering engine.
14. a kind of decoding apparatus of virtual machine instructions, it is characterised in that including：
Acquisition module, for when loading the virtual machine instructions of program to be compiled, obtaining the virtual machine instructions
Configured information, wherein, the configured information is for the instruction encoding for the virtual machine instructions for indicating to change at random
Form；
Decoder module, for according to the command encoding formats indicated by the configured information to the virtual machine instructions
Decoded.
15. device according to claim 14, it is characterised in that the instruction for the virtual machine instructions changed at random is compiled
Code form refers to：The value of command code and/or the void generated at random in the virtual machine instructions generated at random
Register index number in the instruction of plan machine in operand.
16. device according to claim 14, it is characterised in that the acquisition module, for referring to from the virtual machine
The configured information is obtained in order.
17. a kind of virtual machine protection system, it is characterised in that including：
Compiler, for when treating compiler and being compiled, referring to for the virtual machine of the program to be compiled
Order, changes the command encoding formats of the virtual machine instructions at random；And according to random amended instruction encoding
Form generates the rear end output order of compiler；
Virtual machine rendering engine, for loading and performing the rear end output order.
18. system according to claim 17, it is characterised in that the compiler, described virtual for generating at random
The value of command code in machine instruction；And/or register index in the virtual machine instructions in operand is generated at random
Number.
19. system according to claim 17, it is characterised in that the compiler, being additionally operable to will be random amended
The command encoding formats of the virtual machine instructions are synchronized to the virtual machine rendering engine.
20. system according to claim 19, it is characterised in that the virtual machine rendering engine, is additionally operable to load institute
Virtual machine instructions are stated, and are obtained from the virtual machine instructions for indicating that the random amended virtual machine refers to
The configured information of the command encoding formats of order.
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