CN106952952A - A kind of III V CMOS-types are counterfeit to match somebody with somebody HFET - Google Patents
A kind of III V CMOS-types are counterfeit to match somebody with somebody HFET Download PDFInfo
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- 230000004888 barrier function Effects 0.000 claims abstract description 35
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- 229910005542 GaSb Inorganic materials 0.000 claims abstract description 25
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- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
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- 239000010980 sapphire Substances 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 230000003139 buffering effect Effects 0.000 claims 1
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- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 3
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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Abstract
The present invention relates to semiconductor device processing technology field, specifically related to a kind of broad stopband III V CMOS-types based on silicon substrate, combining n-channel transistor and p-channel transistor are counterfeit to match somebody with somebody HFET, the type Heterostructure Field Effect Transistor Materials use MOCVD or MBE equipment epitaxial growths, by the first multilayer lattice strain cushion of epitaxial growth, InGaSb channel layers, AlGaSb barrier layers, GaSb cap layers, the second multilayer lattice strain cushion, InGaAs channel layers, AlGaAs barrier layers and In successively on high resistivity silicon substrateXGa1‑XAs cap layers are constituted.The present invention can effectively lift p-channel transistor mobility, the problem of to improve the huge difference of n-channel transistor and p-channel transistor mobility in III V, and the broad stopband III V group crystal tube passages of high carrier speed and high driving current are provided, short-channel effect is brought during effective improvement transistor scaled down, reduce power consumption, overcome Moore's Law, break the limit, maintain semiconductor industry scaled down process.
Description
Technical field
The invention belongs to semiconductor device processing technology field, and in particular to a kind of III-V CMOS-types are counterfeit to match somebody with somebody heterojunction field
Effect transistor.
Background technology
According to Moore's Law, " number of open ended component on integrated circuit will about increase every 18-24 months
One times, performance will also lift one times ".On the whole for, if the IC of same specification is produced under wafer of the same area, with processing procedure
The progress of technology, every a year and a half, IC quantums of output can be doubled, and be scaled cost, i.e., can be reduced every a year and a half cost
Fifty percent, every year on average cost can reduce by three into many.With regard to Moore's Law extension, IC technologies promote a generation every a year and a half.State
Border semiconductor-on-insulator manufacturer all follows this law substantially.
But, maximum Intel of chip maker announces that skills will be manufactured based on 10 nanometers under postponement a few days ago in the world
The issuing time of the Cannonlake chips of art, was postponed to the second half year in 2017, and Cannonlake chips original date of issue
Phase is 2016.Intel company CEO Brian Krzanich are represented in videoconference, " due to using all kinds of phases
Pass technology, and each technology has its own a series of complexity and difficulties, from 14 nanometers to 10 nanometers and from 22 nanometers
It is not the same thing to 14 nanometers.If it is desired to large-scale production, photoetching technique can be more difficult, moreover, completing Suresh Kumar step
Number can be continuously increased ".Intel follows the timetable of every two years diminution transistor volume all the time, that is, be commonly called as
" Moore's Law ", above-mentioned message makes timetable slight crack occur, and it is that construction chip becomes to become increasingly complex to trace it to its cause, and power consumption is more next
More it is difficult to reduce, and various short-channel effects are difficult to overcome.
Therefore, although semiconductor technology is showing improvement or progress day by day, but is limited by physical law, and minimum dimension can not possibly be too small, to prolong
The validity of continuous semiconductor Moore's Law, processor transistor is made using new material very urgent.At present
Existing many research institutions, through the material that higher performance is integrated for silicon materials, for example with compound semiconductor materials such as
InGaAs/InP (such as InGaAsP and indium phosphide), forms the transistor of so-called broad stopband III-V raceway grooves, can promote p-
Type mobilities and offer high carrier speed and high driving current, this new compound semiconductor are expected to surmount silicon materials sheet
Body performance, maintains Moore's Law, realizes and continues scaled down.
But this scheme also encounters many problems at present, be primarily present of both challenge, on the one hand, silica-base material and
There is big lattice constant between compound semiconductor materials such as GaAs/InP poor, atom is brilliant between material can not be overcome always
Lattice are difficult to the problem matched；On the other hand, usual Si based transistors are bonded by p channel transistor and n-channel transistor
CMOS structure applies to large scale digital field, and n-channel device is easily realized generally in terms of III-V such as GaAs devices, and p ditches
Road device is limited to doping engineering and epitaxial manufacture process, while the mobility of p-channel is far below n-channel, combine at present n- raceway grooves and
The GaAs transistors of p- raceway grooves differ too big (6500 due to both mobilities：300), it is impossible to realize the same circuit structures of CMOS,
Greatly hinder application of the GaAs devices in digital circuit field.
The content of the invention
Counterfeit with HFET it is an object of the invention to provide a kind of III-V CMOS-types, the field-effect is brilliant
Body pipe can solve that existing transistor power consumption during scaled down is difficult to reduce, short-channel effect is difficult to overcome well
The problem of.
To reach above-mentioned requirements, the present invention is adopted the technical scheme that：There is provided a kind of III-V CMOS-types counterfeit with hetero-junctions
Field-effect transistor, including p channel transistor and n-channel transistor, p channel transistor are that AlGaSb/InGaSb pHFET are (counterfeit
With HFET), n-channel transistor is GaAspHEMT (pseudomorphic high electron mobility transistor)；P-channel is brilliant
Body pipe epitaxial growth the first multilayer lattice strain cushion, InGaSb channel layers and AlGaSb barrier layers successively on a silicon substrate,
The GaSb cap layers of growth regulation one and the 2nd GaSb cap layers above AlGaSb barrier layers, the InGaSb channel layers and AlGaSb barrier layers
Form two-dimensional hole gas；It is formed with the first GaSb cap layers in the first drain electrode, and AlGaSb barrier layers and is formed with the first grid
The first source electrode is formed with pole, the 2nd GaSb cap layers；N-channel transistor epitaxial growth successively in the 2nd GaSb cap layers
Growth regulation one above two multilayer lattice strain cushions, InGaAs channel layers and AlGaAs barrier layers, AlGaAs barrier layers
InXGa1-XAs cap layers and the 2nd InXGa1-XAs cap layers, the InGaAs channel layers and AlGaAs barrier layers formation two-dimensional hole gas,
And the first InXGa1-XIt is formed with As cap layers on the second source electrode, AlGaAs barrier layers and is formed with second grid, the 2nd InXGa1-XAs
The second drain electrode is formed with cap layers.The extension hetero-junctions of n-channel transistor of the present invention matches somebody with somebody heterogeneous structure by AlGaAs/InGaAs is counterfeit
Into p-channel transistor extension hetero-junctions is constituted by AlGaSb/InGaSb is counterfeit with heterogeneous.
Compared with prior art, the present invention has advantages below：
(1) counterfeit matched somebody with somebody based on silicon substrate, the broad stopband III-V CMOS-types for being integrated with n-channel transistor and p-channel transistor
HFET can be effectively improved the short-channel effect brought during transistor scaled down, and can reduce
Power consumption, realizes the lasting scaled down of dimensions of semiconductor devices；
(2) AlGaSb barrier layers are adulterated to be formed using p-type, and two-dimensional hole gas is formed between InGaSb channel layers, can be had
The mobility of effect lifting p channel transistor, it is huge to improve n-channel transistor and p-channel transistor mobility difference in III-V
The problem of；
(3) first multilayer lattice strain cushions can be used for absorbing between silicon-based substrate and subsequent epitaxial layer because lattice loses
Stress with generation, filter out substrate generation scattering center, it is to avoid produce lattice relaxation, effectively overcome subsequent epitaxial layer with
The problem of atomic lattice is difficult to matching between silicon-based substrate；
(4) second multilayer lattice strain cushions can be used for absorbing p channel transistor and follow-up n-channel transistor epitaxial layer
Between because lattice mismatch produce stress, it is to avoid produce lattice relaxation；
(5) first multilayer lattice strain cushions and the second multilayer lattice strain cushion are the compound of multiple material composition
Buffer layer structure, due to the band difference between different materials, forms multiple quantum well structures, can effectively obstruct disconnected silicon substrate
Defect spreads to InGaSb channel layers, and the defect of the disconnected 2nd GaSb cap layers of barrier spreads to InGaAs channel layers；
(6) the first InXGa1-XAs cap layers and the 2nd InXGa1-XAs cap layers are highly doped cap, can compared with traditional cap layers
More preferable Ohmic contact is provided to be prepared for device；
(7) InGaAs channel layers and AlGaAs barrier layers formation lattice are counterfeit with AlGaAs/InGaAs heterojunction structures, effectively carry
High device electronic mobility.
Brief description of the drawings
Accompanying drawing described herein is used for providing further understanding of the present application, the part of the application is constituted, at this
Same or analogous part, the schematic description and description of the application are represented using identical reference number in a little accompanying drawings
For explaining the application, the improper restriction to the application is not constituted.In the accompanying drawings：
Fig. 1 is structural representation of the invention.
Embodiment
To make the purpose, technical scheme and advantage of the application clearer, below in conjunction with drawings and the specific embodiments, to this
Application is described in further detail.For the sake of simplicity, eliminate that well known to a person skilled in the art some skills in describing below
Art feature.
As shown in figure 1, the present embodiment is provided, a kind of III-V CMOS-types are counterfeit to match somebody with somebody HFET, uses
MOCVD or MBE equipment epitaxial growths, including p channel transistor and n-channel transistor；P channel transistor is on a silicon substrate successively
It is raw above epitaxial growth the first multilayer lattice strain cushion, InGaSb channel layers and AlGaSb barrier layers, AlGaSb barrier layers
Long first GaSb cap layers and the 2nd GaSb cap layers, the InGaSb channel layers and the general 5nm regions in AlGaSb barrier layers contact position
Two-dimensional hole gas is formed, as shown in a dotted line below in Fig. 1；The first drain electrode is formed with the first GaSb cap layers, and
It is formed with AlGaSb barrier layers in first grid, the 2nd GaSb cap layers and is formed with the first source electrode, first grid is located at the first leakage
Between pole and the first source electrode；N-channel transistor the second multilayer of epitaxial growth lattice strain successively in the 2nd GaSb cap layers
The In of growth regulation one above cushion, InGaAs channel layers and AlGaAs barrier layers, AlGaAs barrier layersXGa1-XAs cap layers 1 and
Two InXGa1-XAs cap layers 2, the InGaAs channel layers form Two-Dimensional Hole with the general 5nm regions in AlGaAs barrier layers contact position
Gas, as shown in a dotted line above in Fig. 1；And the first InXGa1-XThe second source electrode, AlGaAs barrier layers are formed with As cap layers 1
On be formed with second grid, the 2nd InXGa1-XIt is formed with the second drain electrode in As cap layers 2, second grid is located at the second drain electrode and the
Between two source electrodes.
Silicon substrate is high resistance p-type Si substrates, and its material is Si, SiC, GaN, sapphire or diamond, mainly as branch
Timbering material.
First multilayer lattice strain cushion, for absorbing between silicon-based substrate and subsequent epitaxial layer material because lattice loses
Stress with generation；Undope, thickness is 800~1800nm, first GaAs grown at low temperature cushion, then high growth temperature from bottom to up
GaAs/AlGaAs super-lattice buffer layers, then GaAs is grown using gradient-structureySb1-yAs cushions, regrowth GaSb/AlGaSb
Super-lattice buffer layer；Y value is progressively reduced to 0 from 1；Al content is less than 30% in GaSb/AlGaSb super-lattice buffer layers.
InGaSb channel layers undope, and thickness is 15~30nm, and In contents are less than 30%.
AlGaSb barrier layers, for forming Schottky contacts with gate metal, and provide the freely empty of InGaSb channel layers
Cave；Thickness is 15~40nm, and Al content is less than 30%, adulterated using p-type, and body dopant material is Be, C or Mg, and dopant dose is 1
×1018cm-3~3 × 1018cm-3。
First GaSb cap layers and the 2nd GaSb cap layers, to protect AlGaSb barrier layers not oxidized, while to reduce
Ohmic contact resistance rate；Thickness be 15~40nm, adulterated using p-type, body dopant material be Be, C or Mg, dopant dose be 5 ×
1018cm-3~2 × 1019cm-3。
Second multilayer lattice strain cushion, p channel transistor is to the cushion between n-channel transistor, for absorbing P
Because the stress that lattice mismatch is produced between channel transistor and follow-up n-channel transistor epitaxial layer, it is to avoid produce lattice relaxation；
Undope, 600~1500nm of thickness first grows GaAs using gradient-structure from bottom to upySb1-yCushion, regrowth GaAs/
AlGaAs super-lattice buffer layers；Y value is progressively upgraded to 1 from 0；Al content is less than 30% in GaAs/AlGaAs super-lattice buffer layers.
InGaAs channel layers undope, and thickness is 15~30nm, and In contents are less than 30%；Crystalline substance is formed with AlGaAs barrier layers
Lattice are counterfeit to match somebody with somebody AlGaAs/InGaAs heterojunction structures, to improve device electronic mobility.
AlGaAs barrier layers, for forming Schottky contacts with gate metal, and provide the free hole of GaAs channel layers；
Adulterated using N-shaped, thickness is 15~40nm, Al content is less than 30%, adulterated using N-shaped, body doping Si dosage for 1 ×
1018cm-3~3 × 1018cm-3。
First InXGa1-XThe In of As cap layers 1 and the 2ndXGa1-XAs cap layers 2, to protect AlGaAs barrier layers not oxidized, together
When to reduce ohmic contact resistance rate；Thickness is 15~40nm, wherein 0<x<0.5, In component x gradually rises from 0；Using n
Type adulterates, and body doping Si dosage is 5 × 1018cm-3~2 × 1019cm-3。
Above example only represents the several embodiments of the present invention, and it describes more specific and detailed, but can not manage
Solve as limitation of the scope of the invention.It should be pointed out that for the person of ordinary skill of the art, not departing from this hair
On the premise of bright design, various modifications and improvements can be made, these belong to the scope of the present invention.Therefore the present invention
Protection domain should be defined by claim.
Claims (10)
1. a kind of III-V CMOS-types are counterfeit to match somebody with somebody HFET, it is characterised in that including p channel transistor and n ditches
Road transistor；P channel transistor epitaxial growth the first multilayer lattice strain cushion, InGaSb channel layers successively on a silicon substrate
And AlGaSb barrier layers, the AlGaSb barrier layers top GaSb cap layers of growth regulation one and the 2nd GaSb cap layers, the InGaSb raceway grooves
Layer and AlGaSb barrier layers formation two-dimensional hole gas；The first drain electrode, and AlGaSb potential barriers are formed with the first GaSb cap layers
It is formed with layer in first grid, the 2nd GaSb cap layers and is formed with the first source electrode；N-channel transistor is in the 2nd GaSb cap layers
On epitaxial growth the second multilayer lattice strain cushion, InGaAs channel layers and AlGaAs barrier layers, AlGaAs barrier layers successively
The In of top growth regulation oneXGa1-XAs cap layers and the 2nd InXGa1-XAs cap layers, the InGaAs channel layers and AlGaAs barrier layer shapes
Into two-dimensional hole gas, and the first InXGa1-XIt is formed with As cap layers on the second source electrode, AlGaAs barrier layers and is formed with second gate
Pole, the 2nd InXGa1-XThe second drain electrode is formed with As cap layers.
2. III-V CMOS-types according to claim 1 are counterfeit to match somebody with somebody HFET, it is characterised in that the silicon
Substrate is high resistance p-type Si substrates, and its material is Si, SiC, GaN, sapphire or diamond.
3. III-V CMOS-types according to claim 1 or 2 are counterfeit to match somebody with somebody HFET, it is characterised in that institute
State the first multilayer lattice strain cushion to undope, thickness is 800~1800nm, from bottom to up first GaAs grown at low temperature buffering
Layer, then high growth temperature GaAs/AlGaAs super-lattice buffer layers, then GaAs is grown using gradient-structureySb1-yAs cushions, regeneration
Long GaSb/AlGaSb super-lattice buffer layers；Y value is progressively reduced to 0 from 1；Al content is small in GaSb/AlGaSb super-lattice buffer layers
In 30%.
4. III-V CMOS-types according to claim 3 are counterfeit to match somebody with somebody HFET, it is characterised in that described
InGaSb channel layers undope, and thickness is 15~30nm, and In contents are less than 30%.
5. III-V CMOS-types according to claim 3 are counterfeit to match somebody with somebody HFET, it is characterised in that described
AlGaSb barrier layer thickness is 15~40nm, and Al content is less than 30%, adulterated using p-type, and body dopant material is Be, C or Mg, is mixed
Miscellaneous dosage is 1 × 1018cm-3~3 × 1018cm-3。
6. III-V CMOS-types according to claim 3 are counterfeit to match somebody with somebody HFET, it is characterised in that described the
The thickness of one GaSb cap layers and the 2nd GaSb cap layers is 15~40nm, is adulterated using p-type, and body dopant material is Be, C or Mg, is mixed
Miscellaneous dosage is 5 × 1018cm-3~2 × 1019cm-3。
7. the III-V CMOS-types according to right wants 3 are counterfeit with HFET, it is characterised in that described second
Multilayer lattice strain cushion undopes, 600~1500nm of thickness, first grows GaAs using gradient-structure from bottom to upySb1-y
Cushion, regrowth GaAs/AlGaAs super-lattice buffer layers；Y value is progressively upgraded to 1 from 0；GaAs/AlGaAs superlattices are buffered
Al content is less than 30% in layer.
8. the III-V CMOS-types according to any claims of claim 4-7 are counterfeit with HFET, its feature
It is that the InGaAs channel layers undope, thickness is 15~30nm, In contents are less than 30%.
9. the III-V CMOS-types according to any claims of claim 4-7 are counterfeit with HFET, its feature
It is that the thickness of the AlGaAs barrier layers is 15~40nm, and Al content is less than 30%, adulterated using N-shaped, body doping Si agent
Measure as 1 × 1018cm-3~3 × 1018cm-3。
10. the III-V CMOS-types according to any claims of claim 4-7 are counterfeit with HFET, its feature
It is, the first InXGa1-XAs cap layers and the 2nd InXGa1-XThe thickness of As cap layers be 15~40nm, In components x=0~0.5,
And In components x gradually rises from 0；Adulterated using N-shaped, body doping Si dosage is 5 × 1018cm-3~2 × 1019cm-3。
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| CN201710192961.0A CN106952952B (en) | 2017-03-28 | 2017-03-28 | A kind of III-V CMOS type is counterfeit to match heterojunction field effect transistor |
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| WO2021243653A1 (en) * | 2020-06-04 | 2021-12-09 | 英诺赛科（珠海）科技有限公司 | Semiconductor apparatus and manufacturing method therefor |
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