CN106888016B - A kind of current-steering digital-to-analog converter and current steer digital-to-analogue method for transformation - Google Patents

Abstract

The invention discloses a current steering digital-to-analog converter and a current steering digital-to-analog conversion method, comprising: a digital input circuit for receiving digital data input, and sending the digital data to a row decoder and a column decoder device; a shuffling circuit connected to both the row decoder and the column decoder, for generating a switch sequence, and sending the switch sequence to the row decoder and the column decoder; and the A row decoder and a column decoder respectively connected to the digital input circuit are used to convert the row data and column data of the digital data into corresponding thermometer codes in combination with the switching sequence; and send the converted thermometer codes Give the current source matrix; the current source matrix is used to control the on and off of the current according to the received thermometer code, and output the current data; the current-voltage converter connected to the current source matrix is used to convert the current data Convert to voltage data.

Description

A current steering digital-to-analog converter and a current steering digital-to-analog conversion method

technical field

The invention relates to integrated circuit technology, in particular to a current steering digital-to-analog converter and a current steering digital-to-analog conversion method.

Background technique

The development of communication technology has put forward higher requirements for the speed and precision of digital-to-analog converters (DACs, Digital to Analog Converters). High-definition video and high-quality calls all require high-speed DACs. Current Steering Digital to Analog Converters (CS DAC, Current Steering Digital to Analog Converters) can effectively alleviate this contradiction. Different from DACs with other structures, CS DAC has a simple structure, consisting of a binary current source or a current source matrix, plus a current switch controlled by a binary number or a thermometer code controller converted by a decoder. The current from the current source can be switched to a resistor directly connected to ground (for high-speed applications), as shown in Figure 1, or to a feedback resistor through a buffer (for low-speed applications), as shown in Figure 2. In practical applications, the output adopts a differential structure to reduce the interference of common mode noise on the output analog signal. In order to improve the matching characteristics of the current source, the unit current source array is usually used instead of the binary current source.

FIG. 2 shows the structure of a conventionally basic current source unit (current cell). Each current source unit includes a positive current composed of P-type metal insulator semiconductor (PMOS, Positive Channel Metal Oxide Semiconductor) MP and MPC, and a negative current composed of N-type metal insulator semiconductor (NMOS, Negative Channel Metal Oxide Semiconductor) MN and MNC. current. The input digital data of the DAC is converted into current control signals DC and DCB through a decoder under the control of the clock, which controls the opening and closing of this current source. The resulting differential current signals I _op and I _on are then applied to a current-to-voltage converter (I2V) formed by a buffer feedback resistor (or a resistor directly connected to ground), thereby outputting the corresponding converted differential voltage OUTP and OUTN.

Figure 3 shows the relevant input and output waveforms of the current source unit in Figure 2. clk is the input clock of the DAC, data is the input digital data, and DAC current is the corresponding output current I _op or I _on .

Due to the finite speed of the circuit, the output current of the DAC has finite rising and falling edges t _r and t _f . When the input data data is a single logic '1', the output current has a rising edge and a falling edge in a clock cycle; when the input is a series of continuous logic '1' (such as three in Figure 3) , the output current will also have a rising edge at the beginning of this continuous '1' and a falling edge at the end, as shown in Figure 3.

The energy of the final output signal of the DAC is related to the integral of the current versus time (that is, the area contained under the DAC current waveform in Figure 3, such as A ₀ , ..., A ₃ , etc.). Assuming that an ideal current source corresponding to the input data '1' has a current output area of 1, A0 in Figure 3 corresponds to 1-ΔAr+ΔAf, where ΔAr is the area lost due to the limited rising edge, and ΔAf is the area due to the falling along the increased area. Generally speaking, ΔAr≠ΔAf, and due to changes in temperature and process, it is difficult for the two to be equal. In Fig. 3, A ₁ =1-ΔA _r , A ₂ =1, A ₃ =1+ΔA _f . So the ratio A ₁ :A ₀ , A ₂ :A ₀ , A ₃ :A ₀ between them is no longer a 1:1 relationship. That is, the energy of the output signal produces an error relative to the amplitude of the input signal, causing harmonic distortion in the output signal. The harmonic distortion of the signal caused by this phenomenon is called Inter-Symbol Interference (ISI).

A common method to eliminate the above-mentioned harmonic distortion of the DAC output signal due to the limited rising/falling edges of the output current is shown in Figure 4. The current shown in Figure 3 is no longer turned on during the entire clock cycle, but the current shown in Figure 4 only needs to be turned on for a part of a clock cycle, such as half of the clock cycle shown in the figure. If it is still assumed that the current output of an ideal current source corresponding to the input data '1' is 1 in one clock cycle, then the area A ₀ , ..., A ₃ covered by each output current in Figure 4 is 1/ 2-ΔA _r +ΔA _f . This eliminates errors associated with input signal amplitude differences, known as harmonic distortion. The switching method in which the current only needs to be turned on for a part of a clock cycle in Figure 4 is called return-to-zero (RZ). In contrast, implementations like those in Figure 3 are called non-return-to-zero (NRZ).

Although the RZ switching method in Figure 4 eliminates the harmonic distortion caused by the above ISI, it will lose the efficiency of the circuit part because the current is only turned on for part of a clock cycle; secondly, because the turn-on time of the current is shortened, it The requirement on the speed of the current unit circuit, especially the subsequent I2V buffer, will increase with the shortening of the switching time, that is, the power consumption of the circuit will increase.

Contents of the invention

In order to solve the above technical problems, embodiments of the present invention provide a current steering digital-to-analog converter and a current steering digital-to-analog conversion method.

The current steering digital-to-analog converter provided by the embodiment of the present invention includes:

a digital input circuit, configured to receive input of digital data, and send said digital data to a row decoder and a column decoder;

A shuffling circuit connected to both the row decoder and the column decoder, for generating a switching sequence and sending the switching sequence to the row decoder and the column decoder;

A row decoder and a column decoder respectively connected to the digital input circuit are used to convert the row data and column data of the digital data into corresponding thermometer codes in combination with the switching sequence; and convert the converted The thermometer code is sent to the current source matrix;

The current source matrix is used to control the on and off of the current and output the current data according to the received thermometer code;

A current-to-voltage converter connected to the current source matrix is used to convert the current data into voltage data.

In the embodiment of the present invention, the current steering digital-to-analog converter further includes: a clock selection circuit, configured to control the frequency of the clock.

In the embodiment of the present invention, the current source matrix is composed of a plurality of current source units; the current source unit includes: a PMOS circuit, an NMOS circuit, a pair of common-source and common-drain switches MPSW1 and MPSW2, another pair of common-source pole-common-drain switches MPSW3 and MPSW4; a pair of common-source and common-drain switches MNSW1 and MNSW2, and another pair of common-source and common-drain switches MNSW3 and MNSW4.

In the embodiment of the present invention, the gate of MPSW1 is connected to DC, the gate of MPSW2 is connected to DCB, and the drain is connected to IOP; the gate of _MPSW3 is connected to DBC, the gate of MPSW4 is connected to DBCB, and the drain is connected to I _ON . MPSW1, MPSW2 and The sources of MPSW3 and MPSW4 are connected to common PMOS bias current sources MP and MPC;

The gate of MNSW1 is connected to DC, the gate of MNSW2 is connected to DCB, and the drain is connected to I _ON ; the gate of MNSW3 is connected to DBC, the gate of MNSW4 is connected to DBCB, and the drain is connected to IOP; the sources of _MNSW1 , MNSW2, MNSW3, and MNSW4 Connected to the common NMOS bias current sources MN and MNC; I _OP and I _ON are connected to both ends of the current-to-voltage converter I2V;

Among them, switch control signals DC, DCB, DBC, DBCB are generated by two digital data.

In the embodiment of the present invention, the switch control signals DC, DCB, DBC, and DBCB are respectively:

DC=shuffle×data;

DCB=shuffleb×data;

DBC=shuffle×datab;

DBCB=shuffleb×datab;

Wherein, shuffle and shuffleb are the switch sequences, and data and datab are the digital data.

In the embodiment of the present invention, when the clock frequency is the same as the digital data rate, each pair of switches is turned on every half clock cycle under the selection of the switching sequence;

When the clock frequency is half of the digital data rate, each pair of switches is turned on in turn at a half cycle of the current clock under the selection of the switching sequence.

In the embodiment of the present invention, the current-to-voltage converter is a feedback resistor formed by a buffer, or a resistor directly grounded.

The current steering digital-to-analog conversion method provided by the embodiment of the present invention includes:

accept input of digital data, and generate switching sequences;

converting row data and column data of the digital data into corresponding thermometer codes, respectively, in combination with the switch sequence;

According to the received thermometer code, control the on and off of the current, and output the current data;

Converting the current data to voltage data.

The embodiment of the present invention uses the CS DAC current source unit and the shuffling circuit to realize the current steering DAC with equal opportunity disturbance, and ensure that the current output corresponding to the input digital data of N consecutive logic '1' and a single logic '1' is absolutely accurate The N-fold relationship of the non-return-to-zero code DAC solves the problem of harmonic distortion caused by the rising and falling edges, and at the same time avoids the introduction of additional power consumption like the return-to-zero code DAC. The technical solution of the embodiment of the present invention proposes an Equal Perturbation (EP, Equal Perturbation) current switch control method, aiming at the harmonic distortion problem of the output signal caused by the above-mentioned ISI of the CS DAC, by increasing the clock frequency and collecting data with two edges, In order to realize the RZ current switching mode twice in one data cycle; or without increasing the clock frequency, the NRZ switching mode is realized alternately by two current switches. This method has the characteristics of limited rising and falling edges for the switching current, so that each logic '1' in the digital data has the same number of rising and falling edges, thereby eliminating the harmonic distortion caused by ISI. On the other hand, the embodiment of the present invention does not cause additional requirements on circuit power consumption because the disturbance to the output signal is small within one clock cycle.

Description of drawings

Figure 1 is the basic structure diagram of the current steering DAC;

Fig. 2 is a current source unit diagram of a traditional current source matrix;

Fig. 3 is a schematic diagram of traditional CS DAC input clock and data waveforms, as well as output current waveforms and current errors;

Fig. 4 is a schematic diagram of traditional improved current output waveform and ISI error elimination;

5 is a schematic diagram of the structure and composition of the current steering digital-to-analog converter according to the embodiment of the present invention;

6 is a schematic diagram of a current source unit of a current source matrix according to an embodiment of the present invention;

Fig. 7 is a schematic diagram of the output current waveform and the elimination of ISI error in the current switching mode approximate to NRZ according to the embodiment of the present invention;

Fig. 8 is a schematic diagram of the output current waveform and the elimination of ISI error by using continuous logic '1' data to introduce two-way current switches to turn on and off in turn according to an embodiment of the present invention;

FIG. 9 is a schematic flowchart of a current steering digital-to-analog conversion method according to an embodiment of the present invention.

Detailed ways

In order to understand the characteristics and technical contents of the embodiments of the present invention in more detail, the implementation of the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. The attached drawings are only for reference and description, and are not intended to limit the embodiments of the present invention.

The current-steer digital-to-analog converter of the embodiment of the present invention is a novel equal-opportunity perturbation CS DAC, which generates two RZ current waveforms in one data period through two current switches at a clock frequency twice that of the digital data, whichever The results are summed and stitched into an approximate NRZ output waveform. Alternatively, a shuffle circuit is introduced into the switch logic control module, and by turning on and off the two current switches in turn, a rising edge is introduced into the current output corresponding to each logic '1' in the input data data With a falling edge, the elimination of harmonic distortion caused by ISI is realized.

Fig. 5 is a schematic diagram of the structural composition of the current steering digital-to-analog converter according to the embodiment of the present invention. As shown in Fig. 5, the current steering digital-to-analog converter includes:

A digital input circuit 51, configured to receive input of digital data, and send the digital data to a row decoder 52 and a column decoder 53;

The shuffling circuit 54 connected to the row decoder 52 and the column decoder 53 is used to generate a switch sequence, and send the switch sequence to the row decoder 52 and the column decoder 53;

A row decoder 52 and a column decoder 53 respectively connected to the digital input circuit 51 are used to convert the row data and column data of the digital data into corresponding thermometer codes respectively in combination with the switching sequence; and Send the converted thermometer code to the current source matrix 55;

The current source matrix 55 is used to control the on and off of the current and output the current data according to the received thermometer code;

A current-to-voltage converter (I2V) 56 connected to the current source matrix 55 is used to convert the current data into voltage data.

The current steering digital-to-analog converter further includes: a clock selection circuit 57 for controlling the frequency of the clock.

The current source matrix 55 is composed of a plurality of current source units; the current source unit includes: a P-type metal insulator semiconductor PMOS circuit, an N-type metal insulator semiconductor NMOS circuit, a pair of common source and common drain switches MPSW1 and MPSW2, Another pair of common-source and common-drain switches MPSW3 and MPSW4; a pair of common-source and common-drain switches MNSW1 and MNSW2, and another pair of common-source and common-drain switches MNSW3 and MNSW4.

The gate of MPSW1 is connected to DC, the gate of MPSW2 is connected to DCB, and the drain is connected to IOP; the gate of _MPSW3 is connected to DBC, the gate of MPSW4 is connected to DBCB, the drain is connected to I _ON , and the sources of MPSW1, MPSW2, MPSW3 and MPSW4 Connected to the common PMOS bias current source MP and MPC;

The gate of MNSW1 is connected to DC, the gate of MNSW2 is connected to DCB, and the drain is connected to I _ON ; the gate of MNSW3 is connected to DBC, the gate of MNSW4 is connected to DBCB, and the drain is connected to IOP; the sources of _MNSW1 , MNSW2, MNSW3, and MNSW4 Connected to the common NMOS bias current sources MN and MNC; I _OP and I _ON are connected to both ends of the current-to-voltage converter I2V;

I _OP and I _ON are connected to both ends of I2V, specifically, I _OP and I _ON are connected to the two input terminals of the analog BUF, and the two input terminals and output terminals of the analog BUF cross-border resistors and capacitors to act as current and voltage The role of the converter (I2V), the output of the I2V outputs an analog voltage.

Among them, switch control signals DC, DCB, DBC, DBCB are generated by two digital data.

The switch control signals DC, DCB, DBC, DBCB are respectively:

DC=shuffle×data;

DCB=shuffleb×data;

DBC=shuffle×datab;

DBCB=shuffleb×datab;

Wherein, shuffle and shuffleb are the switch sequences, and data and datab are the digital data.

When the clock frequency is the same as the digital data rate, each pair of switches is turned on every half clock cycle under the selection of the switching sequence;

When the clock frequency is half of the digital data rate, each pair of switches is turned on in turn at a half cycle of the current clock under the selection of the switching sequence.

The current-to-voltage converter 56 is a feedback resistor formed by a buffer, or a resistor directly grounded.

In the embodiment of the present invention, referring to FIG. 5, compared with the traditional structure in FIG. 1, the new current steering digital-to-analog conversion method in the embodiment of the present invention adds a shuffling (shuffle) circuit on the current switch control link, and can Selected by adding a clock selection circuit. Correspondingly, the matrix unit circuit of the power source matrix of the present invention is shown in FIG. 6 . The shuffling circuit generates sequentially interleaved sampling current source switching sequence, which is provided to the row decoder and the column decoder. The thermometer code after row decoding and column decoding is passed to the current source matrix. The output end of the current source matrix is connected to I2V to realize the conversion of current to voltage.

As shown in Figure 6, it is a circuit structure diagram of the current source unit of the embodiment of the present invention, which is divided into a PMOS part and an NMOS part, and the switch is formed by superimposing the output of two DACs generated by four sets of signals DC, DCB, DBC, and DBCB. MPSW1 and MPSW2 are a pair of common source and common drain switches. The gate of MPSW1 is connected to DC, the gate of MPSW2 is connected to DCB, and the drain is connected to I _OP ; MPSW3 and MPSW4 are another pair of common-source and common-drain switches. The gate of MPSW3 is connected to DBC, the gate of MPSW4 is connected to DBCB, and the drain is connected to I _ON . The sources of MPSW1, MPSW2, MPSW3, and MPSW4 are connected to common PMOS bias current sources MP and MPC. MNSW1 and MNSW2 are a pair of common-source and common-drain switches. The gate of MNSW1 is connected to DC, the gate of MNSW2 is connected to DCB, and the drain is connected to I _ON ; MNSW3 and MNSW4 are another pair of common-source and common-drain switches. The gate of MNSW3 is connected to DBC, the gate of MNSW4 is connected to DBCB, and the drain is connected to I _OP . The sources of MNSW1, MNSW2 and MNSW3, MNSW4 are connected to common NMOS bias current sources MN and MNC. I _OP and I _ON are connected to both ends of I2V. I2V can be a feedback resistor through a buffer, or a resistor directly to ground. The I2V differential output is the output OUTP and OUTN of the DAC, which completes the conversion from digital to analog. I _OP and I _ON are connected to both ends of I2V, specifically, I _OP and I _ON are connected to the two input terminals of the analog BUF, and the two input terminals and output terminals of the analog BUF cross-border resistors and capacitors to act as current and voltage The role of the converter (I2V), the output of the I2V outputs an analog voltage.

In the cell circuit of FIG. 6, the switch control signal DC=shuffle×data, DCB=shuffleb×data, DBC=shuffle×datab, DBCB=shuffleb×datab. Therefore, in each data cycle, the positive and negative currents are determined by the logic value of data which flows to I _op and which flows to I _on . Which of the current control switches MPSW1 and MPSW2 , MPSW3 and MPSW4 , MNSW1 and MNSW2 , MNSW3 and MNSW4 flows through each pair of current control switches is determined by the logic value of shuffle. When the frequency of the frequency-divided control clock CLK is the same as the data rate, each pair of switches above will be turned on every half clock cycle under the selection of shuffle; similarly, when the frequency of the frequency-divided control clock CLK is half of the data rate, the above Each pair of switches will also be turned on in turn every half clock cycle under the selection of shuffle. So the shuffle module is like shuffling the cards so that the two switches of each pair of current switches are alternately turned on and off in a non-stop cycle.

FIG. 7 shows the output current waveform and current error of the basic unit of the current source in FIG. 6 when the frequency of the control clock CLK is the same as the data rate. It can be seen that under the selection of the shuffle module, for example, the switch MPSW1 is turned on first in the first half clock cycle, while the switch MPSW2 is turned off at this time; in the second half clock cycle, the switch MPSW1 is turned off, and the switch MPSW2 is turned on; the next clock cycle, the switch MPSW1 is turned on again in the first half of the clock cycle, and the switch MPSW2 is turned off. Since each pair of switches alternates on and off once in each data cycle, the coverage area (A _i +A' _i , i=0,...,3) of each current source in a data cycle is 1- 2×ΔA _r +2×ΔA _f . Therefore, no matter what the data format in data is, all current outputs corresponding to '1' are equal, that is, the harmonic distortion caused by ISI is eliminated. Since the current loss caused by the rising edge and the current addition caused by the falling edge can be partially offset when each pair of switches alternates, the disturbance to the circuit is small, and there is no obvious additional demand for circuit power consumption.

Fig. 8 shows the situation when the frequency of the control clock CLK is half of the data rate. Similar to the above analysis, under the selection of the shuffle module, each pair of current control switches is alternately turned on and off every half clock cycle (ie, a data cycle). It can be seen from Fig. 8 that the coverage area (A _i +A' _i , i=0,...,3) of each current source in one data period is 1-ΔA _r +ΔA _f , which also eliminates the Harmonic distortion caused by ISI. Moreover, the maximum disturbance caused by this method to the circuit is the same as that of the traditional method in FIG. 2 , so there is no additional demand for power consumption.

It should be understood that the structure of the equal-opportunity perturbation CS DAC proposed by the present invention is two implementations of the invention of a combination of a clock selection circuit, a shuffling circuit (shuffle), and a symmetrical current source matrix, which can also diffract new Embodiments are also encompassed and encompassed by the present invention.

Fig. 9 is a schematic flow chart of a current steering digital-to-analog conversion method according to an embodiment of the present invention. The current steering digital-to-analog conversion method in this example is applied to the above-mentioned current steering digital-to-analog converter, as shown in Fig. 9, the method includes the following step:

Step 901: Receive input of digital data, and generate switch sequence.

Specifically, the digital input circuit receives input of digital data and sends the digital data to the row decoder and the column decoder.

A shuffling circuit connected to both the row decoder and the column decoder generates a switching sequence and sends the switching sequence to the row decoder and the column decoder.

Step 902: Combining with the switching sequence, convert the row data and column data of the digital data into corresponding thermometer codes respectively.

A row decoder and a column decoder respectively connected to the digital input circuit combine the switching sequence to convert the row data and column data of the digital data into corresponding thermometer codes; and send the converted thermometer codes to Give the current source matrix.

Step 903: According to the received thermometer code, control the on and off of the current, and output the current data.

The current source matrix controls the on and off of the current according to the received thermometer code, and outputs the current data.

Step 904: Convert the current data into voltage data.

A current-to-voltage converter connected to the matrix of current sources converts the current data into voltage data.

In the above solution, the current source matrix is composed of a plurality of current source units; the current source unit includes: a PMOS circuit, an NMOS circuit, a pair of common-source and common-drain switches MPSW1 and MPSW2, another pair of common-source and common-drain switches Drain switches MPSW3 and MPSW4; a pair of common-source and common-drain switches MNSW1 and MNSW2, and another pair of common-source and common-drain switches MNSW3 and MNSW4.

The gate of MPSW1 is connected to DC, the gate of MPSW2 is connected to DCB, and the drain is connected to IOP; the gate of _MPSW3 is connected to DBC, the gate of MPSW4 is connected to DBCB, the drain is connected to I _ON , and the sources of MPSW1, MPSW2, MPSW3 and MPSW4 Connected to the common PMOS bias current source MP and MPC;

The gate of MNSW1 is connected to DC, the gate of MNSW2 is connected to DCB, and the drain is connected to I _ON ; the gate of MNSW3 is connected to DBC, the gate of MNSW4 is connected to DBCB, and the drain is connected to IOP; the sources of _MNSW1 , MNSW2, MNSW3, and MNSW4 Connected to common NMOS bias current sources MN and MNC; I _OP and I _ON connected to both ends of I2V;

Among them, switch control signals DC, DCB, DBC, DBCB are generated by two digital data.

Specifically, I _OP and I _ON are connected to the two ends of I2V. Specifically, I _OP and I _ON are connected to the two input terminals of the analog BUF, and the two input terminals and output terminals of the analog BUF cross-border resistors and capacitors. To the function of the current voltage converter (I2V), the output terminal of I2V outputs an analog voltage.

The switch control signals DC, DCB, DBC, DBCB are respectively:

DC=shuffle×data;

DCB=shuffleb×data;

DBC=shuffle×datab;

DBCB=shuffleb×datab;

Wherein, shuffle and shuffleb are the switch sequences, and data and datab are the digital data.

When the clock frequency is the same as the digital data rate, each pair of switches is turned on every half clock cycle under the selection of the switching sequence;

When the clock frequency is half of the digital data rate, each pair of switches is turned on in turn at a half cycle of the current clock under the selection of the switching sequence.

Those skilled in the art should understand that the current steering digital-to-analog conversion method shown in FIG. 9 can be understood with reference to the relevant description of the aforementioned current steering digital-to-analog converter.

The technical solutions described in the embodiments of the present invention may be combined arbitrarily if there is no conflict.

In the several embodiments provided by the present invention, it should be understood that the disclosed methods and smart devices can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or May be integrated into another system, or some features may be ignored, or not implemented. In addition, the coupling, or direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical or other forms of.

The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units; Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention may be fully integrated into a second processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; The above-mentioned integrated units can be implemented in the form of hardware, or in the form of hardware plus software functional units.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention.

Claims (11)

1. a kind of current-steering digital-to-analog converter characterized by comprising

The numerical data for receiving the input of numerical data, and is sent to line decoder and column are translated by digital input circuit Code device；

The shuffling circuit being all connected with the line decoder and column decoder, for generating on off sequence, and by the switch sequence Column are sent to the line decoder and column decoder, wherein the on off sequence is for following two switches of each pair of current switch Ring is alternately opened and closed；

The line decoder and column decoder being separately connected with the digital input circuit are used in conjunction with the on off sequence, by institute The row data and column data for stating numerical data are respectively converted into corresponding thermometer-code；And the thermometer-code of conversion is sent to electricity Source matrix is flowed, wherein the thermometer-code allows each logic ' 1 ' in the numerical data to have equal number of up and down Edge；

Current source matrix, according to the thermometer-code, controls the Push And Release of electric current, output electricity for receiving the thermometer-code Flow data；

The current-to-voltage convertor being connect with the current source matrix, for the current data to be converted to voltage data.

2. current-steering digital-to-analog converter according to claim 1, which is characterized in that the current-steering digital-to-analog converter also wraps It includes: clock selection circuit, for controlling the frequency of clock.

3. current-steering digital-to-analog converter according to claim 1, which is characterized in that the current source matrix is by multiple electric currents Set of source at；The current source cell includes: p-type metal-insulator semiconductor (MIS) PMOS circuit, N-type metal-insulator semiconductor (MIS) NMOS circuit, a pair of of common source common drain switch MPSW1 and MPSW2, another pair common source common drain switch MPSW3 and MPSW4； A pair of of common source common drain switch MNSW1 and MNSW2, another pair common source common drain switch MNSW3 and MNSW4.

4. current-steering digital-to-analog converter according to claim 3, which is characterized in that

The grid of MPSW1 meets DC, and the grid of MPSW2 meets DCB, and drain electrode meets I_OP；The grid of MPSW3 meets DBC, and the grid of MPSW4 connects DBCB, drain electrode meet I_ON, MPSW1, MPSW2 and MPSW3, MPSW4 source electrode connect in common pmos bias current source MP and MPC On；

The grid of MNSW1 meets DC, and the grid of MNSW2 meets DCB, and drain electrode meets I_ON；The grid of MNSW3 meets DBC, and the grid of MNSW4 connects DBCB, drain electrode meet I_OP；MNSW1, MNSW2 and MNSW3, MNSW4 source electrode connect in common NMOS bias current sources MN and MNC On；I_OPAnd I_ONIt is connected to the both ends of current-to-voltage convertor I2V；

Wherein, switch control signal DC, DCB, DBC, DBCB by two numerical datas generation.

5. current-steering digital-to-analog converter according to claim 4, which is characterized in that the switch control signal DC, DCB, DBC, DBCB are respectively as follows:

DC=shuffle × data；

DCB=shuffleb × data；

DBC=shuffle × datab；

DBCB=shuffleb × datab；

Wherein, shuffle and shuffleb is the on off sequence, and data and datab are the numerical data.

6. current-steering digital-to-analog converter according to claim 5, which is characterized in that

When clock frequency is identical as digital data rates, when each pair of current switch is every half under the selection of the on off sequence The clock period is open-minded in turn；

When clock frequency be digital data rates half when, each pair of current switch under the selection of the on off sequence with it is current when The half period of clock is open-minded in turn.

7. current-steering digital-to-analog converter according to claim 1, which is characterized in that the current-to-voltage convertor is to utilize The feedback resistance that buffer is formed, or the resistance to be directly grounded.

8. a kind of current steer digital-to-analogue method for transformation characterized by comprising

The input of numerical data is received, and generates on off sequence, wherein the on off sequence is for making each pair of current switch Two switch cycles are alternately opened and closed；

In conjunction with the on off sequence, the row data and column data of the numerical data are respectively converted into corresponding thermometer-code, Wherein the thermometer-code allows each logic ' 1 ' in the numerical data to have equal number of up and down edge；

According to the thermometer-code is received, the Push And Release of electric current, output current data are controlled；

The current data is converted into voltage data.

9. a kind of current-steering digital-to-analog converter characterized by comprising

The numerical data for receiving the input of numerical data, and is sent to line decoder and column are translated by digital input circuit Code device；

The shuffling circuit being all connected with the line decoder and column decoder, for generating on off sequence, and by the switch sequence Column are sent to the line decoder and column decoder；

The line decoder and column decoder being separately connected with the digital input circuit are used in conjunction with the on off sequence, by institute The row data and column data for stating numerical data are respectively converted into corresponding thermometer-code；And the thermometer-code of conversion is sent to electricity Flow source matrix；

Current source matrix, according to the thermometer-code, controls the Push And Release of electric current, output electricity for receiving the thermometer-code Flow data；

The current-to-voltage convertor being connect with the current source matrix, for the current data to be converted to voltage data；

The current source matrix is made of multiple current source cells；The current source cell includes: p-type metal-insulator semiconductor (MIS) PMOS circuit, N-type metal-insulator semiconductor (MIS) NMOS circuit, a pair of of common source common drain switch MPSW1 and MPSW2, another pair Common source common drain switch MPSW3 and MPSW4；A pair of of common source common drain switch MNSW1 and MNSW2, another pair common source are total Drain switch MNSW3 and MNSW4；

The grid of MPSW1 meets DC, and the grid of MPSW2 meets DCB, and drain electrode meets I_OP；The grid of MPSW3 meets DBC, and the grid of MPSW4 connects DBCB, drain electrode meet I_ON, MPSW1, MPSW2 and MPSW3, MPSW4 source electrode connect in common pmos bias current source MP and MPC On；

The grid of MNSW1 meets DC, and the grid of MNSW2 meets DCB, and drain electrode meets I_ON；The grid of MNSW3 meets DBC, and the grid of MNSW4 connects DBCB, drain electrode meet I_OP；MNSW1, MNSW2 and MNSW3, MNSW4 source electrode connect in common NMOS bias current sources MN and MNC On；I_OPAnd I_ONIt is connected to the both ends of current-to-voltage convertor I2V；

Wherein, switch control signal DC, DCB, DBC, DBCB by two numerical datas generation.

10. current-steering digital-to-analog converter according to claim 9, which is characterized in that the switch control signal DC, DCB, DBC, DBCB are respectively as follows:

DC=shuffle × data；

DCB=shuffleb × data；

DBC=shuffle × datab；

DBCB=shuffleb × datab；

Wherein, shuffle and shuffleb is the on off sequence, and data and datab are the numerical data.

11. current-steering digital-to-analog converter according to claim 10, which is characterized in that

When clock frequency is identical as digital data rates, each pair of switch every half of clock week under the selection of the on off sequence Phase is open-minded in turn；

When clock frequency is digital data rates half, each pair of switch is under the selection of the on off sequence with present clock The half period is open-minded in turn.