CN106877863A - OSC circuits on a kind of high stability low-power consumption piece - Google Patents
OSC circuits on a kind of high stability low-power consumption piece Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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Abstract
The invention discloses OSC circuits on a kind of high stability low-power consumption piece, the charge-discharge circuit carries out discharge and recharge, the discharge and recharge of switch controlled electric capacity to electric capacity by current source；The control circuit, the level state that the charge-discharge circuit is exported is changed, and the output signal for producing oscillator final, the oscillator output signal controls the switch of the charge-discharge circuit breaker in middle pipe again；Circuit structure of the present invention is simple, low in energy consumption, can realize exporting oscillation functions；The current source carrys out image current by common-source common-gate current mirror, therefore electric current I1, I2 stability for producing is high, so that the frequency of oscillation stabilization of OSC circuits；The NMOS tube M13 is decoupling capacitor, can be with stabilized supply voltage so that the electric current stabilization of generation, while improving the frequency of oscillation stability of OSC circuits, noise is low；Present invention eliminates the comparator in original technology and control section, and phase inverter, two input nor gate and rest-set flip-flops are used, chip occupying area is small.
Description
Technical field
The present invention relates to OSC circuits on a kind of high stability low-power consumption piece, belong to pierce circuit technical field.
Background technology
Oscillator in most of electronic systems is essential part, even more communication system as a kind of frequency source
The core of system.Oscillator type mainly has four kinds：Ring oscillator, LC oscillator, crystal oscillator and relaxation oscillation
Device.The circuit of ring oscillator is relatively simple, easily vibrates, be relatively easy to it is integrated, but the frequency of time delay network is unfavorable for
Flexible selection is made, power consumption is big compared with high, phase noise.LC oscillator is difficult collection due to inductance in integrated circuits
Into, therefore be rarely used.Crystal oscillator output frequency precision for ring oscillator and LC oscillator
Highest and do not influenceed by temperature and supply voltage, performance indications are optimal.But because the cost of crystal oscillator is very high and work(
Consumption is also bigger than ring oscillator and LC oscillator, therefore is not widely used in market various electronic products, only one
A bit for being used in oscillator frequency required precision field very high.The principle of relaxor is then using current cycle
Ground electric capacity is carried out discharge and recharge complete vibration, this oscillator have simple structure, be easily controlled, the linearity is high, can produce saw
The advantages of tooth ripple and square wave.
A kind of structure of traditional oscillators as described in Figure 1, circuit mainly by PMOS M1 and NMOS tube M2, switch SW1 and
SW2, high position and low level comparator and control section constitute.Its course of work is as follows：Electric current is provided by PMOS M1
I1, electric current I2 is provided by NMOS tube M2.When power supply just goes up electricity, capacitance voltage V_C is low level, and this level is produced by comparator
One logic, so as to control SW1 to turn on, SW2 is disconnected, then electric current I1 is charged to electric capacity C so that V_C is constantly raised, when V_C is high
When high position threshold voltage V_H, there is saltus step in output logic, and then cause SW1 shut-offs, SW2 conductings, i.e. I2 pairs, electric current
Electric capacity is discharged so that V_C is constantly reduced, and when V_C falls below the threshold voltage V_L of low level comparator, exports logic
There is saltus step again, now enter charged state again, so constantly just can on the capacitor export repeatedly and continuously shake
Swing waveform.Cycle of oscillation is determined by electric current I1, I2, electric capacity C and threshold difference V_H-V_L.This traditional structure needs two
Comparator, structure is complex, and area is larger, and consumption power is larger, the common electricity that current source is formed by external bias in addition
Stream source, the stability of electric current is not high.
The content of the invention
The technical problems to be solved by the invention are the defects for overcoming prior art, there is provided a kind of high stability low-power consumption piece
Upper OSC circuits, simple structure, chip occupying area are small, small power consumption, high stability, frequency stabilization, are applied in timing circuit,
With good practical value.
To reach above-mentioned purpose, the present invention provides OSC circuits on a kind of high stability low-power consumption piece, including charge-discharge circuit
With control circuit；The charge-discharge circuit, discharge and recharge, the discharge and recharge of switch controlled electric capacity are carried out to electric capacity by current source；
The control circuit, the level state that the charge-discharge circuit is exported is changed, the output for producing oscillator final
Signal, the oscillator output signal controls the switch of the charge-discharge circuit breaker in middle pipe again；
The charge-discharge circuit includes current source I1, current source I2, NMOS tube M1, PMOS M2, electric capacity C1, electric capacity C2；It is described
The bottom crown of the negative pole of current source I1, the source electrode of the PMOS M2 and the electric capacity C2 is all connected with dc source VDD, the electricity
The positive pole of stream source I1 is connected to the top crown connecting node D1 of node D1, the electric capacity C1 with the drain electrode of the NMOS tube M1,
The positive pole connection ground GND of the bottom crown of the electric capacity C1, the source electrode of the NMOS tube M1 and the current source I2, the PMOS
The grid of M2 is connected to node D3 with the grid of the NMOS tube M1, and the bottom crown of the electric capacity C2 is with the PMOS M2's
Drain electrode is connected to the negative pole connecting node D2 of node D2, the current source I2；
Input connecting node D1, the node D2 of the control circuit, the output end connecting node D3 of the control circuit.
Preferentially, the control circuit includes phase inverter INV1, phase inverter INV2, phase inverter INV3, phase inverter INV4, two
Input nor gate NOR1 and rest-set flip-flop；The input of the phase inverter INV1 connects the node in the charge-discharge circuit
The output end of D1, the phase inverter INV1 connects the S ends of the rest-set flip-flop, the input connecting node of the phase inverter INV2
The output end of D2, the phase inverter INV2 connects the input of the phase inverter INV3, and the output end of the phase inverter INV3 connects
The R ends of the rest-set flip-flop are connect, one of them of the output end Q connections two input nor gates NOR1 of the rest-set flip-flop is defeated
Enter end, another input of the two input nor gates NOR1 connects external signal IN1, the two input nor gates NOR1's
Output end OSC connects the input of the phase inverter INV4, the output end connecting node D3 of the phase inverter INV4.
Preferentially, the current source I1 include PMOS M3, PMOS M4, PMOS M5, PMOS M6, NMOS tube M7 and
NMOS tube M8, the source electrode of the PMOS M3, the source electrode of the PMOS M4 are all connected with dc source VDD, the PMOS M3
The drain electrode connection PMOS M5 source electrode, the grid of the PMOS M3 connects the grid of the PMOS M4, described
The grid of PMOS M3 connects the drain electrode of the PMOS M3, the source of the drain electrode connection PMOS M6 of the PMOS M4
Pole, the grid of the PMOS M5 connects the drain electrode of the PMOS M5, and the drain electrode of the PMOS M5 connects the NMOS tube
The drain electrode of M7, the grid of the PMOS M5 connects the grid of the PMOS M6, drain electrode and the electricity of the PMOS M6
The top crown for holding C1 is connected to the drain electrode connection node D1 of node D1, the NMOS tube M1, the source electrode of the NMOS tube M7
Drain electrode with the NMOS tube M8 is connected, and the source electrode of the NMOS tube M8 is connected to ground GND.
Preferentially, the current source I2 includes NMOS tube M9, NMOS tube M10, NMOS tube M11 and NMOS tube M12, described
The drain electrode of NMOS tube M9 is described with the grid connection that the top crown of the electric capacity C2 is connected to node D2, the NMOS tube M10
The drain electrode of NMOS tube M10, the grid of the drain electrode connection NMOS tube M7 of the NMOS tube M10, the grid of the NMOS tube M10
The grid of the NMOS tube M9 is connected, the source electrode of the NMOS tube M9 is connected with the drain electrode of the NMOS tube M11, the NMOS tube
The grid of M12 connects the drain electrode of the NMOS tube M12, and the drain electrode of the NMOS tube M12 connects the source electrode of the NMOS tube M10,
The grid of the NMOS tube M12 connects the grid of the NMOS tube M11, and the grid of the NMOS tube M12 connects the NMOS tube
The grid of M8, the source electrode of the NMOS tube M11, the source electrode of the NMOS tube M12 are all connected to ground GND.
Preferentially, including NMOS tube M13, the NMOS tube M13 grid connection dc source VDD, the NMOS tube M13
Source electrode and the NMOS tube M13 drain electrode be all connected to ground GND.
Preferentially, current source I1, current source I2 use common-source common-gate current mirror mode image current.
The control method of OSC circuits, comprises the following steps on a kind of high stability low-power consumption piece：
State 0：The external signal IN1 original states input that an input of two input nor gate NOR1 is connect in control circuit
It is 1, the duration is A, then the output OSC of oscillator is 0 during original state；
State 1：Phase inverter INV4 is output as 1, feeds back to the grid of NMOS tube M1 in the charge-discharge circuit, PMOS M2
Grid so that NMOS tube M1 conductings, PMOS M2 shut-offs, then the drain electrode of NMOS tube M1 is that node D1 is low level, PMOS M2
Drain electrode be node D2 be low level, electric capacity C2 is in charged state；Condition adjudgement RS according to now node D1, node D2 is touched
Send out the S inputs of device for 1, R input be 0, by the output end Q after rest-set flip-flop be 0；Two input in the control circuit
The external signal IN1 inputs that one input of nor gate NOR1 is connect are changed into 0, and the duration is B, now the output of oscillator
OSC is 1, and output signal is high level 1, and phase inverter INV4 is output as 0；
State 2：Phase inverter INV4 is output as 0, feeds back to the grid of NMOS tube M1 in the charge-discharge circuit, PMOS M2
Grid so that NMOS tube M1 shut-offs, PMOS M2 conductings, then the drain electrode of PMOS M2 is that node D2 is high level, NMOS tube M1
Drain electrode be node D1 be high level, electric capacity C1 is in charged state；The condition adjudgement RS triggerings of node D1, node D2 when thus
The S inputs of device be 0, R input be 1, by the output end Q after rest-set flip-flop be 1；Because two is defeated in the control circuit
It is 0 to enter the IN1 inputs of nor gate NOR1, then now the output OSC of oscillator is 0, and output signal is changed into low level 0；
State 3：The process of repeat mode 1, state 2.
Preferentially, A, B are respectively the 1/2 of oscillator frequency of oscillation.
The beneficial effect that the present invention is reached：
The invention provides a kind of improved OSC circuits, circuit structure is simple, low in energy consumption, can realize exporting oscillation functions；Institute
State current source and image current is come by common-source common-gate current mirror, therefore electric current I1, I2 stability for producing is high, so that OSC is electric
The frequency of oscillation stabilization on road；The NMOS tube M13 is decoupling capacitor, can be with stabilized supply voltage so that the electric current stabilization of generation,
The frequency of oscillation stability of OSC circuits is improved simultaneously, and noise is low；The present invention eliminates the comparator and control unit in original technology
Point, and phase inverter, two input nor gate and rest-set flip-flops are used, chip occupying area is small.
Brief description of the drawings
Fig. 1 is a kind of traditional oscillators structural representation in the prior art；
Fig. 2 is circuit diagram of the invention；
Fig. 3 is specific implementation example of the invention；
Fig. 4 is the specific implementation example of rest-set flip-flop in the present invention.
Specific embodiment
The invention will be further described below in conjunction with the accompanying drawings.Following examples are only used for clearly illustrating the present invention
Technical scheme, and can not be limited the scope of the invention with this.
The present invention provides OSC circuits on a kind of high stability low-power consumption piece, including charge-discharge circuit and control circuit；
The charge-discharge circuit, discharge and recharge, the discharge and recharge of switch controlled electric capacity are carried out to electric capacity by current source；
The control circuit, the level state that the charge-discharge circuit is exported is changed, the output for producing oscillator final
Signal, the oscillator output signal controls the switch of the charge-discharge circuit breaker in middle pipe again；
The charge-discharge circuit includes current source I1, current source I2, NMOS tube M1, PMOS M2, electric capacity C1, electric capacity C2；It is described
The bottom crown of the negative pole of current source I1, the source electrode of the PMOS M2 and the electric capacity C2 is all connected with dc source VDD, the electricity
The positive pole of stream source I1 is connected to the top crown connecting node D1 of node D1, the electric capacity C1 with the drain electrode of the NMOS tube M1,
The positive pole connection ground GND of the bottom crown of the electric capacity C1, the source electrode of the NMOS tube M1 and the current source I2, the PMOS
The grid of M2 is connected to node D3 with the grid of the NMOS tube M1, and the bottom crown of the electric capacity C2 is with the PMOS M2's
Drain electrode is connected to the negative pole connecting node D2 of node D2, the current source I2；
Input connecting node D1, the node D2 of the control circuit, the output end connecting node D3 of the control circuit.
Further, it is described control circuit include phase inverter INV1, phase inverter INV2, phase inverter INV3, phase inverter INV4,
Two input nor gate NOR1 and rest-set flip-flops；The input of the phase inverter INV1 connects the node in the charge-discharge circuit
The output end of D1, the phase inverter INV1 connects the S ends of the rest-set flip-flop, the input connecting node of the phase inverter INV2
The output end of D2, the phase inverter INV2 connects the input of the phase inverter INV3, and the output end of the phase inverter INV3 connects
The R ends of the rest-set flip-flop are connect, one of them of the output end Q connections two input nor gates NOR1 of the rest-set flip-flop is defeated
Enter end, another input of the two input nor gates NOR1 connects external signal IN1, the two input nor gates NOR1's
Output end OSC connects the input of the phase inverter INV4, the output end connecting node D3 of the phase inverter INV4.
Further, the current source I1 includes PMOS M3, PMOS M4, PMOS M5, PMOS M6, NMOS tube M7
With NMOS tube M8, the source electrode of the PMOS M3, the source electrode of the PMOS M4 are all connected with dc source VDD, the PMOS
The source electrode of the drain electrode connection PMOS M5 of M3, the grid of the PMOS M3 connects the grid of the PMOS M4, described
The grid of PMOS M3 connects the drain electrode of the PMOS M3, the source of the drain electrode connection PMOS M6 of the PMOS M4
Pole, the grid of the PMOS M5 connects the drain electrode of the PMOS M5, and the drain electrode of the PMOS M5 connects the NMOS tube
The drain electrode of M7, the grid of the PMOS M5 connects the grid of the PMOS M6, drain electrode and the electricity of the PMOS M6
The top crown for holding C1 is connected to the drain electrode connection node D1 of node D1, the NMOS tube M1, the source electrode of the NMOS tube M7
Drain electrode with the NMOS tube M8 is connected, and the source electrode of the NMOS tube M8 is connected to ground GND.
Further, the current source I2 includes NMOS tube M9, NMOS tube M10, NMOS tube M11 and NMOS tube M12, described
The drain electrode of NMOS tube M9 is described with the grid connection that the top crown of the electric capacity C2 is connected to node D2, the NMOS tube M10
The drain electrode of NMOS tube M10, the grid of the drain electrode connection NMOS tube M7 of the NMOS tube M10, the grid of the NMOS tube M10
The grid of the NMOS tube M9 is connected, the source electrode of the NMOS tube M9 is connected with the drain electrode of the NMOS tube M11, the NMOS tube
The grid of M12 connects the drain electrode of the NMOS tube M12, and the drain electrode of the NMOS tube M12 connects the source electrode of the NMOS tube M10,
The grid of the NMOS tube M12 connects the grid of the NMOS tube M11, and the grid of the NMOS tube M12 connects the NMOS tube
The grid of M8, the source electrode of the NMOS tube M11, the source electrode of the NMOS tube M12 are all connected to ground GND.
Further, including NMOS tube M13, the NMOS tube M13 grid connection dc source VDD, the NMOS tube
The drain electrode of the source electrode of M13 and the NMOS tube M13 is all connected to ground GND.
Further, current source I1, current source I2 use common-source common-gate current mirror mode image current.
The control method of OSC circuits, comprises the following steps on a kind of high stability low-power consumption piece：
State 0：The external signal IN1 original states input that an input of two input nor gate NOR1 is connect in control circuit
It is 1, the duration is A, then the output OSC of oscillator is 0 during original state；
State 1：Phase inverter INV4 is output as 1, feeds back to the grid of NMOS tube M1 in the charge-discharge circuit, PMOS M2
Grid so that NMOS tube M1 conductings, PMOS M2 shut-offs, then the drain electrode of NMOS tube M1 is that node D1 is low level, PMOS M2
Drain electrode be node D2 be low level, electric capacity C2 is in charged state；Condition adjudgement RS according to now node D1, node D2 is touched
Send out the S inputs of device for 1, R input be 0, by the output end Q after rest-set flip-flop be 0；Two input in the control circuit
The external signal IN1 inputs that one input of nor gate NOR1 is connect are changed into 0, and the duration is B, now the output of oscillator
OSC is 1, and output signal is high level 1, and phase inverter INV4 is output as 0；
State 2：Phase inverter INV4 is output as 0, feeds back to the grid of NMOS tube M1 in the charge-discharge circuit, PMOS M2
Grid so that NMOS tube M1 shut-offs, PMOS M2 conductings, then the drain electrode of PMOS M2 is that node D2 is high level, NMOS tube M1
Drain electrode be node D1 be high level, electric capacity C1 is in charged state；The condition adjudgement RS triggerings of node D1, node D2 when thus
The S inputs of device be 0, R input be 1, by the output end Q after rest-set flip-flop be 1；Because two is defeated in the control circuit
It is 0 to enter the IN1 inputs of nor gate NOR1, then now the output OSC of oscillator is 0, and output signal is changed into low level 0；
State 3：The process of repeat mode 1, state 2.
Further, A, B are respectively the 1/2 of oscillator frequency of oscillation.
The relation of four kinds of inputs with the output of rest-set flip-flop：
1. when R ends effectively (0), when S ends are invalid (1), then Q=0, Q '=1, trigger reset；
2. when R ends invalid (1), S ends are effective (0), then Q=1, Q '=0, trigger puts 1.
Output signal switches in just flat, low level repeatedly, and frequency of oscillation is determined by the size of current source, electric capacity C1, C2
It is fixed.
OSC circuit structures are more multiple during OSC circuits overcome existing conventional art on high stability low-power consumption piece of the invention
The problem that miscellaneous, area is larger, power consumption is larger, stability is poor, simple structure of the present invention, chip occupying area are small, small power consumption, Gao Wen
Qualitative, frequency stabilization, is applied in timing circuit, with good practical value.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, on the premise of the technology of the present invention principle is not departed from, some improvement and deformation can also be made, these improve and deform
Also should be regarded as protection scope of the present invention.
Claims (8)
1. OSC circuits on a kind of high stability low-power consumption piece, it is characterised in that including charge-discharge circuit and control circuit；
The charge-discharge circuit, discharge and recharge, the discharge and recharge of switch controlled electric capacity are carried out to electric capacity by current source；
The control circuit, the level state that the charge-discharge circuit is exported is changed, the output for producing oscillator final
Signal, the oscillator output signal controls the switch of the charge-discharge circuit breaker in middle pipe again；
The charge-discharge circuit includes current source I1, current source I2, NMOS tube M1, PMOS M2, electric capacity C1, electric capacity C2；It is described
The bottom crown of the negative pole of current source I1, the source electrode of the PMOS M2 and the electric capacity C2 is all connected with dc source VDD, the electricity
The positive pole of stream source I1 is connected to the top crown connecting node D1 of node D1, the electric capacity C1 with the drain electrode of the NMOS tube M1,
The positive pole connection ground GND of the bottom crown of the electric capacity C1, the source electrode of the NMOS tube M1 and the current source I2, the PMOS
The grid of M2 is connected to node D3 with the grid of the NMOS tube M1, and the bottom crown of the electric capacity C2 is with the PMOS M2's
Drain electrode is connected to the negative pole connecting node D2 of node D2, the current source I2；
Input connecting node D1, the node D2 of the control circuit, the output end connecting node D3 of the control circuit.
2. OSC circuits on a kind of high stability low-power consumption piece according to claim 1, it is characterised in that the control electricity
Road includes phase inverter INV1, phase inverter INV2, phase inverter INV3, phase inverter INV4, two input nor gate NOR1 and RS triggerings
Device；The input of the phase inverter INV1 connects the node D1 in the charge-discharge circuit, the output end of the phase inverter INV1
Connect the S ends of the rest-set flip-flop, the input connecting node D2 of the phase inverter INV2, the output end of the phase inverter INV2
The input of the phase inverter INV3 is connected, the output end of the phase inverter INV3 connects the R ends of the rest-set flip-flop, the RS
One of input of the output end Q connections two input nor gates NOR1 of trigger, the two input nor gates NOR1
The connection of another input external signal IN1, the output end OSC of the two input nor gates NOR1 connect the phase inverter
The input of INV4, the output end connecting node D3 of the phase inverter INV4.
3. OSC circuits on a kind of high stability low-power consumption piece according to claim 1, it is characterised in that the current source
I1 includes PMOS M3, PMOS M4, PMOS M5, PMOS M6, NMOS tube M7 and NMOS tube M8, the source of the PMOS M3
Pole, the source electrode of the PMOS M4 are all connected with the source of the drain electrode connection PMOS M5 of dc source VDD, the PMOS M3
Pole, the grid of the PMOS M3 connects the grid of the PMOS M4, and the grid of the PMOS M3 connects the PMOS
The drain electrode of M3, the source electrode of the drain electrode connection PMOS M6 of the PMOS M4, the grid connection of the PMOS M5 is described
The drain electrode of PMOS M5, the drain electrode of the drain electrode connection NMOS tube M7 of the PMOS M5, the grid of the PMOS M5 connects
Connect the grid of the PMOS M6, the drain electrode of the PMOS M6 and the top crown of the electric capacity C1 are connected to node D1, described
The drain electrode of NMOS tube M1 connects the node D1, and the source electrode of the NMOS tube M7 is connected with the drain electrode of the NMOS tube M8, described
The source electrode of NMOS tube M8 is connected to ground GND.
4. OSC circuits on a kind of high stability low-power consumption piece according to claim 3, it is characterised in that the current source
I2 includes NMOS tube M9, NMOS tube M10, NMOS tube M11 and NMOS tube M12, the drain electrode of the NMOS tube M9 and the electric capacity C2
Top crown be connected to the grid of node D2, the NMOS tube M10 and connect the drain electrode of the NMOS tube M10, the NMOS tube M10
The drain electrode connection NMOS tube M7 grid, the grid of the NMOS tube M10 connects the grid of the NMOS tube M9, described
The source electrode of NMOS tube M9 is connected with the drain electrode of the NMOS tube M11, and the grid of the NMOS tube M12 connects the NMOS tube M12
Drain electrode, the source electrode of the drain electrode connection NMOS tube M10 of the NMOS tube M12, the grid connection of the NMOS tube M12 is described
The grid of NMOS tube M11, the grid of the NMOS tube M12 connects the grid of the NMOS tube M8, the source of the NMOS tube M11
Pole, the source electrode of the NMOS tube M12 are all connected to ground GND.
5. OSC circuits on a kind of high stability low-power consumption piece according to claim 1, it is characterised in that including NMOS tube
The grid connection dc source VDD of M13, the NMOS tube M13, the leakage of the source electrode of the NMOS tube M13 and the NMOS tube M13
Pole is all connected to ground GND.
6. OSC circuits on a kind of high stability low-power consumption piece according to claim 4, it is characterised in that current source I1, electricity
Stream source I2 uses common-source common-gate current mirror mode image current.
7. on a kind of high stability low-power consumption piece OSC circuits control method, it is characterised in that comprise the following steps：
State 0：The external signal IN1 original states input that an input of two input nor gate NOR1 is connect in control circuit
It is 1, the duration is A, then the output OSC of oscillator is 0 during original state；
State 1：Phase inverter INV4 is output as 1, feeds back to the grid of NMOS tube M1 in the charge-discharge circuit, PMOS M2
Grid so that NMOS tube M1 conductings, PMOS M2 shut-offs, then the drain electrode of NMOS tube M1 is that node D1 is low level, PMOS M2
Drain electrode be node D2 be low level, electric capacity C2 is in charged state；Condition adjudgement RS according to now node D1, node D2 is touched
Send out the S inputs of device for 1, R input be 0, by the output end Q after rest-set flip-flop be 0；Two input in the control circuit
The external signal IN1 inputs that one input of nor gate NOR1 is connect are changed into 0, and the duration is B, now the output of oscillator
OSC is 1, and output signal is high level 1, and phase inverter INV4 is output as 0；
State 2：Phase inverter INV4 is output as 0, feeds back to the grid of NMOS tube M1 in the charge-discharge circuit, PMOS M2
Grid so that NMOS tube M1 shut-offs, PMOS M2 conductings, then the drain electrode of PMOS M2 is that node D2 is high level, NMOS tube M1
Drain electrode be node D1 be high level, electric capacity C1 is in charged state；The condition adjudgement RS triggerings of node D1, node D2 when thus
The S inputs of device be 0, R input be 1, by the output end Q after rest-set flip-flop be 1；Because two is defeated in the control circuit
It is 0 to enter the IN1 inputs of nor gate NOR1, then now the output OSC of oscillator is 0, and output signal is changed into low level 0；
State 3：The process of repeat mode 1, state 2.
8. on a kind of high stability low-power consumption piece according to claim 7 OSC circuits control method, it is characterised in that
A, B are respectively the 1/2 of oscillator frequency of oscillation.
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| CN107889350A (en) * | 2017-12-22 | 2018-04-06 | 珠海快捷中祺电子科技有限公司 | Multilayer circuit board |
| CN108681772A (en) * | 2018-04-02 | 2018-10-19 | 北京大学 | Multi-modal neuron circuit and neuron implementation method |
| CN109672408A (en) * | 2018-11-22 | 2019-04-23 | 合肥市芯海电子科技有限公司 | A kind of programmable crystal-oscillator circuit of low-power consumption fast start-up |
| CN110350887A (en) * | 2018-04-08 | 2019-10-18 | 中芯国际集成电路制造(上海)有限公司 | The production method of RC oscillator circuit and clock signal |
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| CN113852352A (en) * | 2021-09-30 | 2021-12-28 | 中国电子科技集团公司第五十八研究所 | Low-power-consumption wide-voltage-range oscillator |
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| CN110350887B (en) * | 2018-04-08 | 2023-03-28 | 中芯国际集成电路制造(上海)有限公司 | Resistance-capacitance oscillator circuit and clock signal generating method |
| CN109672408B (en) * | 2018-11-22 | 2023-02-03 | 合肥市芯海电子科技有限公司 | Low-power-consumption programmable crystal oscillator circuit capable of starting oscillation quickly |
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| CN112583355B (en) * | 2020-12-15 | 2022-12-27 | 思瑞浦微电子科技（苏州）股份有限公司 | High-precision relaxation oscillator |
| CN112583355A (en) * | 2020-12-15 | 2021-03-30 | 思瑞浦微电子科技（苏州）股份有限公司 | High-precision relaxation oscillator |
| CN113852352A (en) * | 2021-09-30 | 2021-12-28 | 中国电子科技集团公司第五十八研究所 | Low-power-consumption wide-voltage-range oscillator |
| CN114132886A (en) * | 2021-11-30 | 2022-03-04 | 江苏普诺威电子股份有限公司 | Five-layer embedded-capacitor MEMS (micro-electromechanical systems) packaging carrier plate with high hole-filling ratio and manufacturing process thereof |
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