CN106847145A - Array base palte test circuit and array base palte - Google Patents
Array base palte test circuit and array base palte Download PDFInfo
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- CN106847145A CN106847145A CN201710241348.3A CN201710241348A CN106847145A CN 106847145 A CN106847145 A CN 106847145A CN 201710241348 A CN201710241348 A CN 201710241348A CN 106847145 A CN106847145 A CN 106847145A
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- switch
- source signal
- array base
- base palte
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The embodiment of the present invention provides a kind of array base palte test circuit, including test cell and multiple switch control units, the test cell includes source signal source, multiple first switch units and multiple sub-pixels corresponding with the multiple first switch unit one-to-one corresponding, each described sub-pixel is connected to the source signal source through first switch unit described in, arranged in the first direction with the multiple switch control unit in the source signal source, the multiple switch control unit, the multiple first switch unit is corresponded, the switch control unit controls corresponding first switch unit conducting, to cause that source signal is transmitted to the corresponding sub-pixel.The arrangement of the test circuit can make full use of the space of the length direction of array base palte, such that it is able to save, so that the test circuit is adapted to the design requirement of narrow frame array base palte.
Description
Technical field
The present invention relates to test equipment field, more particularly to a kind of array base palte test circuit and array base palte.
Background technology
With continuing to develop for LCD (Liquid Crystal Display, liquid crystal display) Display Techniques, LTPS (Low
Temperature Poly-silicon, low-temperature polysilicon silicon technology) process faceplate is considered as whole world high-end applications market at present
One of main flow Display Technique most with prospects.But because the array process complexity in LTPS process faceplates causes product yield not
Height, shipment demand gap is big.And array test (Array Tester, abridge ATS) is checked and can monitor LTPS processing procedures, feedback is produced
Line, reaches the purpose for improving constantly yield.So big fecund all can carry out ATS inspections to product.
ATS is mainly entered in checking using full pin probe (Full-Pin Contact Probing) mode in the prior art
OK.Fig. 1 is referred to, test circuit mainly includes sub-pixel 31, source signal source 32, the and of ON-OFF control circuit 33 in the prior art
Switch 34.The conducting of the controlling switch 34 of ON-OFF control circuit 33, so that control source signal to reach sub-pixel 31, so as to be surveyed
Examination.This ATS test circuits the disadvantage is that, need take panel frame space, product design framework can be influenceed.It is especially right
It is smaller in the frame of narrow frame product, therefore the test circuit required for test cannot be placed, cause what processing procedure cannot monitor to show
As.
The content of the invention
It is an object of the invention to provide array base palte test circuit, the arrangement of the test circuit can make full use of array
The space of the length direction of substrate, so that the test circuit is adapted to the design requirement of narrow frame array base palte.
Another object of the present invention is to provide using the array base palte of above-mentioned test circuit.
To achieve these goals, embodiment of the present invention provides following technical scheme：
The present invention provides a kind of array base palte test circuit, including test cell and multiple switch control units, the survey
Examination unit includes source signal source, multiple first switch unit and corresponding many with the multiple first switch unit one-to-one corresponding
Individual sub-pixel, each described sub-pixel is connected to the source signal source, the source signal through first switch unit described in
Source is arranged in the first direction with the multiple switch control unit, the multiple switch control unit, the multiple first switch
Unit is corresponded, and the switch control unit controls corresponding first switch unit conducting, with cause source signal transmit to
The corresponding sub-pixel.
Wherein, the quantity of the test cell is multiple, the multiple switch control unit and each test cell
In multiple first switch units correspond, the switch control unit controls corresponding first switch in each test cell
Unit is turned on, to cause that the source signal in each test cell is transmitted to corresponding sub-pixel.
Wherein, the multiple source signal sources in the multiple test cell are arranged successively along the first direction.
Wherein, the multiple switch control unit is uniformly distributed in the multiple source signal source.
Wherein, the array base palte test circuit also includes on-off circuit, and the test cell also includes second switch list
Unit, the second switch unit is connected between the source signal source and the first switch unit, the on-off circuit control
The conducting of the second switch unit is made, to cause that source signal is transmitted to the first switch unit.
The present invention also provides a kind of array base palte, including test circuit, and the test circuit includes test cell and multiple
Switch control unit, the test cell includes source signal source, multiple first switch unit and multiple sub-pixels, described in each
Sub-pixel is connected to the source signal source, the source signal source and the multiple switching control through first switch unit described in
Unit processed is arranged in the first direction, the multiple switch control unit, the multiple first switch unit and the multiple sub- picture
Plain electrode is corresponded, and the switch control unit controls corresponding first switch unit conducting, to cause that source signal is transmitted
To the corresponding sub-pixel.
Wherein, the quantity of the test cell is multiple, the multiple switch control unit and each test cell
In multiple first switch units correspond, the switch control unit controls corresponding first switch in each test cell
Unit is turned on, to cause that the source signal in each test cell is transmitted to corresponding sub-pixel.
Wherein, the multiple source signal sources in the multiple test cell are arranged successively along the first direction.
Wherein, the multiple switch control unit is uniformly distributed in the multiple source signal source.
Wherein, the array base palte test circuit also includes on-off circuit, and the test cell also includes second switch list
Unit, the second switch unit is connected between the source signal source and the first switch unit, the on-off circuit control
The conducting of the second switch unit is made, to cause that source signal is transmitted to the first switch unit.
The embodiment of the present invention has the following advantages that or beneficial effect：
In embodiments of the invention, source signal source S, the first switch unit (Q1-Qn) and the sub-pixel are successively
Connection, the source signal source S arranges in the first direction with the multiple switch control unit (sw1-swn), the multiple to cut
Change a pair of control unit (sw1-swn), the multiple first switch unit (Q1-Qn) and the multiple pixel electrode 21 1
Should, the test to sub-pixel is realized, the arrangement of the test circuit can make full use of the length direction in Array Test regions 11
Space, such that it is able to save the space of the width of Array Test regions 11, so that the test circuit is adapted to narrow side
The design requirement of frame array base palte.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is prior art array base palte test circuit structure schematic diagram.
Fig. 2 is array base-plate structure schematic diagram of the present invention.
Fig. 3 is a kind of structural representation of the test circuit in the array base palte described in Fig. 2.
Fig. 4 is another structural representation of the test circuit in the array base palte described in Fig. 2.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.Base
Embodiment in the present invention, it is all that those of ordinary skill in the art are obtained on the premise of creative work is not made
Other embodiments, belong to the scope of protection of the invention.
Additionally, the explanation of following embodiment is with reference to additional diagram, it is used to illustrate the spy that the present invention may be used to implement
Determine embodiment.The direction term being previously mentioned in the present invention, for example, " on ", D score, "front", "rear", "left", "right", " interior ",
" outward ", " side " etc., is only the direction with reference to annexed drawings, therefore, the direction term for using is to more preferably, more clearly say
The bright and understanding present invention, must be with specific orientation, with specific square rather than the device or element for indicating or infer meaning
Position construction and operation, therefore be not considered as limiting the invention.
In the description of the invention, it is necessary to illustrate, unless otherwise clearly defined and limited, term " installation ", " phase
Company ", " connection " should be interpreted broadly, for example, it may be being fixedly connected, or detachably connected, or integratedly connect
Connect；Can mechanically connect；Can be joined directly together, it is also possible to be indirectly connected to by intermediary, can be in two elements
The connection in portion.For the ordinary skill in the art, above-mentioned term tool in the present invention can be understood with concrete condition
Body implication.
Additionally, in the description of the invention, unless otherwise indicated, " multiple " is meant that two or more.If this
Occur the term of " operation " in specification, it refers not only to independent operation, when cannot clearly be distinguished with other operations, as long as
Can realize that the effect desired by the operation is then also included within this term.In addition, the numerical value model represented with "~" in this specification
Enclose the scope that the numerical value for referring to record before and after "~" is included as minimum value and maximum.In the accompanying drawings, structure
Similar or identical is indicated by the same numeral.
Refer to Fig. 2.Fig. 2 is array base-plate structure schematic diagram of the invention.Array base palte of the invention includes：Test electricity
Road region 11 (namely Array Test regions), viewing area 12 (AA areas), GOA (Gate On Array) region 13, multichannel are multiple
With selection (Demux) region 14, it is fanned out to (Fanout) region 15, WOA (Wire On Array) region 16, driving chip (IC)
Region 17, flexible connector (FPC) region 18.Wherein, Array Test regions 11 are used for complete in array (Array) substrate manufacture
After, to electrically testing for Array substrates, array base palte test circuit of the invention is all located in addition to sub-pixel
Array Test regions 11；AA areas 12 include multiple pixel cells, and each pixel cell includes red sub-pixel, blue sub- picture
Element, green sub-pixels, AA areas are used for the display of pixel；GOA regions 13, the raster data model for producing the TFT in viewing area
Signal；Fanout regions 15, for the cabling connection between the data wire for realizing IC and AA areas；Demux regions 14, for will be from
The output end that IC sides are drawn is split, to realize the driving of a plurality of Dataline；WOA regions 16, for cabling around panel
Connection；IC regions 17, for the bonding (Bonding) of IC, the driving chip is used to provide the data-signal in AA regions；FPC
Region 18, for the Bonding of FPC, circuit board is connected by FPC.Wherein test circuit region 11 is by connecting line and IC areas
Domain 17 is connected, and test control signal (ATEN) is provided with to test circuit, specifically, when test circuit works, testing and control
Signal is high level, when test circuit test complete after, test control signal is low level, also will test circuit close,
Preventing test circuit from being shown for AA areas influences.
Please refer to Fig. 3.Fig. 3 is a kind of structural representation of the test circuit in the array base palte described in Fig. 2.This hair
Bright array base palte test circuit includes test cell 20 and multiple switch control units (i.e. sw1-swn in Fig. 3).Specifically
, the test cell 20 includes source signal source S, multiple first switches unit (i.e. Q1-Qn in Fig. 2) and multiple sub-pixels
21.Each described sub-pixel 21 is connected to the source signal source S, the source signal source S through first switch unit described in
Source signal needed for for providing test.The source signal source S, the first switch unit (Q1-Qn) and the sub- picture
Plain 21 trend (Y-direction i.e. in Fig. 1 and Fig. 2) substantially in a second direction is sequentially connected.It is understood that the second party
To the width in substantially described Array Test regions 11.The source signal source S and the multiple switch control unit
(Q1-Qn) (X-direction i.e. in Fig. 1 and Fig. 2) arrangement in the first direction.It is understood that the first direction substantially institute
State the length direction in Array Test regions 11.The multiple switch control unit (sw1-swn), the multiple first switch list
First (Q1-Qn) and the multiple pixel electrode 21 are corresponded, and each switch control unit controls a first switch unit
Be turned on or off so that whether the signal for controlling source electrode signal source S to send reaches corresponding sub-pixel, complete the survey of sub-pixel
Examination process.
It is understood that in other embodiments, the first direction X can also for other not with second direction Y
Parallel direction.
It is understood that above n can be 1,2,3,4,5 ...
In present embodiment, source signal source S, the first switch unit (Q1-Qn) and the sub-pixel 21 approximately along
Second direction trend is sequentially connected；The source signal source S is with the multiple switch control unit (sw1-swn) in the first direction
(X-direction i.e. in Fig. 1 and Fig. 2) arranges, the multiple switch control unit (sw1-swn), the multiple first switch unit
(Q1-Qn) test to sub-pixel and the multiple pixel electrode 21 is corresponded, is realized, the arrangement of the test circuit can be with
The space of the length direction in Array Test regions 11 is made full use of, the width of Array Test regions 11 is taken such that it is able to reduce
The space in direction, so that the test circuit is adapted to the design requirement of narrow frame array base palte.
Refer to Fig. 4.Fig. 4 is another structural representation of the test circuit in the array base palte described in Fig. 2.In this reality
Apply in mode, the quantity of the test cell 20 is multiple.It is understood that test cell 20 in present embodiment and cutting
Change control unit roughly the same with the test cell structure of a upper implementation method, here is omitted.It should be noted that this reality
Apply and represent for convenience in mode, each test cell includes 6 first switch units (i.e. Q1-Q6) and 6 sub-pixels.Phase
Answer, in present embodiment, the quantity of switch control unit is also 6 (i.e. sw1-sw6).In other embodiments, first
The quantity of switch element and sub-pixel can also be 1,2,3,4,5,7,8,9 ... herein not to be limited.
In present embodiment, switch control unit sw1 controls the state of first switch unit Q1 in each test cell 20
(ON/OFF), that is to say, that control unit sw1 controls the state of multiple first switch unit Q1 simultaneously；Switch control unit
Sw2 controls the state (ON/OFF) of first switch unit Q2 in each test cell 20, that is to say, that switch control unit
Sw1 controls the state of multiple first switch unit Q1 simultaneously；The rest may be inferred, and switch control unit sw6 controls each test cell
The state (ON/OFF) of first switch unit Q6 in 20.In other words, the multiple switch control unit and each survey
Multiple first switch units in examination unit 20 are corresponded, and the switch control unit controls correspondence in each test cell 20
First switch unit conducting, with cause each test cell in source signal transmit to corresponding sub-pixel.
In a kind of possible implementation of the present invention, the X arrangements in the first direction of the multiple test cell 20, so as to reduce
The space of the width (and second direction Y) of Array Test regions 11 that test circuit takes.Preferably, the multiple source electrode
Signal source S arranges successively along the first direction X.
It is understood that the multiple test cell 20 and the multiple switch control unit are along the first direction
X arranges.Preferably, the multiple switch control unit is uniformly distributed in the multiple source signal source S.As a rule, exist
In array base palte test circuit, the quantity of the quantity much larger than switch control unit of test cell 20.Therefore, it can cut multiple
Control unit is changed to be uniformly distributed between multiple test cells 20.Specifically, multiple test cells 20 can be along the first party
Arranged successively in straight line to X.In other words, the multiple source signal source S is linear along first direction arrangement, institute
State multiple switch control units to be interspersed in the straight line that multiple source signal source S are formed, between two neighboring switch control unit
It is spaced the test cell 20 (source signal source S) of equal number.The interspersed multiple that is arranged at of multiple switch control units is tested single
Between unit 20 so that the line between switch control unit and first switch unit can intert the cabling for being distributed in source signal source
In so that wiring is compacter, reduces the occupancy to the space of Array Test regions 11, the particularly space of width.
It is to cause switching as far as possible additionally, the multiple switch control unit is uniformly distributed in the multiple source signal source S
Control unit is roughly the same with the average distance of test cell 20, it is to avoid multiple switch control unit concentrations, causes part
The switching signal time delay that the test cell of position is received, influences the accuracy of test result.
In a kind of possible implementation of the present invention, the array base palte test circuit also includes that on-off circuit is (not shown
Go out), the test cell also includes second switch unit 22, and the second switch unit 22 is connected to the source signal source S
And the first switch unit between, the on-off circuit controls the conducting of the second switch unit 22, to cause that source electrode is believed
Number transmit to the first switch unit.So as to control the break-make of source signal.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means to combine specific features, structure, material or feature that the embodiment or example are described
It is contained at least one embodiment of the invention or example.In this manual, the schematic representation to above-mentioned term differs
Surely identical embodiment or example are referred to.And, the specific features of description, structure, material or feature can be any one
Combined in an appropriate manner in individual or multiple embodiments or example.
Embodiments described above, does not constitute the restriction to the technical scheme protection domain.It is any in above-mentioned implementation
Modification, equivalent and improvement made within the spirit and principle of mode etc., should be included in the protection model of the technical scheme
Within enclosing.
Claims (10)
1. a kind of array base palte test circuit, it is characterised in that including test cell and multiple switch control units, the test
Unit include source signal source, multiple first switch unit and with the corresponding multiple of the multiple first switch unit one-to-one corresponding
Sub-pixel, each described sub-pixel is connected to the source signal source, the source signal source through first switch unit described in
Arranged in the first direction with the multiple switch control unit, the multiple switch control unit, the multiple first switch list
Unit corresponds, and the switch control unit controls corresponding first switch unit conducting, to cause that source signal is transmitted to right
The sub-pixel answered.
2. array base palte test circuit as claimed in claim 1, it is characterised in that the quantity of the test cell is multiple,
The multiple switch control unit is corresponded with the multiple first switch units in each test cell, the switching control
Unit processed controls corresponding first switch unit conducting in each test cell, to cause the source signal in each test cell
Transmit to corresponding sub-pixel.
3. array base palte test circuit as claimed in claim 2, it is characterised in that the multiple sources in the multiple test cell
Pole signal source is arranged successively along the first direction.
4. array base palte test circuit as claimed in claim 3, it is characterised in that the multiple switch control unit uniformly divides
It is distributed in the multiple source signal source.
5. array base palte test circuit as claimed in claim 3, it is characterised in that the array base palte test circuit also includes
On-off circuit, the test cell also includes second switch unit, and the second switch unit is connected to the source signal source
And the first switch unit between, the on-off circuit controls the conducting of the second switch unit, to cause source signal
Transmit to the first switch unit.
6. a kind of array base palte, it is characterised in that including test circuit, the test circuit includes test cell and multiple switches
Control unit, the test cell includes source signal source, multiple first switch units and multiple sub-pixels, each described sub- picture
Element is connected to the source signal source, the source signal source and the multiple switching control list through first switch unit described in
Unit arranges in the first direction, the multiple switch control unit, the multiple first switch unit and the multiple sub-pixel electricity
Pole corresponds, and the switch control unit controls corresponding first switch unit conducting, to cause that source signal is transmitted to right
The sub-pixel answered.
7. array base palte as claimed in claim 6, it is characterised in that the quantity of the test cell is multiple, the multiple
Switch control unit is corresponded with the multiple first switch units in each test cell, the switch control unit control
Corresponding first switch unit conducting in each test cell is made, to cause that the source signal in each test cell is transmitted to right
The sub-pixel answered.
8. array base palte as claimed in claim 7, it is characterised in that the multiple source signal sources in the multiple test cell
Arranged successively along the first direction.
9. array base palte as claimed in claim 8, it is characterised in that the multiple switch control unit is uniformly distributed in described
In multiple source signal sources.
10. array base palte as claimed in claim 9, it is characterised in that the array base palte test circuit also includes switch electricity
Road, the test cell also includes second switch unit, and the second switch unit is connected to the source signal source and described
Between first switch unit, the on-off circuit controls the conducting of the second switch unit, with cause source signal transmit to
The first switch unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710241348.3A CN106847145B (en) | 2017-04-13 | 2017-04-13 | Array substrate test circuit and array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710241348.3A CN106847145B (en) | 2017-04-13 | 2017-04-13 | Array substrate test circuit and array substrate |
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| CN106847145A true CN106847145A (en) | 2017-06-13 |
| CN106847145B CN106847145B (en) | 2020-10-09 |
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| CN201710241348.3A Active CN106847145B (en) | 2017-04-13 | 2017-04-13 | Array substrate test circuit and array substrate |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107578735A (en) * | 2017-10-31 | 2018-01-12 | 武汉华星光电技术有限公司 | A kind of array base palte, method of testing and display device |
| CN107680521A (en) * | 2017-09-28 | 2018-02-09 | 武汉华星光电技术有限公司 | Detection circuit and display device based on array base palte |
| CN107784968A (en) * | 2017-11-06 | 2018-03-09 | 武汉华星光电技术有限公司 | Carry on the back optical detection circuit and Related product |
| CN109491154A (en) * | 2018-12-29 | 2019-03-19 | 厦门天马微电子有限公司 | Display panel, display device and its manufacturing method |
| US20190130802A1 (en) * | 2017-10-31 | 2019-05-02 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Array substrate, testing method and display apparatus |
| US10782335B2 (en) | 2017-11-06 | 2020-09-22 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Backlight test circuit, backlight test method and backlight module using the same |
| CN113658540A (en) * | 2021-08-24 | 2021-11-16 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| CN113763848A (en) * | 2020-06-04 | 2021-12-07 | 群创光电股份有限公司 | Display panel |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007140378A (en) * | 2005-11-22 | 2007-06-07 | Toshiba Matsushita Display Technology Co Ltd | Display apparatus |
| CN101191910A (en) * | 2006-11-30 | 2008-06-04 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and testing method thereof |
| CN105185332A (en) * | 2015-09-08 | 2015-12-23 | 深圳市华星光电技术有限公司 | Liquid crystal display panel, driving circuit thereof and manufacturing method thereof |
| CN105427775A (en) * | 2015-12-30 | 2016-03-23 | 厦门天马微电子有限公司 | Display panel and electronic device |
| CN106200161A (en) * | 2016-07-13 | 2016-12-07 | 深圳市华星光电技术有限公司 | Display panels periphery design circuit and use the display panels of this circuit |
| CN106291999A (en) * | 2015-06-24 | 2017-01-04 | 乐金显示有限公司 | Display device and the method for test display apparatus |
-
2017
- 2017-04-13 CN CN201710241348.3A patent/CN106847145B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007140378A (en) * | 2005-11-22 | 2007-06-07 | Toshiba Matsushita Display Technology Co Ltd | Display apparatus |
| CN101191910A (en) * | 2006-11-30 | 2008-06-04 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and testing method thereof |
| CN106291999A (en) * | 2015-06-24 | 2017-01-04 | 乐金显示有限公司 | Display device and the method for test display apparatus |
| CN105185332A (en) * | 2015-09-08 | 2015-12-23 | 深圳市华星光电技术有限公司 | Liquid crystal display panel, driving circuit thereof and manufacturing method thereof |
| CN105427775A (en) * | 2015-12-30 | 2016-03-23 | 厦门天马微电子有限公司 | Display panel and electronic device |
| CN106200161A (en) * | 2016-07-13 | 2016-12-07 | 深圳市华星光电技术有限公司 | Display panels periphery design circuit and use the display panels of this circuit |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107680521A (en) * | 2017-09-28 | 2018-02-09 | 武汉华星光电技术有限公司 | Detection circuit and display device based on array base palte |
| CN107578735A (en) * | 2017-10-31 | 2018-01-12 | 武汉华星光电技术有限公司 | A kind of array base palte, method of testing and display device |
| US20190130802A1 (en) * | 2017-10-31 | 2019-05-02 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Array substrate, testing method and display apparatus |
| US10777107B2 (en) | 2017-10-31 | 2020-09-15 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Array substrate, testing method and display apparatus |
| CN107784968A (en) * | 2017-11-06 | 2018-03-09 | 武汉华星光电技术有限公司 | Carry on the back optical detection circuit and Related product |
| US10782335B2 (en) | 2017-11-06 | 2020-09-22 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Backlight test circuit, backlight test method and backlight module using the same |
| CN109491154A (en) * | 2018-12-29 | 2019-03-19 | 厦门天马微电子有限公司 | Display panel, display device and its manufacturing method |
| CN113763848A (en) * | 2020-06-04 | 2021-12-07 | 群创光电股份有限公司 | Display panel |
| CN113658540A (en) * | 2021-08-24 | 2021-11-16 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
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| CN106847145B (en) | 2020-10-09 |
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