CN106783743A - Storage arrangement and its manufacture method - Google Patents
Storage arrangement and its manufacture method Download PDFInfo
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- CN106783743A CN106783743A CN201510814717.4A CN201510814717A CN106783743A CN 106783743 A CN106783743 A CN 106783743A CN 201510814717 A CN201510814717 A CN 201510814717A CN 106783743 A CN106783743 A CN 106783743A
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- Prior art keywords
- insulating barrier
- wordline
- drain region
- storage arrangement
- substrate
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- 238000000034 method Methods 0.000 title claims abstract description 75
- 238000003860 storage Methods 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 230000004888 barrier function Effects 0.000 claims abstract description 87
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 238000002955 isolation Methods 0.000 claims abstract description 45
- 239000010410 layer Substances 0.000 claims description 52
- 239000000463 material Substances 0.000 claims description 20
- 239000011241 protective layer Substances 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000004528 spin coating Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004062 sedimentation Methods 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- -1 tungsten nitride Chemical class 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- 239000010948 rhodium Substances 0.000 description 1
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
- H10B12/377—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate having a storage electrode extension located over the transistor
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention provides a kind of storage arrangement and its manufacture method.The storage arrangement, including：Substrate, includes with isolation channel and two active regions, and each active region：First wordline, the second wordline, source area, the first drain region and the second drain region.Storage arrangement further includes the first insulating barrier, partly inserts isolation channel；Second insulating barrier, on the first wordline and the second wordline；And conductive layer, on the first drain region, on the second drain region and isolation channel not by the first insulating barrier cover side wall on.The present invention also provides the manufacture method of this storage arrangement.By implementing the present invention, technique allowance and technique yields can be increased.
Description
Technical field
The invention relates to storage arrangement and its manufacture method, and inserted with drain contact in particular to one kind
The storage arrangement and its manufacture method of plug.
Background technology
For the stacked elements density increased in dynamic random access memory (DRAM) and improve its general performance,
Currently manufactured technology is continued towards the electric capacity reduced in dynamic random access memory and diminution dynamic random access memory
The size of device and effort.However as the size reduction of dynamic random access memory, technique allowance can be produced not enough
And the problem that technique yields declines.Therefore, industry needs one kind can further to reduce the size, and can increase technique
The storage arrangement and its manufacture method of allowance and technique yields.
The content of the invention
The present invention provides a kind of storage arrangement, including：Substrate, with isolation channel and two active regions, two of which
Active region is separated by isolation channel, and each active region includes：First wordline and the second wordline, in substrate；
Source area, in the substrate between the first wordline and the second wordline；First drain region, wherein the first drain region and source
Polar region is respectively arranged in the substrate of the opposition side of the first wordline；And second drain region, wherein the second drain region and source electrode
Area is respectively arranged in the substrate of the opposition side of the second wordline；First insulating barrier, partly inserts isolation channel；Second insulation
Layer, on the first wordline and the second wordline；And conductive layer, on the first drain region, the second drain region
On the side wall that upper and isolation channel is not covered by the first insulating barrier.
The present invention more provides a kind of manufacture method of storage arrangement, including：Substrate is provided, with isolation channel and two
Active region, two of which active region is separated by isolation channel；Form the first insulating barrier and insert isolation channel, each of which
Active region includes；First wordline and the second wordline, in substrate；Source area, located at the first wordline and the second word
In substrate between line；First drain region, wherein the first drain region and source area are be respectively arranged on the first wordline opposite
In the substrate of side；And second drain region, wherein the second drain region and source area are the opposition sides for being respectively arranged on the second wordline
Substrate in, wherein the first insulating barrier covering source area, the first drain region and the second drain region；Form the second insulating barrier
On the first wordline and the second wordline；Mask layer is formed, the first wordline, the second wordline and source area is covered, and
Expose on the first drain region, on the second drain region and located at the first insulating barrier of isolation channel；Remove located at the first leakage
The first insulating barrier on polar region and on the second drain region, and first insulating barrier of the part located at isolation channel is removed, to expose
The side wall that first drain region, the second drain region and isolation channel are not covered by the first insulating barrier；And formed conductive layer in
On first drain region, on the second drain region and isolation channel not by the first insulating barrier cover side wall on.
By implementing the present invention, technique allowance and technique yields can be increased.
Be that feature of the invention and advantage can be become apparent, it is cited below particularly go out preferred embodiment, and coordinate appended
Schema, is described in detail below.
Brief description of the drawings
Figure 1A-Figure 1B is the manufacture method wherein of the storage arrangement for showing described according to some embodiments of the invention
The profile and top view of the storage arrangement of step.
Fig. 2 is a manufacture method wherein step of the storage arrangement for showing described according to some embodiments of the invention
The profile of storage arrangement.
Fig. 3 A- Fig. 3 B are the manufacture methods wherein of the storage arrangement for showing described according to some embodiments of the invention
The profile and top view of the storage arrangement of step.
Fig. 4 is a manufacture method wherein step of the storage arrangement for showing described according to some embodiments of the invention
The profile of storage arrangement.
Fig. 5 A- Fig. 5 B are the manufacture methods wherein of the storage arrangement for showing described according to some embodiments of the invention
The profile and top view of the storage arrangement of step.
Fig. 6 A- Fig. 6 B are the manufacture methods wherein of the storage arrangement for showing described according to some embodiments of the invention
The profile and top view of the storage arrangement of step.
Drawing reference numeral
100 storage arrangements
102 substrates
104 isolation channels
106 active regions
108th, 110 wordline
108A, 110A gate electrode
108B, 110B gate dielectric
108C, 110C, 130B lining
112 source areas
114A, 114B drain region
116 doped regions
118th, 118 ', 120,120 ', 120 ", 128,128 ', 130D, 132 second insulating barriers
120A, A, B region
122 mask layers
126th, 130A, 130C conductive layer
130 bit lines
130E, S side wall
134 protective layers
134S upper surfaces
136A, 136B drain contact connector
1A-1A, 3A-3A, 5A-5A, 6A-6A line segment
Specific embodiment
Referring to the schema of the present embodiment more fully illustrating the present invention.However, the present invention can also various differences
Form embody, and should not necessarily be limited by embodiments described herein.Layer in schema can be in order to clear with the thickness in region
For the sake of and amplify.Same or analogous reference number represents same or analogous element, and paragraphs below no longer will go to live in the household of one's in-laws on getting married one by one
State.
Figure 1A-Figure 1B is the manufacture method wherein of the storage arrangement for showing described according to some embodiments of the invention
The profile and top view of the storage arrangement of step, and Figure 1A is drawn along the line segment 1A-1A of Figure 1B
Profile.Refer to Figure 1A-Figure 1B, there is provided substrate 102, this substrate 102 has isolation channel 104 and at least two
Active region 106, and this two active regions 106 are separated by isolation channel 104.In certain embodiments, active region
106 can be the part of the projection of substrate 102, and isolation channel 104 can be the recessed part of substrate 102.Substrate 102
Semiconductor substrate, semiconducting compound substrate, semiconducting alloy substrate, insulating barrier overlying semiconductor substrate in this way
(Semiconductor Over Insulator, SOI) or the p-type being lightly doped or N-type substrate.Then, form exhausted
Edge layer 120, insulating barrier 120 covers follow-up source area 112, drain region 114A and 114B, and inserts isolation channel 104
In.The material of insulating barrier 120 may include silicon nitride, silica, silicon oxynitride or its combination, and its forming method
E.g. chemical vapour deposition technique, atomic layer deposition method or method of spin coating.
With continued reference to Figure 1A-Figure 1B, two recesses are formed with the substrate 102 of each active region 106, this two
Wordline 108 and 110 is provided with recess.This wordline 108 and 110 is also referred to as grid structure.As shown in Figure 1A,
Wordline 108 includes that gate electrode 108A and gate dielectric 108B, gate dielectric 108B are provided at gate electrode
Between 108A and substrate 102, follow-up drain region, follow-up source area, to prevent gate electrode 108A and substrate
102nd, follow-up drain region and source area are electrically connected.Similarly, wordline 110 also includes gate electrode 110A and grid
Pole dielectric layer 110B, gate dielectric 110B be provided at gate electrode 110A and substrate 102, follow-up drain region,
Between follow-up source area, to prevent gate electrode 110A to be electrically connected with substrate 102, follow-up drain region and source area
Connect.
Additionally, wordline 108 can further include a lining 108C.Lining 108C is provided at gate electrode 108A and grid
Between dielectric layer 108B.Similarly, wordline 110 can further include a lining 110C.Lining 110C is provided at grid
Between electrode 110A and gate dielectric 110B.The material of gate electrode 108A and 110A can be wrapped independently of one another
Include, but be not limited to non-crystalline silicon, polysilicon, one or more metal, metal nitride, conducting metal oxide or its
Combination.The material of gate dielectric 108B and 110B can independently of one another include, but are not limited to silica, nitridation
Silicon, silicon oxynitride, high-k (high-k) dielectric material or its combination.In certain embodiments, lining 108C
With the material of 110C can include, but are not limited to independently of one another tungsten nitride, titanium nitride, tantalum nitride or its combine.This
Outward, wordline 108 and 110 can make it below insulating barrier 120 by an etch step.
With continued reference to Figure 1A-Figure 1B, each active region 106 further includes source area 112, drain region 114A and 114B.
Source area 112 is provided in the substrate 102 between wordline 108 and 110, and drain region 114A and source area 112
It is to be respectively arranged in the substrate 102 of the opposition side of wordline 108, drain region 114B is to be respectively arranged on source area 112
In the substrate 102 of the opposition side of wordline 110.Source area 112, drain region 114A and 114B are heavily doped with first
The admixture of conductivity type (such as N-type).In the described embodiment, " heavy doping " mean exceed about 1019/cm3Doping
Concentration, such as about 1019/cm3To about 1021/cm3Doping concentration, but the invention is not restricted to this.
In certain embodiments, each active region 106 optionally further includes two doped regions 116, and this two are mixed
Miscellaneous area 116 is respectively arranged under wordline 108 and 110.This two doped regions 116 can have the second conductivity type, for example
It is p-type.Additionally, this first conductivity type is different from the second conductivity type.Additionally, the doping concentration of doped region 116 can be
About 1014/cm3-1016/cm3, but the invention is not restricted to this.
It should be noted that clearly to illustrate embodiments of the invention, Figure 1B only show substrate 102, isolation channel 104,
Active region 106, wordline 108, wordline 110, source area 112, drain region 114A and drain region 114B.
Then, insulating barrier 118 is formed on wordline 108 and 110.The material of insulating barrier 118 may include silicon nitride,
Silica, silicon oxynitride or its combination, and its forming method is, for example, chemical vapour deposition technique, atomic layer deposition method
(atomic layer deposition, ALD) or method of spin coating are formed.Additionally, in certain embodiments, insulating barrier
118 material from 120 is different.
Then, mask layer 122 is formed, mask layer 122 covers wordline 108, wordline 110 and source area 112, and
Expose located at drain region 114A, 114B be upper and insulating barrier 120 located at isolation channel 104.In certain embodiments,
This mask layer 122 can be patterning photoresist or patterned hard mask.
Fig. 2 is a manufacture method wherein step of the storage arrangement for showing described according to some embodiments of the invention
The profile of storage arrangement.Fig. 2 is referred to, all insulating barriers on drain region 114A and 114B are removed
120, and insulating barrier 120 of the part in isolation channel 104 is removed, only leave part and insert the exhausted of isolation channel 104
Edge layer 120 ', and the insulating barrier 120 on source area 112 ", and expose drain region 114A, 114B and
The side wall S not covered by insulating barrier 120 ' in isolation channel 104.In certain embodiments, can be removed by etch step
Insulating barrier of all insulating barriers 120 and part on drain region 114A and 114B in isolation channel 104
120.Above-mentioned etch step includes dry etching, wet etching or its combination.
Fig. 3 A are a manufacture method wherein steps of the storage arrangement for showing described according to some embodiments of the invention
The profile of storage arrangement, Fig. 3 B are the manufactures of the storage arrangement for showing described according to some embodiments of the invention
The top view of the method wherein storage arrangement of a step, and Fig. 3 A are drawn along the line segment 3A-3A of Fig. 3 B
Profile.Fig. 3 A- Fig. 3 B are referred to, mask layer 122 is removed.In certain embodiments, can be divested by wet type
Method, plasma incineration or its combination remove mask layer 122.Then, on drain region 114A and 114B with
And form conductive layer 126 on the side wall S that isolation channel 104 is not covered by insulating barrier 120 '.In other words, conductive layer
126 are formed at that drain region 114A and 114B be upper and isolation channel 104 is not by the side wall S of the covering of insulating barrier 120 '
On.Additionally, two conductive layers 126 are electrically connected drain region 114A and drain region 114B.
In certain embodiments, conductive layer 126 can be by epitaxial growth (epitaxial growth) technique formed silicon,
Germanium, silicon and germanium, III-V or its combine.This epitaxial growth process may include metal-organic chemical vapor
Sedimentation (MOCVD), metal-organic chemical vapor epitaxy (MOVPE), plasma-enhanced chemical gas phase
Outside sedimentation (plasma-enhanced CVD), remote plasma chemical vapour deposition technique (RP-CVD), molecular beam
Prolong method (MBE), hydride vapour phase epitaxy method (HVPE), liquid phase epitaxial method (LPE), chloride vapor phase epitaxy method
(Cl-VPE)。
Special instruction, conductive layer 126 is the touch-down zone as follow-up drain contact connector.In traditional memory
In device, drain contact connector only can directly land on the upper surface of drain region, that is, only be located at Fig. 3 A- Fig. 3 B
A areas in.In comparison, the embodiment of the present invention be by using this as the touch-down zone of drain contact connector conduction
Floor 126 is extended on the side wall S that isolation channel 104 is not covered by insulating barrier 120 ' (that is, extending to B areas by A areas),
Therefore can increase drain contact connector touch-down zone (that is, increased the touch-down zone of dark parts in the 126 of corresponding diagram 3B,
This part is part of the conductive layer 126 beyond active region 106 in top view), and thereby increase memory device
The technique allowance and technique yields put.
Fig. 4 is a manufacture method wherein step of the storage arrangement for showing described according to some embodiments of the invention
The profile of storage arrangement.Fig. 4 is referred to, in the formation insulating barrier 128 (not illustrating) of blanket on substrate 102,
And a flatening process is carried out to expose the insulating barrier on source area 112 for stop-layer with insulating barrier 118
120 " (Fig. 4 is not illustrated in, its position is the position corresponding to the 120A of Fig. 4 regions).The material of insulating barrier 128
May include silicon nitride, silica, silicon oxynitride or its combination, and its forming method be, for example, chemical vapour deposition technique,
Atomic layer deposition method or method of spin coating.Then, as shown in figure 4, removing on source area 112 by insulating barrier
128 insulating barriers 120 for exposing ".
Fig. 5 A- Fig. 5 B are the manufacture methods wherein of the storage arrangement for showing described according to some embodiments of the invention
The profile and top view of the storage arrangement of step, and Fig. 5 A are drawn along the line segment 5A-5A of Fig. 5 B
Profile.Fig. 5 A- Fig. 5 B are referred to, bit line 130 is formed on source area 112, this bit line 130 electrically connects source
Polar region 112.Bit line 130 may include conductive layer 130A, lining 130B, the conductive layer being sequentially disposed on substrate 102
130C and insulating barrier 130D and coated with conductive layer 130A, lining 130B, conductive layer 130C and insulating barrier 130D
Side wall 130E.Additionally, this side wall 130E more may extend on insulating barrier 128 (do not illustrate).Special instruction,
When side wall 130E is formed, can etching insulating layer 118 and 128.Insulating barrier after etched is respectively with insulating barrier
118 ' represent with insulating barrier 128 '.
The material of conductive layer 130A may include doped or undoped polysilicon, copper, aluminium, tungsten or its combination.Lining
The material of 130B may include titanium nitride, tungsten nitride, tantalum nitride or its combination.The material of conductive layer 130C may include tungsten,
Copper, aluminium, gold, chromium, nickel, platinum, titanium, iridium, rhodium or its combination.Conductive layer 130A, lining 130B and conduction
Layer 130C can be formed for example, by for sputtering method, galvanoplastic, resistance heating evaporation method or electron-beam vapor deposition method.Insulation
Layer 130D and the material of side wall 130E may include silicon nitride, silica, silicon oxynitride or its combine, and its shape
It is, for example, chemical vapour deposition technique, atomic layer deposition method or method of spin coating into method.
With continued reference to Fig. 5 A, in the formation insulating barrier 132 of compliance on substrate 102.Then, in insulating barrier 132
The formation protective layer 134 (not illustrating) of upper blanket.Then, with insulating barrier 132 for stop-layer carries out a flat chemical industry
Skill, to expose the upper surface of the insulating barrier 132 of covering bit line 130.The material of insulating barrier 132 and protective layer 134 can
Including silicon nitride, silica, silicon oxynitride or its combination, and its forming method be, for example, chemical vapour deposition technique,
Atomic layer deposition method or method of spin coating.In certain embodiments, the material of insulating barrier 132 and protective layer 134 is different.
In certain embodiments, the material of protective layer 134 can be with insulating barrier 120,120 ', 120 " material it is identical.
The material of for example, in certain embodiments, protective layer 134 and insulating barrier 120,120 ', 120 " is all silica.
Additionally, in certain embodiments, the material of insulating barrier 118,128,130D, side wall 130E and insulating barrier 132
Can be identical.For example, in certain embodiments, insulating barrier 118,128,130D, side wall 130E and insulating barrier
132 material is all silicon nitride.
Fig. 6 A- Fig. 6 B are the manufacture methods wherein of the storage arrangement for showing described according to some embodiments of the invention
The profile and top view of the storage arrangement of step, and Fig. 6 A are drawn along the line segment 6A-6A of Fig. 6 B
Profile.Fig. 6 A- Fig. 6 B are referred to, drain contact connector 136A and 136B are formed in protective layer 134, this
Drain contact connector 136A and 136B is respectively arranged on two conductive layers 126 of the left and right sides of active region 106, and
It is electrically connected drain region 114A and 114B.Specifically, this drain contact connector 136A and 136B self-shields
The upper surface 134S of layer 134 extends downwardly through protective layer 134 and insulating barrier 132 and 128 ' and respectively directly contact
Corresponding conductive layer 126, to electrically connect drain region 114A and 114B.
From Fig. 6 A, the embodiment of the present invention is formed from drain region 114A and 114B upper surfaces and extends to isolation channel
Conductive layer (that is, B areas are extended to by A areas) on the 104 side wall S not covered by insulating barrier 120 ', therefore leakage can be increased
The touch-down zone of pole contact plunger 136A and 136B (that is, increased dark color portion in the 136A and 136B of corresponding diagram 6B
The touch-down zone divided, this part is part of the conductive layer 126 beyond active region 106 in top view), and thereby
Increase the technique allowance and technique yields of storage arrangement.
With continued reference to Fig. 6 A- Fig. 6 B, the embodiment of the present invention provides a kind of storage arrangement 100, storage arrangement 100
Including substrate 102, this substrate 102 has isolation channel 104 and two active regions 106, and this two active regions 106
It is to be separated by isolation channel 104.Each active region 106 include wordline 108 and 110 in the substrate 102,
The source area 112 in substrate 102 between wordline 108 and 110, located at wordline 108 and the phase of source area 112
Drain region 114A in the substrate 102 tossed about and the substrate 102 located at wordline 110 Yu the opposition side of source area 112
In drain region 114B.Additionally, in certain embodiments, each active region 106 is further included and is respectively arranged on wordline 108
Lower two doped regions 116 with 110.
Storage arrangement 100 further includes the insulating barrier 118 on wordline 108 and 110, and part insert every
From the insulating barrier 120 ' of groove 104.Additionally, storage arrangement 100 further includes conductive layer 126, conductive layer 126 is to set
In drain region 114A and 114B be upper and the side wall S not by the covering of insulating barrier 120 ' of isolation channel 104 on.
Storage arrangement 100 further includes the insulating barrier 128 ' on the insulating barrier 120 ' in isolation channel 104, and
Bit line 130 on source area 112, wherein, the electrical connection source area 112 of bit line 130.Additionally, memory device
Put 100 further include compliance covering substrate 102 and bit line 130 insulating barriers 132, and located at substrate 102 with it is exhausted
Protective layer 134 in edge layer 132.Additionally, the drain electrode that storage arrangement 100 is further included in protective layer 134 connects
Touch connector 136A and 136B.The upper surface 134S of drain contact connector 136A and 136B self-insurances sheath 134 is downward
Extend through protective layer 134, insulating barrier 132 and 128 and be electrically connected drain region 114A and 114B.
In sum, it is of the invention by the conductive layer extended on ditch non-intercommunicating cells lateral wall is formed on drain region, to increase leakage
The touch-down zone scope of pole contact plunger, and thereby increase the technique allowance and technique yields of storage arrangement.Separately
Outward, as shown in Figure 3A, because the present invention forms conductive layer by epitaxial growth (epitaxial growth) technique, therefore
Without complicated chemical wet etching step, you can self aligned only to form conductive layer in the substrate surface for exposing.
Although the present invention is disclosed above with foregoing embodiment, so it is not limited to the present invention.Skill belonging to of the invention
Have usually intellectual in art field, without departing from the spirit and scope of the present invention, when can do a little change with profit
Decorations.Therefore protection scope of the present invention is worked as and is defined depending on the claim person of defining.
Claims (10)
1. a kind of storage arrangement, it is characterised in that the storage arrangement includes：
One substrate, with an isolation channel and two active regions, wherein two active regions are separated by the isolation channel,
And each active region includes：
One first wordline and one second wordline, in the substrate；
Source region, in the substrate between first wordline and second wordline；
One first drain region, wherein first drain region and the source area are the opposition sides for being respectively arranged on first wordline
In substrate；And
One second drain region, wherein second drain region and the source area are the opposition sides for being respectively arranged on second wordline
In substrate；
One first insulating barrier, partly inserts the isolation channel；
One second insulating barrier, on first wordline and second wordline；And
One conductive layer, on first drain region, on second drain region and the isolation channel first is not insulated by this
On the side wall of layer covering.
2. storage arrangement as claimed in claim 1, it is characterised in that the storage arrangement is further included：
One the 3rd insulating barrier, on first insulating barrier in the isolation channel；And
One bit line, on the source area, wherein the bit line electrically connects the source area.
3. storage arrangement as claimed in claim 2, it is characterised in that the storage arrangement is further included：
One the 4th insulating barrier, compliance covers the substrate and the bit line；
One protective layer, on the substrate and the 4th insulating barrier；And
One first drain contact connector and one second drain contact connector, in the protective layer, wherein first drain electrode
Contact plunger extends downwardly through the protective layer, the 4th with the second drain contact connector from the upper surface of the protective layer
Insulating barrier and the 3rd insulating barrier are simultaneously electrically connected first drain region and second drain region.
4. storage arrangement as claimed in claim 1, it is characterised in that each active region is further included：
Two doped regions, are respectively arranged under first wordline and second wordline.
5. storage arrangement as claimed in claim 1, it is characterised in that the material of second insulating barrier with this
The material of one insulating barrier is different.
6. a kind of manufacture method of storage arrangement, it is characterised in that the manufacture method of the storage arrangement includes：
A substrate is provided, with an isolation channel and two active regions, wherein two active regions are by the isolation channel point
Every；
Form one first insulating barrier and insert the isolation channel, each of which active region includes；
One first wordline and one second wordline, in the substrate；
Source region, in the substrate between first wordline and second wordline；
One first drain region, wherein first drain region and the source area are the opposition sides for being respectively arranged on first wordline
In substrate；And
One second drain region, wherein second drain region and the source area are the opposition sides for being respectively arranged on second wordline
In substrate, wherein first insulating barrier covers the source area, first drain region and second drain region；
One second insulating barrier is formed on first wordline and second wordline；
A mask layer is formed, first wordline, second wordline and the source area is covered, and expose located at first leakage
On polar region, on second drain region and located at first insulating barrier of the isolation channel；
Remove first insulating barrier on first drain region and on second drain region, and remove part located at should
First insulating barrier of isolation channel, with expose first drain region, second drain region and the isolation channel not by this
The side wall of one insulating barrier covering；And
A conductive layer is formed on first drain region, on second drain region and the isolation channel first is not insulated by this
On the side wall of layer covering.
7. the manufacture method of storage arrangement as claimed in claim 6, it is characterised in that form the conductive layer
Step includes an epitaxial growth process.
8. the manufacture method of storage arrangement as claimed in claim 6, it is characterised in that in forming the conductive layer
Afterwards, the manufacture method of the storage arrangement is further included：
One the 3rd insulating barrier is formed on the substrate, wherein the 3rd insulating barrier expose on the source area this first
Insulating barrier；
Remove first insulating barrier on the source area；And
A bit line is formed on the source area, wherein the bit line electrically connects the source area.
9. the manufacture method of storage arrangement as claimed in claim 8, it is characterised in that after the bit line is formed,
The manufacture method of the storage arrangement is further included：
One the 4th insulating barrier is formed, compliance covers the substrate and the bit line；
A protective layer is formed on the substrate and the 4th insulating barrier；And
Form one first drain contact connector and during one second drain contact plugs in the protective layer, wherein first drain electrode
Contact plunger is electrically connected first drain region and second drain region with the second drain contact connector.
10. the manufacture method of storage arrangement as claimed in claim 6, it is characterised in that each active region is more
Including：
Two doped regions, are respectively arranged under first wordline and second wordline.
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| CN201510814717.4A CN106783743B (en) | 2015-11-23 | 2015-11-23 | Memory device and its manufacturing method |
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