CN106776107B - A kind of parity error correction method and the network equipment - Google Patents
A kind of parity error correction method and the network equipment Download PDFInfo
- Publication number
- CN106776107B CN106776107B CN201611079584.1A CN201611079584A CN106776107B CN 106776107 B CN106776107 B CN 106776107B CN 201611079584 A CN201611079584 A CN 201611079584A CN 106776107 B CN106776107 B CN 106776107B
- Authority
- CN
- China
- Prior art keywords
- module
- configuration data
- parity error
- hardware
- hardware forwarding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Detection And Correction Of Errors (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The embodiment of the invention provides a kind of parity error correction method and the network equipments, belong to data communication technology field.This method comprises: processor module down distributing configuration data is to hardware forwarding module, and the configuration data is sent to cache module and is backed up.Processor module configures corresponding hardware table item in hardware forwarding module or register according to the configuration data.Hardware forwarding module carries out parity errors error detection to the value with the hardware table item or register postponed, and when detecting that parity errors, which occur, mistakes, Xiang Suoshu processor module sends interrupt notification.Processor module receives after the interrupt notification according to the configuration data backed up in the cache module, to occurring the hardware table item of parity error in the hardware forwarding module or register is corrected and restores.The present invention can effectively improve the validity and reliability restored to parity error.
Description
Technical field
The present invention relates to data communication technology fields, set in particular to a kind of parity error correction method and network
It is standby.
Background technique
With the fast development of Internet technology, the dependence in life for internet is more and more stronger, hence for net
The requirement of network is also higher and higher (such as: network bandwidth and network stabilization), therefore for the network of bearer network data forwarding
More stringent requirements are proposed for equipment (such as router and interchanger) to guarantee the fluency and stability of network application.Current net
Network equipment is essentially all that the forward process of data is completed using hard forwarding chip, to reduce network delay, increase Netowrk tape
Wide and raising forward efficiency.At present since the integrated level of chip is higher and higher, lead to the word of chip list item entry and register
Section is also more and more.In addition, the various network equipments are often put together at computer room, there is interference between each other, increase chip
The probability of list item and register bit mistake.Once some significant bits in chip list item or register are flipped (example
It such as: two-layer retransmitting table, three layer retransmitting tables and logic judgment register) will lead to two layers of forwarding or three layers of forwarding do not given birth to
Effect, and then cause service disconnection failure.
Inventor has found that the error correction for chip is typically all to carry out self redundancy recovery by chip interior under study for action,
For the parity check method of chip, since there may be multiple bit-errors, there is presently no a good methods can
The mistake of configuration data in chip is detected and corrected simultaneously with even-odd check.
Summary of the invention
The present invention provides a kind of parity error correction method and the network equipments, it is intended to even-odd check detected error
It is effectively corrected and is restored, to improve the validity and reliability of data forwarding.
In a first aspect, a kind of parity error correction method provided in an embodiment of the present invention, comprising:
Processor module down distributing configuration data to hardware forwarding module, and by the configuration data be sent to cache module into
Row backup；
The processor module is according to the configuration data to corresponding hardware table item or deposit in hardware forwarding module
Device is configured；
The hardware forwarding module carries out parity error to the value with the hardware table item or register postponed
Detection, when detecting that parity errors, which occur, mistakes, Xiang Suoshu processor module sends interrupt notification；
The processor module receives after the interrupt notification according to the configuration data backed up in the cache module,
The hardware table item of generation parity error or register in the hardware forwarding module are corrected and are restored.
Preferably, after the processor module down distributing configuration data to hardware forwarding module, by the configuration data
It is sent to before cache module backed up, the method also includes:
The processor module detects the corresponding hardware table item of the configuration data or the whether enabled odd even school of register
Test error correction；
When the parity error correction function of detecting the corresponding hardware table item of the configuration data or register is enabled
When, the configuration data is just sent to cache module and is backed up.
Preferably, the processor module is matched after receiving the interrupt notification according to what is backed up in the cache module
Data are set, the hardware table item of generation parity error or register in the hardware forwarding module are corrected and are restored
The step of include:
There is the position of parity error in the configuration data that the processor module obtains in the hardware forwarding module
Confidence breath, wherein the location information includes the call number or initial address of hardware table item or register；
The processor module inquires corresponding storage location in the cache module according to the positional information, calls
Configuration data in the cache module is corrected and restores to the configuration data in the hardware forwarding module.
Preferably, after the step of configuration data in the hardware forwarding module is corrected and restores, institute
State method further include:
The processor module records parity error event and correction event.
Preferably, the processor module down distributing configuration data is sent to hardware forwarding module, and by the configuration data
After the step of being backed up to cache module, the method also includes:
The processor module will go enabled control instruction to be sent to the hardware forwarding module, be turned with disabling the hardware
Send out the parity error correction function of module；
The configuration data that parity error will be present in the processor module is sent to the hardware forwarding module；
The processor module sends enabled control instruction to the hardware forwarding module, forwards mould to enable the hardware
The parity error correction function of block；
Configuration of the processor module according to the hardware forwarding module after parity error correction function is enabled
Whether the data verification parity error is corrected reparation.Second aspect, a kind of network equipment provided in an embodiment of the present invention,
Including processor module, hardware forwarding module and cache module, the processor module includes configuration unit, parity error
Receiving unit and parity error recovery unit,
The configuration unit for down distributing configuration data to hardware forwarding module, and the configuration data is sent to slow
Storing module is backed up；
The configuration unit, be also used to according to the configuration data to corresponding hardware table item in hardware forwarding module or
Register is configured；
The hardware forwarding module, for carrying out even-odd check to the value with the hardware table item or register postponed
Error detection, when detecting that parity errors, which occur, mistakes, Xiang Suoshu processor module sends interrupt notification；
The parity error receiving unit is sent to institute for receiving the interrupt notification, and by the interrupt notification
State parity error recovery unit；
The parity error recovery unit, for basis after receiving the interrupt notification in the cache module
The configuration data of backup carries out school to the hardware table item of generation parity error or register in the hardware forwarding module
Just and restore.
Preferably, the configuration unit, is also used to detect the corresponding hardware table item of the configuration data or register is
No enabled parity error correction function；And
When the parity error correction function of detecting the corresponding hardware table item of the configuration data or register is enabled
When, the configuration data is just sent to cache module and is backed up.
Preferably, the parity error recovery unit, for obtaining the configuration number in the hardware forwarding module
According to there is the location information of parity error, wherein the location information include hardware table item or register call number or
Initial address；And
For inquiring corresponding storage location in the cache module according to the positional information, the caching mould is called
Configuration data in block is corrected and restores to the configuration data in the hardware forwarding module.
Preferably, the processor module further include: recording unit, for parity error event and correction event
It is recorded.
Preferably, the configuration unit, for enabled control instruction will to be gone to be sent to the hardware forwarding module, with disabling
The parity error correction function of the hardware forwarding module；
Configuration data for parity error to will be present is sent to the hardware forwarding module；And it is used for described hard
Part forwarding module sends enabled control instruction, to enable the parity error correction function of the hardware forwarding module；
The processor module further include: authentication unit is used for according to the hardware forwarding module in parity error correction
Configuration data after function is enabled verifies whether the parity error is corrected reparation.
A kind of parity error correction method provided in an embodiment of the present invention and the network equipment will be configured by processor module
Data are sent to hardware forwarding module, while being sent to cache module and being backed up, when the hardware forwarding module detects institute
It states configuration data generation parity errors to mistake, sends an interrupt notification to the processor module, to trigger the processor
Module call backup the configuration data in the cache module to the configuration data in hardware forwarding module be corrected with it is extensive
It is multiple, to effectively improve the validity and reliability restored to parity error.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore should not be viewed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 is a kind of hardware composition block diagram for network equipment that embodiment of the present invention provides.
Fig. 2 shows the functional block diagrams of the processor module in Fig. 1.
Fig. 3 is a kind of flow chart for parity error correction method that embodiment of the present invention provides.
Fig. 4 be applied to down distributing configuration data shown in Fig. 3 to hardware forwarding module the step of before flow chart.
Configuration data is sent to after the step of cache module is backed up by Fig. 5 applied to shown in Fig. 3
Flow chart.
Figure acceptance of the bid note is respectively as follows:
Icon: the 100- network equipment；101- hardware forwarding module；102- cache module；103- processor module；1031-
Configuration unit；1032- parity error receiving unit；1033- parity error recovery unit；1034- recording unit；
1035- authentication unit.
Specific embodiment
Error correction for chip is typically all to carry out self redundancy recovery by chip interior, for the even-odd check side of chip
Method can detecte out individual bit mistake or odd number bit-errors, but can not confirm specifically which bit-errors, i.e.,
Parity check method does not have the ability of error correction.Since there may be multiple bit-errors, well there is presently no one
Method can detect and correct simultaneously the mistake of the configuration data in chip with parity check method.
In view of this, can effectively be solved the embodiment of the invention provides a kind of parity error correction method and the network equipment
The certainly above problem.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without creative efforts, shall fall within the protection scope of the present invention.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.
As shown in Figure 1, it is a kind of hardware composition block diagram of network equipment 100 provided in an embodiment of the present invention.The network is set
Standby 100 may include, but be not limited to interchanger and router etc..Wherein, the network equipment 100 may include hardware forwarding mould
Block 101, cache module 102 and processor module 103.
Referring to Fig. 2, being the functional block diagram of the processor module 103.In the present embodiment, the processor module
103 may include configuration unit 1031, parity error receiving unit 1032, parity error recovery unit 1033, note
Record unit 1034 and authentication unit 1035 etc..Above each functional module will be described in detail below.
In the present embodiment, before configuration data is sent to the hardware forwarding module 101 by the configuration unit 1031,
Enabled control instruction is sent to the hardware forwarding module 101 first by the configuration unit 1031, to trigger the hardware forwarding
Module 101 opens parity error correction function.Then, it is spaced after a preset time (such as: 3 seconds or 5 seconds etc.), the configuration list
First 1031 pairs of hardware forwarding modules 101 detect, and obtain the parity error correction function of the hardware forwarding module 101
Open and close state.
Wherein, when the configuration unit 1031 detects that the parity error correction function of the hardware forwarding module 101 is opened
Configuration data can be sent respectively to the hardware forwarding module 101 and the cache module 102 by Qi Shi.In the present embodiment, institute
Stating configuration data may include chip list item and register words segment information.The hardware forwarding module 101 is according to the configuration data
Hardware table item or register are configured.The configuration data is then carried out storage backup by the cache module 102.Wherein, institute
Stating configuration may include that the configuration data in the hardware table item or register is added, updates or is deleted.In detail
Ground, the cache module 102 parse the configuration data received, obtain and hardware table item corresponding to the configuration data
Or after the field width of register, the distribution of storage address and storage size is carried out, and carry out to the configuration data
Storage.
In addition, when the configuration unit 1031 detects that the parity function of the hardware forwarding module 101 is not opened
When, configuration data can be simply sent to the hardware forwarding module 101, deposited without being sent to the cache module 102
Lay in part.The hardware forwarding module 101 configuration data can be written the hardware forwarding module 101 hardware table item or
Register.Certainly, the configuration data not important for hardware table item or register, in order to increase configuration flexibility and
The memory space for saving cache module 102, can not store the configuration data.
The hardware forwarding module 101 carries out parity errors error detection to the configuration data received, when detecting
It states configuration data generation parity errors to mistake, Xiang Suoshu parity error receiving unit 1032 sends interrupt notification.It is described
The interrupt notification received is transmitted to the parity error recovery unit by parity error receiving unit 1032 in time
1033, to avoid because parity error does not have to restore the phenomenon for causing business interruption time too long in time.In addition, working as
Detect that parity errors do not occur and mistake for the configuration data, according to the configuration data to the hardware forwarding module 101
Hardware table item or register configured.
In the present embodiment, the parity error recovery unit 1033 is obtained according to the interrupt notification received described
The configuration data backed up in cache module 102, complete to the configuration data in the hardware forwarding module 101 be corrected with it is extensive
It is multiple.In detail, the parity error recovery unit 1033 obtains that there are the positions of the configuration data of parity error first
Confidence breath.Wherein, the location information may include call number or initial address of hardware table item or register etc..In addition,
The parity error recovery unit 1033 inquires corresponding storage in the cache module 102 according to the positional information
Position, and the configuration data in the cache module 102 is called out, to the configuration number in the hardware forwarding module 101
According to being corrected and restore.
Optionally, when the parity error receiving unit 1032 detects the configuration data, there are parity errors
It mistakes, which is sent to the recording unit 1034, the recording unit 1034 is to the even-odd check
Error message is recorded and stored.In addition, when there are parity errors for 1033 pairs of the parity error recovery unit
Configuration data when being corrected, which is sent to the recording unit 1034, the recording unit
1034 record and store the parity-corrected information.
In order to which the parity error recovery capability to the network equipment 100 is effectively simulated and tested, in Xiang Suoshu
Before hardware forwarding module 101 sends configuration data, the configuration unit 1031 will be sent out to the hardware forwarding module 101 first
Send one to go enabled control instruction, the hardware forwarding module 101 it is described go enabled control instruction under the action of disable it is described hard
The parity error correction function of part forwarding module 101.Then, the configuration unit 1031 is sent out to the hardware forwarding module 101
Enabled control instruction is sent, the hardware forwarding module 101 triggers the hardware according to the enabled control instruction received and forwards mould
The parity error correction function of block 101.And the configuration is triggered by external event (such as: beat stream or read configuration data etc.)
The parity error of data.After being spaced a preset time (such as 5 seconds or 10 seconds etc.) again, the authentication unit 1035 is described
Parity function carries out the inquiry of configuration data after being enabled, judge whether the parity error is resumed.In detail,
It mistakes when the configuration data inquired still remains parity errors, judges that the parity error is not corrected recovery.When looking into
The configuration data ask out and there is no when parity error, judges that the parity error is corrected recovery.
As shown in figure 3, being a kind of flow chart of parity error correction method provided in an embodiment of the present invention.This method can answer
For the network equipment 100.Referring to Fig. 1, the network equipment 100 may include hardware forwarding module 101, cache module
102 and processor module 103.Wherein, the method can comprise the following steps that
Step S101: 103 down distributing configuration data of processor module is to hardware forwarding module 101, and by the configuration
Data are sent to the cache module 102 and are backed up.
Wherein, when the processor module 103 detects that the parity error correction function of the hardware forwarding module 101 is opened
Configuration data is then sent respectively to the hardware forwarding module 101 and the cache module 102 by Qi Shi.In the present embodiment, institute
Stating configuration data may include hardware table item and register words segment information.
Step S102: the processor module 103 is according to the configuration data to corresponding hard in hardware forwarding module 101
Part list item or register are configured.
In the present embodiment, the processor module 103 configures hardware table item or register according to the configuration data.
The configuration data is then carried out storage backup by the cache module 102.Wherein, the configuration may include to the hardware table item
Or the configuration data in register is added, updates or deletes.In detail, the cache module 102 is to receiving
Configuration data is parsed, and is obtained and is stored after the field width of hardware table item corresponding to the configuration data or register
The distribution of address and storage size, and the configuration data is stored.
Step S103: the hardware forwarding module 101 carries out the value with the hardware table item or register postponed
Parity errors error detection, when detecting that parity errors, which occur, mistakes, Xiang Suoshu processor module 103 sends interrupt notification.
The hardware forwarding module 101 carries out parity errors error detection to the configuration data received, when detecting
It states configuration data generation parity errors to mistake, Xiang Suoshu processor module 103 sends interrupt notification.The processor module
103 pairs of interrupt notifications received timely respond to, to avoid because parity error leads to business without recovery in time
Break period too long phenomenon occurs.In addition, when detecting that parity errors do not occur and mistake for the configuration data, according to described
Configuration data configures the hardware table item or register of the hardware forwarding module 101.
Step S104: basis is in the cache module 102 after the processor module 103 receives the interrupt notification
Configuration data, in the hardware forwarding module 101 occur parity error hardware table item or register carry out school
Just and restore.
In the present embodiment, the processor module 103 is obtained according to the interrupt notification received in the cache module 102
The configuration data of middle backup, completion are corrected and restore to the configuration data in the hardware forwarding module 101.In detail,
The processor module 103 obtains that there are the location informations of the configuration data of parity error first.Wherein, the position letter
Breath may include call number or initial address of hardware table item or register etc..In addition, the processor module 103 is according to institute
It states location information and inquires corresponding storage location in the cache module 102, and by the configuration number in the cache module 102
According to calling out, the configuration data in the hardware forwarding module 101 is corrected and is restored.
Optionally, when the processor module 103 detects the configuration data, there are parity errors to mistake, to described
Parity errors false information is recorded and stored.In addition, when the processor module 103 is to there are parity errors to match
When setting data and being corrected, which is recorded and stored.
As shown in figure 4, the method also includes following steps before step S101.
Step S201: the processor module 103 detects the corresponding hardware table item of the configuration data or register is
No enabled parity error correction function.
In the present embodiment, the processor module 103 by configuration data be sent to the hardware forwarding module 101 it
Before, which is sent to the hardware forwarding module 101 for enabled control instruction first, to trigger the hardware
Forwarding module 101 opens parity error correction function.Then, a preset time (such as: 3 seconds or 5 seconds etc.) is spaced to described hard
Part forwarding module 101 is detected, and obtains the open and close state of the parity function of the hardware forwarding module 101.
Step S202: when the parity error correction function for detecting the corresponding hardware table item of the configuration data or register
When can be enabled, the configuration data is just sent to cache module 102 and is backed up.
In the present embodiment, the hardware forwarding module 101 matches hardware table item or register according to the configuration data
It sets.The configuration data is then carried out storage backup by the cache module 102.Wherein, the configuration may include to the hardware
Configuration data in list item or register is added, updates or deletes.In detail, 102 pairs of cache module receptions
To configuration data parsed, obtain carrying out with after the field width of hardware table item corresponding to the configuration data or register
The distribution of storage address and storage size, and the configuration data is stored.
In addition, when the processor module 103 detects that the parity function of the hardware forwarding module 101 is not opened
When, configuration data can be simply sent to the hardware forwarding module 101, deposited without being sent to the cache module 102
Lay in part.The hardware forwarding module 101 configuration data can be written the hardware forwarding module 101 hardware table item or
Register.Certainly, the configuration data not important for hardware table item or register, in order to increase configuration flexibility and
The memory space for saving cache module 102, can not store the configuration data.
In order to which the parity error recovery capability to the network equipment 100 is effectively simulated and tested, such as Fig. 5 institute
Show, the method also includes following steps.
Step S301: the processor module 103 will go enabled control instruction to be sent to the hardware forwarding module 101,
To disable the parity error correction function of the hardware forwarding module 101.
Before sending configuration data to the hardware forwarding module 101, the processor module 103 will be first to described
Hardware forwarding module 101 sends one and goes enabled control instruction, and the hardware forwarding module 101 goes to enable control instruction described
The parity error correction function of the effect lower disabling hardware forwarding module 101.
Step S302: the configuration data that parity error will be present in the processor module 103 is sent to the hardware
Forwarding module 101.
Step S303: the processor module 103 sends enabled control instruction to the hardware forwarding module 101, so that
The parity error correction function of the energy hardware forwarding module 101.
The processor module 103 sends enabled control instruction to the hardware forwarding module 101, and the hardware forwards mould
Block 101 triggers the parity error correction function of the hardware forwarding module 101 according to the enabled control instruction received.And pass through
The parity error of external event (such as: beating stream and read configuration data etc.) described configuration data of triggering.
Step S304: the processor module 103 is according to the hardware forwarding module 101 in parity error correction function quilt
Configuration data after enabled verifies whether the parity error is corrected reparation.
After being spaced a preset time (such as 5 seconds or 10 seconds etc.) again, the processor module 103 is in the even-odd check function
The inquiry that configuration data is carried out after capable of being enabled, judges whether the parity error is resumed.In detail, when inquiring
Configuration data still remains parity errors and mistakes, and judges that the parity error is not corrected recovery.When the configuration inquired
Data and be not present parity error when, judge that the parity error is corrected recovery.
A kind of parity error correction method provided in an embodiment of the present invention and the network equipment, will by processor module 103
Configuration data is sent to hardware forwarding module 101, while being sent to cache module 102 and being backed up, when the hardware forwards mould
Block 101 detects that the configuration data occurs parity errors and mistakes, and sends an interrupt notification to the processor module 103,
Call configuration data of the backup in the cache module 102 to hardware forwarding module 101 to trigger the processor module 103
In configuration data be corrected and restore, to effectively improve the validity restored to parity error and reliable
Property.
In the embodiment of the present invention, processor module 103 and hardware forwarding module 101 can the functions as defined in executing or dynamic
The dedicated hardware chip made realizes that (such as 103 function of processor module is realized that hardware forwarding module 101 is by handing over by CPU
Chip is changed to realize), or can realize using a combination of dedicated hardware and computer instructions (such as 103 module function of processor
It can be realized by CPU and dependent instruction, hardware forwarding module 101 is realized by exchange chip and dependent instruction).
It should be noted that in embodiment provided herein, it should be understood that disclosed device and method, it can
To realize by another way.The apparatus embodiments described above are merely exemplary, for example, the unit is drawn
Point, only a kind of logical function partition, there may be another division manner in actual implementation.
In embodiment provided herein, it should be understood that disclosed device and method can pass through others
Mode is realized.The apparatus embodiments described above are merely exemplary, for example, the flow chart and block diagram in the drawings show
The device of multiple embodiments according to the present invention, the architectural framework in the cards of method and computer program product, function and
Operation.In this regard, each box in flowchart or block diagram can represent a part of a module, section or code,
A part of the module, section or code includes one or more executable fingers for implementing the specified logical function
It enables.It should also be noted that in some implementations as replacements, function marked in the box can also be to be different from institute in attached drawing
The sequence of mark occurs.For example, two continuous boxes can actually be basically executed in parallel, they sometimes can also be by phase
Anti- sequence executes, and this depends on the function involved.The unit as illustrated by the separation member can be or can also be with
It is not physically separated, component shown as a unit may or may not be physical unit, it can be located at one
A place, or may be distributed over multiple network units.Part therein or complete can be selected according to the actual needs
Portion unit achieves the purpose of the solution of this embodiment.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion so that article or equipment including a series of elements not only include those elements, but also is wrapped
Include other elements that are not explicitly listed.In the absence of more restrictions, being wanted by what sentence "including a ..." limited
Element, it is not excluded that there is also other identical elements in the article or equipment for including the element.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (10)
1. a kind of parity error correction method, which is characterized in that the described method includes:
Processor module down distributing configuration data to hardware forwarding module, and by the configuration data be sent to cache module carry out it is standby
Part；
The processor module according to the configuration data to corresponding hardware table item in hardware forwarding module or register into
Row configuration；
The hardware forwarding module carries out parity errors error detection to the value with the hardware table item or register postponed,
When detecting that parity errors, which occur, mistakes, Xiang Suoshu processor module sends interrupt notification；
The processor module is received according to the configuration data backed up in the cache module after the interrupt notification, to institute
The hardware table item of generation parity error or register in hardware forwarding module is stated to be corrected and restore.
2. parity error correction method according to claim 1, which is characterized in that the processor module issues configuration number
After arriving hardware forwarding module, before the configuration data to be sent to cache module and is backed up, the method is also wrapped
It includes:
The processor module detects the corresponding hardware table item of the configuration data or the whether enabled even-odd check of register is entangled
Wrong function；
When the parity error correction function of detecting the corresponding hardware table item of the configuration data or register is enabled,
The configuration data is sent to cache module to back up.
3. parity error correction method according to claim 1, which is characterized in that the processor module receives described
According to the configuration data that is backed up in the cache module after interrupt notification, to even-odd check occurs in the hardware forwarding module
The hardware table item or register of mistake are corrected and include: the step of recovery
There is the position letter of parity error in the configuration data that the processor module obtains in the hardware forwarding module
Breath, wherein the location information includes the call number or initial address of hardware table item or register；
The processor module inquires corresponding storage location in the cache module according to the positional information, described in calling
Configuration data in cache module is corrected and restores to the configuration data in the hardware forwarding module.
4. parity error correction method according to claim 3, which is characterized in that described in the hardware forwarding module
Configuration data the step of being corrected and restoring after, the method also includes:
The processor module records parity error event and correction event.
5. parity error correction method according to claim 1, which is characterized in that the processor module issues configuration number
According to arriving hardware forwarding module, and after the configuration data is sent to the step of cache module is backed up, the method is also
Include:
The processor module will go enabled control instruction to be sent to the hardware forwarding module, to disable the hardware forwarding mould
The parity error correction function of block；
The configuration data that parity error will be present in the processor module is sent to the hardware forwarding module；
The processor module sends enabled control instruction to the hardware forwarding module, to enable the hardware forwarding module
Parity error correction function；
Configuration data of the processor module according to the hardware forwarding module after parity error correction function is enabled
Verify whether the parity error is corrected reparation.
6. a kind of network equipment, which is characterized in that the network equipment includes processor module, hardware forwarding module and caching mould
Block, the processor module include configuration unit, parity error receiving unit and parity error recovery unit,
The configuration unit is sent to caching mould to hardware forwarding module, and by the configuration data for down distributing configuration data
Block is backed up；
The configuration unit is also used to according to the configuration data to corresponding hardware table item or deposit in hardware forwarding module
Device is configured；
The hardware forwarding module, for carrying out parity error to the value with the hardware table item or register postponed
Detection, when detecting that parity errors, which occur, mistakes, Xiang Suoshu processor module sends interrupt notification；
The parity error receiving unit is sent to the surprise for receiving the interrupt notification, and by the interrupt notification
Even parity check error recovery unit；
The parity error recovery unit backs up in the cache module for basis after receiving the interrupt notification
Configuration data, in the hardware forwarding module occur parity error hardware table item or register be corrected and
Restore.
7. the network equipment according to claim 6, which is characterized in that
The configuration unit is also used to detect the corresponding hardware table item of the configuration data or the whether enabled odd even school of register
Test error correction；And
When the parity error correction function of detecting the corresponding hardware table item of the configuration data or register is enabled,
The configuration data is sent to cache module to back up.
8. the network equipment according to claim 6, which is characterized in that
There is odd even school for obtaining the configuration data in the hardware forwarding module in the parity error recovery unit
The location information of error checking accidentally, wherein the location information includes the call number or initial address of hardware table item or register；And
For inquiring corresponding storage location in the cache module according to the positional information, call in the cache module
Configuration data the configuration data in the hardware forwarding module is corrected and is restored.
9. the network equipment according to claim 8, which is characterized in that the processor module further include:
Recording unit, for being recorded to parity error event and correction event.
10. the network equipment according to claim 6, which is characterized in that
The configuration unit is turned for enabled control instruction will to be gone to be sent to the hardware forwarding module with disabling the hardware
Send out the parity error correction function of module；
Configuration data for parity error to will be present is sent to the hardware forwarding module；And
For sending enabled control instruction to the hardware forwarding module, the even-odd check to enable the hardware forwarding module is entangled
Wrong function；
The processor module further include:
Authentication unit, for being tested according to configuration data of the hardware forwarding module after parity error correction function is enabled
Demonstrate,prove whether the parity error is corrected reparation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611079584.1A CN106776107B (en) | 2016-11-30 | 2016-11-30 | A kind of parity error correction method and the network equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611079584.1A CN106776107B (en) | 2016-11-30 | 2016-11-30 | A kind of parity error correction method and the network equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106776107A CN106776107A (en) | 2017-05-31 |
| CN106776107B true CN106776107B (en) | 2019-07-16 |
Family
ID=58901170
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611079584.1A Active CN106776107B (en) | 2016-11-30 | 2016-11-30 | A kind of parity error correction method and the network equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106776107B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107317755B (en) * | 2017-08-23 | 2020-07-31 | 普联技术有限公司 | Hardware forwarding table entry error correction method and device and computer readable storage medium |
| CN108664352B (en) * | 2018-05-11 | 2022-07-12 | 卡斯柯信号有限公司 | Hot standby system education data verification method based on off-line simulation |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102904685A (en) * | 2012-09-29 | 2013-01-30 | 杭州华三通信技术有限公司 | Method and device for processing hardware table entry checking error |
| CN105700859A (en) * | 2014-11-25 | 2016-06-22 | 中兴通讯股份有限公司 | Network-processor-based hardware table traversal method and apparatus |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9419903B2 (en) * | 2012-11-08 | 2016-08-16 | Texas Instruments Incorporated | Structure for implementing openflow all group buckets using egress flow table entries |
-
2016
- 2016-11-30 CN CN201611079584.1A patent/CN106776107B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102904685A (en) * | 2012-09-29 | 2013-01-30 | 杭州华三通信技术有限公司 | Method and device for processing hardware table entry checking error |
| CN105700859A (en) * | 2014-11-25 | 2016-06-22 | 中兴通讯股份有限公司 | Network-processor-based hardware table traversal method and apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106776107A (en) | 2017-05-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20110219263A1 (en) | Fast cluster failure detection | |
| CN102890716B (en) | The data back up method of distributed file system and distributed file system | |
| CN106059791B (en) | Link switching method of service in storage system and storage device | |
| CN106463179A (en) | Method, apparatus and system for handling data error events with memory controller | |
| CN103795570B (en) | The unicast message restoration methods and device of the stacked switchboard system of ring topology | |
| US8775859B2 (en) | Method, apparatus and system for data disaster tolerance | |
| WO2017088572A1 (en) | Data processing method, device, and system | |
| CN106603279A (en) | Disaster tolerance method and disaster tolerance system | |
| CN104866234A (en) | Data migration method, device and system | |
| CN111078662A (en) | Block chain data storage method and device | |
| WO2016177231A1 (en) | Dual-control-based active-backup switching method and device | |
| CN103152390A (en) | Method and device and nodes and system for node configuration of distributed storage system | |
| CN106331166B (en) | A kind of access method and device of storage resource | |
| CN109491609A (en) | A kind of caching data processing method, device, equipment and readable storage medium storing program for executing | |
| CN106776107B (en) | A kind of parity error correction method and the network equipment | |
| US20210326211A1 (en) | Data backup method, apparatus, and system | |
| CN109167700B (en) | Detection method and device for Segment Routing (SR) tunnel | |
| CN102457400B (en) | Method for preventing split brain phenomenon from occurring on distributed replicated block device (DRBD) resource | |
| WO2021115043A1 (en) | Distributed database system and data disaster backup drilling method | |
| CN109815065B (en) | Main-standby switching method and device for dual computers and electronic equipment | |
| CN102664757A (en) | Cascading method and equipment for storage devices | |
| US8990619B1 (en) | Method and systems to perform a rolling stack upgrade | |
| CN113051428B (en) | Method and device for back-up storage at front end of camera | |
| CN107526652B (en) | Data synchronization method and storage device | |
| CN105159846A (en) | Method for supporting dual-control switching of virtualized disk and storage system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |