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CN106711220B - Fin field effect transistor and manufacturing method thereof - Google Patents

Fin field effect transistor and manufacturing method thereof Download PDF

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Publication number
CN106711220B
CN106711220B CN201610784601.5A CN201610784601A CN106711220B CN 106711220 B CN106711220 B CN 106711220B CN 201610784601 A CN201610784601 A CN 201610784601A CN 106711220 B CN106711220 B CN 106711220B
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Prior art keywords
fin
gate stack
semiconductor
insulators
finfet
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CN106711220A (en
Inventor
张哲诚
林志翰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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Abstract

A fin field effect transistor (FinFET) includes a substrate, a plurality of insulators disposed on the substrate, a gate stack, and a strained material. The substrate includes at least one semiconductor fin and the semiconductor fin includes at least one modulating portion distributed therein. The insulator sandwiches the semiconductor fin. The gate stack is disposed over a portion of the semiconductor fin and over a portion of the insulator. The strained material covers a portion of the semiconductor fin exposed by the gate stack. Further, a method for fabricating a FinFET is provided.

Description

Fin field effect transistor and manufacturing method thereof
Technical Field
Embodiments of the invention relate to integrated circuit devices, and more particularly, to fin field effect transistors and methods of fabricating the same.
Background
As semiconductor device dimensions continue to scale down, three-dimensional multi-gate structures such as fin field effect transistors (finfets) have evolved to replace planar Complementary Metal Oxide Semiconductor (CMOS) devices. The structural component of the FinFET is a silicon-based fin that extends vertically from the surface of the substrate, and the gate that wraps around the conductive channel formed by the fin further provides better electrical control of the channel.
During the fabrication of a FinFET, the fin profile is very important to the process window. Current FinFET processes may suffer from loading effects and fin bending problems.
Disclosure of Invention
An embodiment of the present invention provides a fin field effect transistor (FinFET), including: a substrate comprising at least one semiconductor fin comprising at least one modulating portion distributed in the semiconductor fin; a plurality of insulators disposed on the substrate, the insulators sandwiching the semiconductor fin; a gate stack disposed over a portion of the semiconductor fin and over a portion of the insulator; and a strained material covering a portion of the semiconductor fin exposed by the gate stack.
Another embodiment of the present invention provides a fin field effect transistor (FinFET), including: a substrate comprising a plurality of semiconductor fins including at least one active fin and a plurality of dummy fins disposed at two opposing sides of the active fin, the active fin including at least one modulation portion distributed in the active fin; a plurality of insulators disposed on the substrate, the semiconductor fins being insulated by the insulators; a gate stack disposed over a portion of the semiconductor fin and over a portion of the insulator; and a strained material covering a portion of the active fin exposed by the gate stack.
Yet another embodiment of the present invention provides a method for fabricating a fin field effect transistor (FinFET), including: providing a substrate comprising at least one modulating material distributed in the substrate; patterning the substrate to form trenches in the substrate and at least one semiconductor fin between the trenches, the semiconductor fin including at least one modulating portion distributed in the semiconductor fin; forming a plurality of insulators in the trenches; forming a gate stack over a portion of the semiconductor fin and over a portion of the insulator; and forming a strained material over portions of the active fin exposed by the gate stack.
Drawings
Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.
Fig. 1 is a flow diagram illustrating a method for fabricating a FinFET, according to some embodiments.
Fig. 2A-2H are perspective views of methods for fabricating finfets according to some embodiments.
Fig. 3A-3H are cross-sectional views of methods for fabricating finfets according to some embodiments.
Fig. 4-8 are cross-sectional views illustrating semiconductor fins according to some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include examples in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element (or other) component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Embodiments of the present invention describe exemplary fabrication processes for finfets and finfets fabricated therefrom. In some embodiments of the invention, finfets may be formed on a bulk silicon substrate. Still alternatively, the FinFET may be formed on a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. Also according to some embodiments, the silicon substrate may comprise other conductive layers or other semiconductor elements such as transistors, diodes, etc. The embodiments are not limited in this context.
Referring to fig. 1, a flow diagram illustrating a method for fabricating a FinFET in accordance with some embodiments of the present invention is shown. The method includes at least step S10, step S12, step S14, and step S16. First, in step S10, a substrate is provided and at least one semiconductor fin is formed thereon, wherein the semiconductor fin includes at least one modulating portion distributed therein. Thereafter, in step S12, an insulator is formed on the substrate and the semiconductor fin is sandwiched by the insulator. For example, the insulator is a Shallow Trench Isolation (STI) structure. Thereafter, in step S14, a gate stack is formed over a portion of the semiconductor fin and over a portion of the insulator; in step S16, a strained material is formed on a portion of the semiconductor fin. As shown in fig. 1, the strained material is formed after the formation of the gate stack. However, the order of forming the gate stack (step S14) and the strained material (step S16) is not limited to the present invention.
Fig. 2A is a perspective view of a FinFET of one at various stages of a fabrication method, and fig. 3A is a cross-sectional view of the FinFET taken along line I-I' of fig. 2A. In step S10 of fig. 1 and as shown in fig. 2A and 3A, a substrate 200 is provided. In one embodiment, substrate 200 comprises a crystalline silicon substrate (e.g., a wafer). The substrate 200 may include various doped regions according to design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, the doped region may be doped with a p-type or n-type dopant. For example, the doped region may be doped with a dopant such as boron or BF2A p-type dopant of (a); n-type dopants such as phosphorus or arsenic; and/or combinations thereof. The doped regions may be configured for n-type finfets or alternatively configured for p-type finfets. In some alternative implementations, the substrate 200 may be made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor such as silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide.
As shown in FIGS. 2A and 3A, substrate 200 includes two modulating materials M1 and M2 distributed therein, where modulating materials M1 and M2 are implanted regions formed by ion implantation or semiconductor layers formed by atomic layer deposition (A L D), for examplex，0<x), silicon germanium (SiGe), silicon oxide (SiO)x，0<x), silicon phosphide (SiP), silicon phosphate (SiPO)x，0<x<1) Or they may beCombinations of (a) and (b). For example, the thickness of modulating material M1 ranges from about 1nm to about 50nm, and the thickness of modulating material M2 ranges from about 1nm to about 50 nm. In some embodiments, by appropriately controlling the implant dose and implant depth, the modulating materials M1, M2 may be formed at different locations of the substrate 200 by ion implantation. In some alternative embodiments, an epitaxial layer (e.g., a silicon epitaxial layer) between deposited modulating materials M1 and M2 may be formed by an epitaxial process.
In one embodiment, a pad layer 202a and a mask layer 202b are sequentially formed on a substrate 200. for example, pad layer 202a may be a silicon oxide film formed by a thermal oxidation process.pad layer 202a may serve as an adhesion layer between substrate 200 and mask layer 202 b. pad layer 202a may also serve as an etch stop layer for etching mask layer 202 b. in at least one embodiment, mask layer 202b is a silicon nitride layer formed by low pressure chemical vapor deposition (L PCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD). mask layer 202b serves as a hard mask during a subsequent photolithography process.A patterned photoresist layer 204 having a predetermined pattern is formed on mask layer 202 b.
Fig. 2B is a perspective view of a FinFET of one at various stages of a fabrication method, and fig. 3B is a cross-sectional view of the FinFET taken along line I-I' of fig. 2B. In step S10 of fig. 1 and as shown in fig. 2A-2B and 3A-3B, mask layer 202B and underlayer 202A, which are not covered by patterned photoresist layer 204, are sequentially etched to form patterned mask layer 202B 'and patterned underlayer 202A' to expose underlying substrate 200. Using patterned mask layer 202b ', patterned pad layer 202 a', and patterned photoresist layer 204 as a mask, portions of substrate 200 are exposed and etched to form trenches 206 and semiconductor fins 208. The semiconductor fin 208 is covered by the patterned mask layer 202b ', the patterned pad layer 202 a', and the patterned photoresist layer 204. Two adjacent trenches 206 are spaced apart by a spacing S. For example, the spacing S between the trenches 206 may be less than about 30 nm. In other words, two adjacent trenches 206 are spaced apart by a respective semiconductor fin 208.
The height of the semiconductor fin 208 and the depth of the trench 206 range from about 5nm to about 500 nm. After forming the trench 206 and the semiconductor fin 208, the patterned photoresist layer 204 is then removed. In one embodiment, a cleaning process may be performed to remove native oxide of the semiconductor substrate 200a and the semiconductor fin 208. The cleaning process may be performed using Dilute Hydrofluoric (DHF) acid or other suitable cleaning solution.
After performing the above-described fin etch process, a semiconductor fin 208 including two modulated portions MP1 and MP2 distributed therein is formed over the substrate 200 a. The material and thickness of the modulating portions MP1 and MP2 are substantially the same as the material and thickness of the modulating materials M1 and M2. However, the number of the modulated parts MP1 and MP2 is not limited to the present invention. For example, each semiconductor fin 208 may have one or more than two modulated portions. For example, the minimum distance between modulating portion MP1 and substrate 200a ranges from 500nm to 1000nm and the minimum distance between modulating portion MP2 and substrate 200a ranges from 5nm to 500 nm. Furthermore, the locations of portions MP1 and MP2 are not limiting of the present invention. The number and location of the modulated portions in the semiconductor fin 208 may be varied by one skilled in the art according to design requirements.
Modulating portions MP1 and MP2 may modulate or stabilize the characteristics of semiconductor fin 208. For example, modulating portions MP1 and MP2 help control fin height, stress, electrical characteristics, and the like. Thus, the semiconductor fin 208 having the modulated portions MP1 and MP2 therein may improve Wafer Analysis and Testing (WAT) results.
As shown in fig. 2B and 3B, the semiconductor fins 208 include at least one active fin 208A and a pair of dummy fins 208D disposed at both sides of the active fin 208A. In other words, one dummy fin 208D is disposed on one side of active fin 208A and another dummy fin 208D is disposed on the other side of active fin 208A. In some embodiments, the height of the active fin 208A and the height of the dummy fin 208D are substantially the same. For example, the height of active fin 208A and dummy fin 208D is between about 10 angstroms and about 100 angstroms. Dummy fins 208D may protect active fins 208A from fin bending issues caused by a continuous deposition process. Furthermore, dummy fins 208D may protect active fins 208A from the severe effects of loading effects during the fin etch process.
Fig. 2C is a perspective view of a FinFET of one at various stages of a fabrication method, and fig. 3C is a cross-sectional view of the FinFET taken along line I-I' of fig. 2C. In step S12 of fig. 1 and as shown in fig. 2B-2C and 3B-3C, an insulating material 210 is formed over the substrate 200a to cover the semiconductor fin 208 and fill the trench 206. In addition to semiconductor fin 208, insulating material 210 further covers patterned pad layer 202a 'and patterned mask layer 202 b'. The insulating material 210 may comprise silicon oxide, silicon nitride, silicon oxynitride, a spin-on dielectric material, or a low-k dielectric material. The insulating material 210 may be formed by high density plasma chemical vapor deposition (HPD-CVD), sub-atmospheric pressure CVD (sacvd), or spin coating.
Fig. 2D is a perspective view of a FinFET of one at various stages of a fabrication method, and fig. 3D is a cross-sectional view of the FinFET taken along line I-I' of fig. 2D. In step S12 of fig. 1 and as shown in fig. 2C-2D and 3C-3D, for example, a chemical mechanical polishing process is performed to remove portions of the insulating material 210, the patterned masking layer 202b ', and the patterned pad layer 202 a' until the semiconductor fin 208 is exposed. As shown in fig. 2D and 3D, after polishing insulating material 210, the top surface of polished insulating material 210 is substantially coplanar with top surface T2 of the semiconductor fin.
Fig. 2E is a perspective view of a FinFET of one at various stages of a fabrication method, and fig. 3E is a cross-sectional view of the FinFET taken along line I-I' of fig. 2E. In step S12 of fig. 1 and as shown in fig. 2D to 2E and 3D to 3E, the polished insulating material 210 filled in the trench 206 is partially removed by an etching process, so that insulators 210a are formed on the substrate 200a and each insulator 210a is located between two adjacent semiconductor fins 208. In one embodiment, the etching process may be a wet etching process or a dry etching process using hydrofluoric acid (HF). The top surface T1 of the insulator 210a is lower than the top surface T2 of the semiconductor fin 208. Semiconductor fin 208 protrudes above top surface T1 of insulator 210 a. The height difference between the top surface T2 of fin 208 and the top surface T1 of insulator 210a is H, and the height difference H ranges from about 15nm to about 50 nm.
As shown in fig. 2E and 3E, the modulation portion MP2 in the semiconductor fin 208 and between the top surface T1 of the insulator 210a and the top surface T2 of the semiconductor fin 208 is exposed. The modulated portion MP1 in semiconductor fin 208 is encapsulated by insulator 210 a.
Fig. 2F is a perspective view of a FinFET of one at various stages of a fabrication method, and fig. 3F is a cross-sectional view of the FinFET taken along line I-I' of fig. 2F. In step S14 of fig. 1 and as shown in fig. 2E-2F and 2F-3F, a gate stack 212 is formed over a portion of semiconductor fin 208 and a portion of insulator 210 a. In one embodiment, for example, the extending direction D1 of the gate stack 212 is perpendicular to the extending direction D2 of the semiconductor fin 208, thereby covering the middle M of the semiconductor fin 208 (as shown in fig. 3F). The middle portion M described above may serve as the channel of a tri-gate FinFET. The gate stack 212 includes a gate dielectric layer 212a and a gate electrode layer 212b disposed over the gate dielectric layer 212 a. A gate dielectric layer 212a is disposed over a portion of the semiconductor fin 208 and over a portion of the insulator 210 a.
The gate dielectric layer 212a is formed to cover a central portion M of the semiconductor fin 208. in some embodiments, the gate dielectric layer 212a may include silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric.the high-k dielectric includes a metal oxide examples of metal oxides for the high-k dielectric include oxides of L i, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, L a, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, L u, or mixtures thereof.
The gate electrode layer 212b may comprise polysilicon, or a metal such as Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi, other conductive materials having a work function compatible with the substrate material, or combinations thereof in some embodiments, the gate electrode layer 212b comprises a silicon-containing material such as polysilicon, amorphous silicon, or combinations thereof, and the gate electrode layer 212b is formed prior to the formation of the strained material 214. in alternative embodiments, the gate electrode layer 212b is a dummy gate and the dummy gate is replaced by a metal gate (or "replacement gate") after the formation of the strained material 214. in some embodiments, the gate electrode layer 212b comprises a thickness in the range of about 30nm to about 60 nm.
In addition, the gate stack 212 may further include a pair of spacers 212c disposed on sidewalls of the gate dielectric layer 212a and the gate electrode layer 212 b. The pair of spacers 212c may also cover a portion of the semiconductor fin 208. The spacers 212c are formed of a dielectric material such as silicon nitride or SiCON. The spacer 212c may include a single layer or a multi-layer structure. The portion of the semiconductor fin 208 not covered by the gate stack 212 is referred to as an exposed portion E hereinafter.
Fig. 2G is a perspective view of a FinFET of one at various stages of a fabrication method, and fig. 3G is a cross-sectional view of the FinFET taken along line II-II' of fig. 2G. In step S16 of fig. 1 and as shown in fig. 2F-2G and 3F-3G, the exposed portion E of the semiconductor fin 208 is removed and the exposed portion E of the semiconductor fin 208 is recessed to form a recessed portion R. The exposed portions E are removed, for example, by anisotropic etching, isotropic etching, or a combination thereof. In some embodiments, exposed portion E of semiconductor fin 208 is recessed below top surface T1 of insulator 210 a. The depth D of the recessed portion R is smaller than the thickness TH of the insulator 210 a. In other words, the exposed portion E of the semiconductor fin 208 is not entirely removed. As shown in fig. 2G and 3G, when the exposed portion E of the semiconductor fin 208 is recessed, a portion of the semiconductor fin 208 covered by the gate stack 212 is not removed. Portions of the semiconductor fin 208 covered by the gate stack 212 are exposed at sidewalls of the gate stack 212.
When the exposed portion E of the semiconductor fin 208 is removed and the exposed portion E of the semiconductor fin 208 is recessed to form the recessed portion R, the modulated portion MP1 (as shown in fig. 2F and 2G) not covered by the gate stack 212 may be used as an etch stop layer to well control the profile of the recessed portion R. During the recess process described above, the modulation portion MP1 not covered by the gate stack 212 may be completely removed. In some alternative embodiments, the recess process described above may stop at the modulation portion MP1 and the modulation portion MP1 not covered by the gate stack 212 remains. Since the modulated portion MP1 helps to well control the profile of the recess R, the subsequent epitaxial growth of the strained material may also be well controlled. Accordingly, the process window of the subsequent epitaxial process is enlarged.
Fig. 2H is a perspective view of a FinFET of one at various stages of a fabrication method, and fig. 3H is a cross-sectional view of the FinFET taken along line II-II' of fig. 2H. In step S16 of fig. 1 and as shown in fig. 2G-2H and 3G-3H, the strained material 214 is selectively grown over the recessed portion R of the semiconductor fin 208 and extends over the top surface T1 of the insulator 210a to strain or stress the semiconductor fin 208.
As shown in fig. 2H and 3H, the strained material 214 includes a source disposed at one side of the gate stack 212 and a drain disposed at the other side of the gate stack 212. The source covers one end of the semiconductor fin 208 and the drain covers the other end of the semiconductor fin 208. In this case, the dummy fin 208D may be electrically grounded through the strained material 214 overlying it.
In some embodiments, the source and drain may only cover the two ends (i.e., the first and second ends) of the active fin 208A exposed by the gate stack 212, and the dummy fin 208D is not covered by the strained material 214. in this case, the dummy fin 208D is electrically floating because the lattice constant of the strained material 214 is different from the lattice constant of the substrate 200a, the portion of the semiconductor fin 208 covered by the gate stack 212 is strained or stressed to enhance carrier mobility and performance of the FinFET finfet.in one embodiment, the strained material 214, such as silicon carbide (SiC), is epitaxially grown by an L PCVD process to form the source and drain of an n-type finfet.in another embodiment, the strained material 214, such as silicon germanium (SiGe), is epitaxially grown by a L PCVD process to form the source and drain of a p-type FinFET.
In the FinFET of the present invention, the active fin 208A includes a channel covered by the gate stack 212 when the drive voltage is biased to the gate stack 212. Dummy fin 208D is electrically floating or electrically grounded. In other words, although the gate stack 212 and the dummy fin 208D partially overlap, the dummy fin 208D does not serve as a channel of the transistor.
During fabrication of the FinFET, the dummy fin 208D suffers from fin bending issues (i.e., CVD stress effects) and the active fin 208A is not significantly affected by the fin bending issues. Furthermore, due to the formation of dummy fins 208D, active fins 208A are not significantly affected by loading effects and fin bending issues. The dummy fins 208D may enlarge the process window for the epitaxial process of the strained material 214 (strained source/drain) and provide better critical dimension loading. Accordingly, the FinFET including dummy fins 208D has better Wafer Analysis and Testing (WAT) results, better reliability performance, and better manufacturing performance.
Referring back to fig. 2A and 3A, the semiconductor fins 208 shown include at least one active fin 208A and a pair of dummy fins 208D. However, the number of active fins 208A and dummy fins 208D is not limited to the present invention. In addition, the height of dummy fin 208D may also be modified. Modified embodiments are described in conjunction with fig. 4 through 8.
Referring to fig. 4, illustrated is a cross-sectional view of a semiconductor fin according to some embodiments. The semiconductor fins 208 include a set of active fins 208A (e.g., two active fins) and two dummy fins 208D. One dummy fin 208D is disposed at one side of the set of active fins 208A and another second dummy fin 208D is disposed at the other side of the set of active fins 208A. In some alternative embodiments, the number of active fins 208A may be more than two.
Referring to fig. 5, illustrated is a cross-sectional view of a semiconductor fin according to some embodiments. The semiconductor fins 208 include a set of active fins 208A (e.g., two active fins) and four dummy fins 208D. Two first dummy fins 208D are disposed at one side of the set of active fins 208A and two other second dummy fins 208D are disposed at the other side of the set of active fins 208A. In some alternative embodiments, the number of active fins 208A may be more than two and the number of dummy fins 208D may be three or more than four. The active fin 208A may serve as a channel for a single FinFET or a channel for multiple finfets.
Referring to fig. 6, illustrated is a cross-sectional view of a semiconductor fin according to some embodiments. The semiconductor fin 208 includes one active fin 208A and two dummy fins 208D disposed at two opposite sides of the active fin 208A. Height H1 of active fin 208A is greater than height H2 of dummy fin 208D.
Referring to fig. 7, illustrated is a cross-sectional view of a semiconductor fin according to some embodiments. The semiconductor fin 208 includes two active fins 208A and four dummy fins 208D disposed at two opposite sides of the active fins 208A. Height H1 of active fin 208A is greater than height H2 of dummy fin 208D. In some alternative embodiments, the number of active fins 208A may be more than two and the number of dummy fins 208D may be three or more than four.
In some alternative embodiments, as shown in fig. 6 and 7, height H2 of dummy fin 208D is less than thickness TH of insulator 210 a. Accordingly, dummy fin 208D is buried in partial insulator 210 a. Dummy fins 208D are fabricated by a fin cutting process. A fin cut process may be performed prior to forming the insulator 210a, thereby removing the top of the dummy fin 208D to reduce the height of the dummy fin 208D. For example, the fin cut process may be an etch process. The fin bending problem (i.e., CVD stress effects) experienced by the shorter dummy fins 208D may be significantly reduced.
Referring to fig. 8, illustrated is a cross-sectional view of a semiconductor fin according to some embodiments. Unlike the embodiments illustrated in fig. 4 to 7, the semiconductor fin 208 illustrated in fig. 8 includes three active fins 208A, and dummy fins are not formed. The number of active fins 208A may be modified according to design requirements.
According to some embodiments of the present invention, a FinFET includes a substrate, a plurality of insulators disposed on the substrate, a gate stack, and a strained material. The substrate includes at least one semiconductor fin and the semiconductor fin includes at least one modulating portion distributed therein. The insulator sandwiches the semiconductor fin. A gate stack is disposed over a portion of the semiconductor fin and over a portion of the insulator. The strained material covers a portion of the semiconductor fin exposed by the gate stack.
In the above FinFET, wherein the modulation portion comprises a semiconductor layer, and a material of the semiconductor layer comprises silicon germanium oxide (SiGeO)x) Silicon germanium (SiGe), silicon oxide (SiO)x) Silicon phosphide (SiP), silicon phosphate (SiPO)x) Or a combination thereof.
In the above FinFET, wherein the modulation portion comprises an implanted region, and a material of the implanted region comprises silicon germanium oxide (SiGeO)x) Silicon germanium (SiGe), silicon oxide (SiO)x) Silicon phosphide (SiP), silicon phosphate (SiPO)x) Or a combination thereof.
In the above FinFET, wherein the at least one modulation section comprises: a first modulation section; and a second modulation portion, the first modulation portion and the second modulation portion distributed in different locations of the semiconductor fin.
In the above FinFET, wherein the strained material comprises a source and a drain, the source covering a first end of the active fin, the drain covering a second end of the active fin, the first and second ends being exposed by the gate stack, the source and drain being located at two opposite sides of the gate stack, respectively.
In the above FinFET, wherein the active fin comprises a plurality of recesses revealed by the gate stack, and the strained material covers the recesses of the active fin.
In accordance with an alternative embodiment of the present invention, a FinFET includes a substrate, a plurality of insulators disposed on the substrate, a gate stack, and a strained material. The substrate includes a plurality of semiconductor fins. The semiconductor fin includes at least one active fin and a plurality of dummy fins disposed at two opposite sides of the active fin. The active fin includes at least one modulating portion distributed therein. An insulator is disposed on the substrate and the semiconductor fins are insulated by the insulator. A gate stack is disposed over a portion of the semiconductor fin and over a portion of the insulator. The strained material covers a portion of the active fin exposed by the gate stack.
In the above FinFET, wherein the modulation portion comprises a semiconductor layer, and a material of the semiconductor layer comprises silicon germanium oxide (SiGeO)x) Silicon germanium (SiGe), silicon oxide (SiO)x) Silicon phosphide (SiP), silicon phosphate (SiPO)x) Or a combination thereof.
In the above FinFET, wherein the modulation portion comprises an implanted region, and a material of the implanted region comprises silicon germanium oxide (SiGeO)x) Silicon germanium (SiGe), silicon oxide (SiO)x) Silicon phosphide (SiP), silicon phosphate (SiPO)x) Or a combination thereof.
In the above FinFET, wherein a height of the active fin is the same as a height of the dummy fin.
In the above FinFET, wherein a height of the active fin is greater than a height of the dummy fin.
In the above FinFET, wherein a height of the active fin is greater than a height of the dummy fin, the dummy fin is buried in a portion of the insulator.
In the above FinFET, wherein the dummy fin is electrically grounded or electrically floating.
In the above FinFET, wherein the at least one modulation section comprises: a first modulation section; and a second modulation portion, the first modulation portion and the second modulation portion being distributed at different locations of the semiconductor fin.
In the above FinFET, wherein the strained material comprises a source and a drain, the source covering a first end of the active fin, the drain covering a second end of the active fin, the first and second ends being exposed by the gate stack, the source and drain being located at two opposite sides of the gate stack, respectively.
In the above FinFET, wherein the active fin comprises a plurality of recesses revealed by the gate stack, and the strained material covers the recesses of the active fin.
According to yet another alternative embodiment of the present invention, a method for fabricating a FinFET includes at least the following steps. At least one semiconductor fin is formed on a substrate, wherein the semiconductor fin includes at least one modulating portion distributed therein. A plurality of insulators are formed on a substrate, wherein the insulators sandwich a semiconductor fin. A gate stack is formed over a portion of the semiconductor fin and over a portion of the insulator. A strained material is formed over portions of the active fin exposed by the gate stack.
In the above method, wherein the modulation portion is formed in the semiconductor fin by an implantation process or a deposition process.
In the above method, wherein the method for manufacturing the modulation material distributed in the substrate is performed by ion implantation or atomic layer deposition.
In the above method, further comprising: partially removing portions of the semiconductor fin exposed by the gate stack to form a plurality of recessed portions, wherein the strained material covers the recessed portions of the active fin.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced by oneself. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (19)

1. A fin field effect transistor (FinFET), comprising:
a substrate comprising at least one semiconductor fin comprising a plurality of fin portions made of a same material and at least one modulation portion separating every two adjacent fin portions of the plurality of fin portions;
a plurality of insulators disposed on the substrate, the plurality of insulators sandwiching the semiconductor fin, wherein the at least one modulation section includes a first modulation section located above top surfaces of the plurality of insulators and a second modulation section located below the top surfaces of the plurality of insulators;
a gate stack disposed over a portion of the at least one semiconductor fin and over a portion of the plurality of insulators, wherein the gate stack covers the plurality of fin portions and the at least one modulation portion made of the same material; and
a strained material covering a portion of the at least one semiconductor fin exposed by the gate stack.
2. The fin-type field effect transistor of claim 1, wherein the at least one modulating portion comprises a semiconductor layer, and a material of the semiconductor layer comprises silicon germanium oxide (SiGeO)x) Silicon germanium (SiGe), silicon oxide (SiO)x) Silicon phosphide (SiP), silicon phosphate (SiPO)x) Or a combination thereof.
3. The fin-type field effect transistor of claim 1, wherein the at least one modulation portion comprises an implant region, and a material of the implant region comprises silicon germanium oxide (SiGeO)x) Silicon germanium (SiGe), silicon oxide (SiO)x) Silicon phosphide (SiP), silicon phosphate (SiPO)x) Or a combination thereof.
4. The fin-type field effect transistor of claim 1, wherein the strained material comprises a source overlying a first end of an active fin and a drain overlying a second end of the active fin, the first and second ends being exposed by the gate stack, the source and drain being located at two opposing sides of the gate stack, respectively.
5. The fin-type field effect transistor of claim 1, wherein the active fin includes a plurality of recesses exposed by the gate stack, and the strained material covers the plurality of recesses of the active fin.
6. A fin field effect transistor (FinFET), comprising:
a substrate comprising a plurality of semiconductor fins including at least one active fin and a plurality of dummy fins disposed at two opposing sides of the at least one active fin, the at least one active fin comprising a plurality of active fin portions made of a same material and at least one modulation portion separating every two adjacent active fin portions of the plurality of active fin portions;
a plurality of insulators disposed on the substrate, the plurality of semiconductor fins being insulated by the plurality of insulators, wherein the at least one modulation section includes a first modulation section located above top surfaces of the plurality of insulators and a second modulation section located below the top surfaces of the plurality of insulators;
a gate stack disposed over a portion of the plurality of semiconductor fins and over a portion of the plurality of insulators, wherein the gate stack covers the plurality of active fin portions and the at least one modulation portion made of the same material; and
a strained material covering a portion of the at least one active fin exposed by the gate stack.
7. The fin-type field effect transistor of claim 6, wherein the at least one modulating portion comprises a semiconductor layer, and a material of the semiconductor layer comprises silicon germanium oxide (SiGeO)x) Silicon germanium (SiGe), silicon oxide (SiO)x) Silicon phosphide (SiP), silicon phosphate (SiPO)x) Or a combination thereof.
8. The fin-type field effect transistor of claim 6, wherein the at least one modulation portion comprises an implant region, and a material of the implant region comprises silicon germanium oxide (SiGeO)x) Silicon germanium (SiGe), silicon oxide (SiO)x) Silicon phosphide (SiP), silicon phosphate (SiPO)x) Or a combination thereof.
9. The FinFET of claim 6, wherein a height of the at least one active fin is the same as a height of the plurality of dummy fins.
10. The FinFET of claim 6, wherein a height of the at least one active fin is greater than a height of the plurality of dummy fins.
11. The finfet of claim 10, wherein the plurality of dummy fins are buried in a portion of the plurality of insulators.
12. The FinFET of claim 6, wherein the plurality of dummy fins are electrically grounded or electrically floating.
13. The FinFET of claim 6, wherein the first and second modulating portions are distributed at different locations of the semiconductor fin.
14. The fin field effect transistor of claim 6, wherein the strained material comprises a source overlying a first end of the at least one active fin and a drain overlying a second end of the at least one active fin, the first and second ends being exposed by the gate stack, the source and drain being located at two opposing sides of the gate stack, respectively.
15. The fin-type field effect transistor of claim 6, wherein the at least one active fin includes a plurality of recesses exposed by the gate stack, and the strained material covers the plurality of recesses of the at least one active fin.
16. A method for fabricating a fin field effect transistor (FinFET), comprising:
providing a substrate comprising at least one modulating material distributed in the substrate;
patterning the substrate to form trenches in the substrate and at least one semiconductor fin between the trenches, the at least one semiconductor fin including a plurality of fin portions made of a same material and at least one modulation portion that separates every two adjacent fin portions of the plurality of fin portions;
forming a plurality of insulators in the trenches, wherein the at least one modulation section includes a first modulation section located above top surfaces of the plurality of insulators and a second modulation section located below the top surfaces of the plurality of insulators;
forming a gate stack over a portion of the at least one semiconductor fin and over a portion of the plurality of insulators, wherein the gate stack covers the plurality of fin portions and the at least one modulation portion made of the same material; and
a strained material is formed over portions of the active fin exposed by the gate stack.
17. The method of claim 16, wherein the at least one modulating portion is formed in the at least one semiconductor fin by an implantation process or a deposition process.
18. The method of claim 16, wherein the method for fabricating the at least one modulating material distributed in the substrate is achieved by ion implantation or atomic layer deposition.
19. The method of claim 16, further comprising:
partially removing portions of the at least one semiconductor fin exposed by the gate stack to form a plurality of recesses, wherein the strained material covers the plurality of recesses of the active fin.
CN201610784601.5A 2015-11-16 2016-08-31 Fin field effect transistor and manufacturing method thereof Active CN106711220B (en)

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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105336579B (en) * 2015-09-29 2018-07-10 安徽三安光电有限公司 A kind of semiconductor element and preparation method thereof
CN106611787A (en) * 2015-10-26 2017-05-03 联华电子股份有限公司 A semiconductor structure and a manufacturing method thereof
US20170140992A1 (en) * 2015-11-16 2017-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor and method for fabricating the same
US9960273B2 (en) * 2015-11-16 2018-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure with substrate isolation and un-doped channel
US10115807B2 (en) * 2015-11-18 2018-10-30 Globalfoundries Inc. Method, apparatus and system for improved performance using tall fins in finFET devices
US9842929B1 (en) * 2016-06-09 2017-12-12 International Business Machines Corporation Strained silicon complementary metal oxide semiconductor including a silicon containing tensile N-type fin field effect transistor and silicon containing compressive P-type fin field effect transistor formed using a dual relaxed substrate
US9812363B1 (en) 2016-11-29 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of forming same
US10020398B1 (en) * 2017-01-11 2018-07-10 International Business Machines Corporation Stress induction in 3D device channel using elastic relaxation of high stress material
US10720516B2 (en) * 2017-06-30 2020-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Gate stack structure and method for forming the same
US10644030B2 (en) * 2017-10-20 2020-05-05 Mediatek Inc. Integrated circuit and cell structure in the integrated circuit
WO2019116827A1 (en) * 2017-12-12 2019-06-20 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device and method for manufacturing same
US10332999B1 (en) * 2018-03-09 2019-06-25 International Business Machines Corporation Method and structure of forming fin field-effect transistor without strain relaxation
US10861969B2 (en) * 2018-07-16 2020-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming FinFET structure with reduced Fin buckling

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103474397A (en) * 2012-06-06 2013-12-25 台湾积体电路制造股份有限公司 Method of making a FINFET device
CN104241361A (en) * 2013-06-12 2014-12-24 台湾积体电路制造股份有限公司 Semiconductor device with strain technique
US9023705B1 (en) * 2013-11-01 2015-05-05 Globalfoundries Inc. Methods of forming stressed multilayer FinFET devices with alternative channel materials

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6756643B1 (en) 2003-06-12 2004-06-29 Advanced Micro Devices, Inc. Dual silicon layer for chemical mechanical polishing planarization
KR100487566B1 (en) * 2003-07-23 2005-05-03 삼성전자주식회사 Fin field effect transistors and methods of formiing the same
KR100674914B1 (en) * 2004-09-25 2007-01-26 삼성전자주식회사 MOS transistor having strained channel layer and methods of manufacturing thereof
US7795669B2 (en) * 2007-05-30 2010-09-14 Infineon Technologies Ag Contact structure for FinFET device
US20090050975A1 (en) * 2007-08-21 2009-02-26 Andres Bryant Active Silicon Interconnect in Merged Finfet Process
JP2010040630A (en) * 2008-08-01 2010-02-18 Toshiba Corp Semiconductor device
US8440517B2 (en) * 2010-10-13 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of fabricating the same
US20110079861A1 (en) * 2009-09-30 2011-04-07 Lucian Shifren Advanced Transistors with Threshold Voltage Set Dopant Structures
US8941153B2 (en) * 2009-11-20 2015-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with different fin heights
US8373238B2 (en) * 2009-12-03 2013-02-12 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with multiple Fin heights
US8283653B2 (en) * 2009-12-23 2012-10-09 Intel Corporation Non-planar germanium quantum well devices
US8575653B2 (en) * 2010-09-24 2013-11-05 Intel Corporation Non-planar quantum well device having interfacial layer and method of forming same
US9287385B2 (en) * 2011-09-01 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-fin device and method of making same
US20130200455A1 (en) 2012-02-08 2013-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Dislocation smt for finfet device
US8865560B2 (en) * 2012-03-02 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET design with LDD extensions
US8853037B2 (en) * 2012-03-14 2014-10-07 GlobalFoundries, Inc. Methods for fabricating integrated circuits
US9054212B2 (en) * 2012-10-30 2015-06-09 Globalfoundries Inc. Fin etch and Fin replacement for FinFET integration
US8900958B2 (en) * 2012-12-19 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial formation mechanisms of source and drain regions
US8846490B1 (en) * 2013-03-12 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a FinFET device
US9236444B2 (en) * 2013-05-03 2016-01-12 Samsung Electronics Co., Ltd. Methods of fabricating quantum well field effect transistors having multiple delta doped layers
US20140353767A1 (en) * 2013-05-31 2014-12-04 Stmicroelectronics, Inc. Method for the formation of fin structures for finfet devices
US9293534B2 (en) * 2014-03-21 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of dislocations in source and drain regions of FinFET devices
US8987094B2 (en) * 2013-07-09 2015-03-24 GlobalFoundries, Inc. FinFET integrated circuits and methods for their fabrication
US9202918B2 (en) * 2013-09-18 2015-12-01 Globalfoundries Inc. Methods of forming stressed layers on FinFET semiconductor devices and the resulting devices
US9184089B2 (en) * 2013-10-04 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanism of forming a trench structure
US9093302B2 (en) * 2013-11-13 2015-07-28 Globalfoundries Inc. Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices
US20150171217A1 (en) * 2013-12-12 2015-06-18 Texas Instruments Incorporated Design and integration of finfet device
US9136356B2 (en) * 2014-02-10 2015-09-15 Taiwan Semiconductor Manufacturing Co., Ltd. Non-planar field effect transistor having a semiconductor fin and method for manufacturing
US9412822B2 (en) * 2014-03-07 2016-08-09 Globalfoundries Inc. Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103474397A (en) * 2012-06-06 2013-12-25 台湾积体电路制造股份有限公司 Method of making a FINFET device
CN104241361A (en) * 2013-06-12 2014-12-24 台湾积体电路制造股份有限公司 Semiconductor device with strain technique
US9023705B1 (en) * 2013-11-01 2015-05-05 Globalfoundries Inc. Methods of forming stressed multilayer FinFET devices with alternative channel materials

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